From f42b3c3b87bcffdf702a965d880569972333be65 Mon Sep 17 00:00:00 2001 From: Ken Sloat Date: Wed, 19 Jul 2023 12:19:56 -0400 Subject: [PATCH] imx93-var-som: Add support for additional M33 examples This change adds support for the following new examples: driver_examples/canfd/loopback driver_examples/canfd/loopback_transfer driver_examples/edma/memory_to_memory driver_examples/edma/scatter_gather driver_examples/edma4/channel_link driver_examples/edma4/interleave_transfer driver_examples/edma4/memory_to_memory driver_examples/edma4/memory_to_memory_transfer driver_examples/edma4/memset driver_examples/edma4/ping_pong_transfer driver_examples/edma4/scatter_gather driver_examples/edma4/wrap_transfer driver_examples/flexcan/loopback driver_examples/flexcan/loopback_edma_transfer driver_examples/flexcan/loopback_transfer driver_examples/lpit/chained_channel driver_examples/lpit/single_channel driver_examples/lptmr driver_examples/lpuart/interrupt driver_examples/lpuart/interrupt_rb_transfer driver_examples/lpuart/interrupt_transfer driver_examples/lpuart/polling driver_examples/tpm/input_capture driver_examples/tpm/output_compare driver_examples/tpm/simple_pwm driver_examples/tpm/timer driver_examples/tstmr multicore_examples/rpmsg_lite_pingpong_rtos multicore_examples/rpmsg_lite_str_echo_rtos rtos_examples/freertos_event rtos_examples/freertos_generic rtos_examples/freertos_hello rtos_examples/freertos_mutex rtos_examples/freertos_queue rtos_examples/freertos_sem rtos_examples/freertos_swtimer Signed-off-by: Ken Sloat --- .../demo_apps/ethosu_apps_rpmsg/board.c | 150 ------- .../demo_apps/ethosu_apps_rpmsg/board.h | 58 --- .../demo_apps/ethosu_apps_rpmsg/pin_mux.c | 8 +- boards/som_mx93/demo_apps/hello_world/board.c | 150 ------- boards/som_mx93/demo_apps/hello_world/board.h | 58 --- .../som_mx93/demo_apps/hello_world/pin_mux.c | 4 +- .../som_mx93/demo_apps/hello_world/readme.txt | 15 +- .../canfd/loopback/armgcc/CMakeLists.txt | 111 +++++ .../loopback/armgcc/MIMX9352_cm33_ram.ld | 246 +++++++++++ .../canfd/loopback/armgcc/build_all.bat | 15 + .../canfd/loopback/armgcc/build_all.sh | 15 + .../canfd/loopback/armgcc/build_debug.bat | 6 + .../canfd/loopback/armgcc/build_debug.sh | 7 + .../canfd/loopback/armgcc/build_release.bat | 6 + .../canfd/loopback/armgcc/build_release.sh | 7 + .../canfd/loopback/armgcc/clean.bat | 3 + .../canfd/loopback/armgcc/clean.sh | 3 + .../canfd/loopback/armgcc/config.cmake | 2 + .../canfd/loopback/armgcc/flags.cmake | 187 +++++++++ .../driver_examples/canfd/loopback/board.c | 152 +++++++ .../driver_examples/canfd/loopback/board.h | 71 ++++ .../canfd/loopback/clock_config.c | 97 +++++ .../canfd/loopback/clock_config.h | 29 ++ .../canfd/loopback/flexcan_loopback.c | 298 +++++++++++++ .../driver_examples/canfd/loopback/pin_mux.c | 87 ++++ .../driver_examples/canfd/loopback/pin_mux.h | 54 +++ .../driver_examples/canfd/loopback/readme.txt | 69 +++ .../loopback_transfer/armgcc/CMakeLists.txt | 111 +++++ .../armgcc/MIMX9352_cm33_ram.ld | 246 +++++++++++ .../loopback_transfer/armgcc/build_all.bat | 15 + .../loopback_transfer/armgcc/build_all.sh | 15 + .../loopback_transfer/armgcc/build_debug.bat | 6 + .../loopback_transfer/armgcc/build_debug.sh | 7 + .../armgcc/build_release.bat | 6 + .../loopback_transfer/armgcc/build_release.sh | 7 + .../canfd/loopback_transfer/armgcc/clean.bat | 3 + .../canfd/loopback_transfer/armgcc/clean.sh | 3 + .../loopback_transfer/armgcc/config.cmake | 2 + .../loopback_transfer/armgcc/flags.cmake | 187 +++++++++ .../canfd/loopback_transfer/board.c | 152 +++++++ .../canfd/loopback_transfer/board.h | 71 ++++ .../canfd/loopback_transfer/clock_config.c | 97 +++++ .../canfd/loopback_transfer/clock_config.h | 29 ++ .../flexcan_loopback_transfer.c | 269 ++++++++++++ .../canfd/loopback_transfer/pin_mux.c | 87 ++++ .../canfd/loopback_transfer/pin_mux.h | 54 +++ .../canfd/loopback_transfer/readme.txt | 69 +++ .../memory_to_memory/armgcc/CMakeLists.txt | 112 +++++ .../armgcc/MIMX9352_cm33_ram.ld | 246 +++++++++++ .../memory_to_memory/armgcc/build_all.bat | 15 + .../edma/memory_to_memory/armgcc/build_all.sh | 15 + .../memory_to_memory/armgcc/build_debug.bat | 6 + .../memory_to_memory/armgcc/build_debug.sh | 7 + .../memory_to_memory/armgcc/build_release.bat | 6 + .../memory_to_memory/armgcc/build_release.sh | 7 + .../edma/memory_to_memory/armgcc/clean.bat | 3 + .../edma/memory_to_memory/armgcc/clean.sh | 3 + .../edma/memory_to_memory/armgcc/config.cmake | 2 + .../edma/memory_to_memory/armgcc/flags.cmake | 185 +++++++++ .../edma/memory_to_memory/board.c | 152 +++++++ .../edma/memory_to_memory/board.h | 89 ++++ .../edma/memory_to_memory/clock_config.c | 97 +++++ .../edma/memory_to_memory/clock_config.h | 29 ++ .../memory_to_memory/edma_memory_to_memory.c | 114 +++++ .../edma/memory_to_memory/pin_mux.c | 65 +++ .../edma/memory_to_memory/pin_mux.h | 54 +++ .../edma/memory_to_memory/readme.txt | 51 +++ .../edma/scatter_gather/armgcc/CMakeLists.txt | 112 +++++ .../armgcc/MIMX9352_cm33_ram.ld | 246 +++++++++++ .../edma/scatter_gather/armgcc/build_all.bat | 15 + .../edma/scatter_gather/armgcc/build_all.sh | 15 + .../scatter_gather/armgcc/build_debug.bat | 6 + .../edma/scatter_gather/armgcc/build_debug.sh | 7 + .../scatter_gather/armgcc/build_release.bat | 6 + .../scatter_gather/armgcc/build_release.sh | 7 + .../edma/scatter_gather/armgcc/clean.bat | 3 + .../edma/scatter_gather/armgcc/clean.sh | 3 + .../edma/scatter_gather/armgcc/config.cmake | 2 + .../edma/scatter_gather/armgcc/flags.cmake | 185 +++++++++ .../edma/scatter_gather/board.c | 152 +++++++ .../edma/scatter_gather/board.h | 89 ++++ .../edma/scatter_gather/clock_config.c | 97 +++++ .../edma/scatter_gather/clock_config.h | 29 ++ .../edma/scatter_gather/edma_scatter_gather.c | 139 +++++++ .../edma/scatter_gather/pin_mux.c | 65 +++ .../edma/scatter_gather/pin_mux.h | 54 +++ .../edma/scatter_gather/readme.txt | 52 +++ .../edma4/channel_link/armgcc/CMakeLists.txt | 114 +++++ .../channel_link/armgcc/MIMX9352_cm33_ram.ld | 246 +++++++++++ .../edma4/channel_link/armgcc/build_all.bat | 15 + .../edma4/channel_link/armgcc/build_all.sh | 15 + .../edma4/channel_link/armgcc/build_debug.bat | 6 + .../edma4/channel_link/armgcc/build_debug.sh | 7 + .../channel_link/armgcc/build_release.bat | 6 + .../channel_link/armgcc/build_release.sh | 7 + .../edma4/channel_link/armgcc/clean.bat | 3 + .../edma4/channel_link/armgcc/clean.sh | 3 + .../edma4/channel_link/armgcc/config.cmake | 2 + .../edma4/channel_link/armgcc/flags.cmake | 185 +++++++++ .../edma4/channel_link/board.c | 152 +++++++ .../edma4/channel_link/board.h | 89 ++++ .../edma4/channel_link/clock_config.c | 97 +++++ .../edma4/channel_link/clock_config.h | 29 ++ .../edma4/channel_link/edma_channel_link.c | 152 +++++++ .../edma4/channel_link/pin_mux.c | 65 +++ .../edma4/channel_link/pin_mux.h | 54 +++ .../edma4/channel_link/readme.txt | 74 ++++ .../interleave_transfer/armgcc/CMakeLists.txt | 114 +++++ .../armgcc/MIMX9352_cm33_ram.ld | 246 +++++++++++ .../interleave_transfer/armgcc/build_all.bat | 15 + .../interleave_transfer/armgcc/build_all.sh | 15 + .../armgcc/build_debug.bat | 6 + .../interleave_transfer/armgcc/build_debug.sh | 7 + .../armgcc/build_release.bat | 6 + .../armgcc/build_release.sh | 7 + .../interleave_transfer/armgcc/clean.bat | 3 + .../edma4/interleave_transfer/armgcc/clean.sh | 3 + .../interleave_transfer/armgcc/config.cmake | 2 + .../interleave_transfer/armgcc/flags.cmake | 185 +++++++++ .../edma4/interleave_transfer/board.c | 152 +++++++ .../edma4/interleave_transfer/board.h | 89 ++++ .../edma4/interleave_transfer/clock_config.c | 97 +++++ .../edma4/interleave_transfer/clock_config.h | 29 ++ .../edma_interleave_transfer.c | 109 +++++ .../edma4/interleave_transfer/pin_mux.c | 65 +++ .../edma4/interleave_transfer/pin_mux.h | 54 +++ .../edma4/interleave_transfer/readme.txt | 52 +++ .../memory_to_memory/armgcc/CMakeLists.txt | 114 +++++ .../armgcc/MIMX9352_cm33_ram.ld | 246 +++++++++++ .../memory_to_memory/armgcc/build_all.bat | 15 + .../memory_to_memory/armgcc/build_all.sh | 15 + .../memory_to_memory/armgcc/build_debug.bat | 6 + .../memory_to_memory/armgcc/build_debug.sh | 7 + .../memory_to_memory/armgcc/build_release.bat | 6 + .../memory_to_memory/armgcc/build_release.sh | 7 + .../edma4/memory_to_memory/armgcc/clean.bat | 3 + .../edma4/memory_to_memory/armgcc/clean.sh | 3 + .../memory_to_memory/armgcc/config.cmake | 2 + .../edma4/memory_to_memory/armgcc/flags.cmake | 185 +++++++++ .../edma4/memory_to_memory/board.c | 152 +++++++ .../edma4/memory_to_memory/board.h | 89 ++++ .../edma4/memory_to_memory/clock_config.c | 97 +++++ .../edma4/memory_to_memory/clock_config.h | 29 ++ .../memory_to_memory/edma_memory_to_memory.c | 104 +++++ .../edma4/memory_to_memory/pin_mux.c | 65 +++ .../edma4/memory_to_memory/pin_mux.h | 54 +++ .../edma4/memory_to_memory/readme.txt | 48 +++ .../armgcc/CMakeLists.txt | 114 +++++ .../armgcc/MIMX9352_cm33_ram.ld | 246 +++++++++++ .../armgcc/build_all.bat | 15 + .../armgcc/build_all.sh | 15 + .../armgcc/build_debug.bat | 6 + .../armgcc/build_debug.sh | 7 + .../armgcc/build_release.bat | 6 + .../armgcc/build_release.sh | 7 + .../armgcc/clean.bat | 3 + .../memory_to_memory_transfer/armgcc/clean.sh | 3 + .../armgcc/config.cmake | 2 + .../armgcc/flags.cmake | 185 +++++++++ .../edma4/memory_to_memory_transfer/board.c | 152 +++++++ .../edma4/memory_to_memory_transfer/board.h | 89 ++++ .../memory_to_memory_transfer/clock_config.c | 97 +++++ .../memory_to_memory_transfer/clock_config.h | 29 ++ .../edma_memory_to_memory_transfer.c | 104 +++++ .../edma4/memory_to_memory_transfer/pin_mux.c | 65 +++ .../edma4/memory_to_memory_transfer/pin_mux.h | 54 +++ .../memory_to_memory_transfer/readme.txt | 48 +++ .../edma4/memset/armgcc/CMakeLists.txt | 114 +++++ .../edma4/memset/armgcc/MIMX9352_cm33_ram.ld | 246 +++++++++++ .../edma4/memset/armgcc/build_all.bat | 15 + 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| 7 + .../single_channel/armgcc/build_release.bat | 6 + .../single_channel/armgcc/build_release.sh | 7 + .../lpit/single_channel/armgcc/clean.bat | 3 + .../lpit/single_channel/armgcc/clean.sh | 3 + .../lpit/single_channel/armgcc/config.cmake | 2 + .../lpit/single_channel/armgcc/flags.cmake | 185 +++++++++ .../lpit/single_channel/board.c | 152 +++++++ .../lpit/single_channel/board.h | 89 ++++ .../lpit/single_channel/clock_config.c | 97 +++++ .../lpit/single_channel/clock_config.h | 29 ++ .../lpit/single_channel/lpit_single_channel.c | 121 ++++++ .../lpit/single_channel/pin_mux.c | 65 +++ .../lpit/single_channel/pin_mux.h | 54 +++ .../lpit/single_channel/readme.txt | 50 +++ .../lptmr/armgcc/CMakeLists.txt | 109 +++++ .../lptmr/armgcc/MIMX9352_cm33_ram.ld | 246 +++++++++++ .../lptmr/armgcc/build_all.bat | 15 + .../driver_examples/lptmr/armgcc/build_all.sh | 15 + .../lptmr/armgcc/build_debug.bat | 6 + .../lptmr/armgcc/build_debug.sh | 7 + .../lptmr/armgcc/build_release.bat | 6 + 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+ .../interrupt_transfer/armgcc/clean.bat | 3 + .../lpuart/interrupt_transfer/armgcc/clean.sh | 3 + .../interrupt_transfer/armgcc/config.cmake | 2 + .../interrupt_transfer/armgcc/flags.cmake | 185 +++++++++ .../lpuart/interrupt_transfer/board.c | 152 +++++++ .../lpuart/interrupt_transfer/board.h | 89 ++++ .../lpuart/interrupt_transfer/clock_config.c | 97 +++++ .../lpuart/interrupt_transfer/clock_config.h | 29 ++ .../lpuart_interrupt_transfer.c | 148 +++++++ .../lpuart/interrupt_transfer/pin_mux.c | 65 +++ .../lpuart/interrupt_transfer/pin_mux.h | 54 +++ .../lpuart/interrupt_transfer/readme.txt | 45 ++ .../lpuart/polling/armgcc/CMakeLists.txt | 107 +++++ .../polling/armgcc/MIMX9352_cm33_ram.ld | 246 +++++++++++ .../lpuart/polling/armgcc/build_all.bat | 15 + .../lpuart/polling/armgcc/build_all.sh | 15 + .../lpuart/polling/armgcc/build_debug.bat | 6 + .../lpuart/polling/armgcc/build_debug.sh | 7 + .../lpuart/polling/armgcc/build_release.bat | 6 + .../lpuart/polling/armgcc/build_release.sh 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6 + .../freertos_swtimer/armgcc/build_release.sh | 7 + .../freertos_swtimer/armgcc/clean.bat | 3 + .../freertos_swtimer/armgcc/clean.sh | 3 + .../freertos_swtimer/armgcc/config.cmake | 3 + .../freertos_swtimer/armgcc/flags.cmake | 191 +++++++++ .../rtos_examples/freertos_swtimer/board.c | 152 +++++++ .../rtos_examples/freertos_swtimer/board.h | 89 ++++ .../freertos_swtimer/clock_config.c | 97 +++++ .../freertos_swtimer/clock_config.h | 29 ++ .../freertos_swtimer/freertos_swtimer.c | 72 ++++ .../rtos_examples/freertos_swtimer/pin_mux.c | 65 +++ .../rtos_examples/freertos_swtimer/pin_mux.h | 54 +++ .../rtos_examples/freertos_swtimer/readme.txt | 49 +++ 752 files changed, 50429 insertions(+), 430 deletions(-) create mode 100644 boards/som_mx93/driver_examples/canfd/loopback/armgcc/CMakeLists.txt create mode 100644 boards/som_mx93/driver_examples/canfd/loopback/armgcc/MIMX9352_cm33_ram.ld create mode 100644 boards/som_mx93/driver_examples/canfd/loopback/armgcc/build_all.bat create mode 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boards/som_mx93/rtos_examples/freertos_swtimer/readme.txt diff --git a/boards/som_mx93/demo_apps/ethosu_apps_rpmsg/board.c b/boards/som_mx93/demo_apps/ethosu_apps_rpmsg/board.c index 37894a62e..2a3b145e0 100644 --- a/boards/som_mx93/demo_apps/ethosu_apps_rpmsg/board.c +++ b/boards/som_mx93/demo_apps/ethosu_apps_rpmsg/board.c @@ -7,9 +7,6 @@ #include "board.h" #include "fsl_cache.h" -#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED -#include "fsl_lpi2c.h" -#endif /******************************************************************************* * Definitions @@ -39,153 +36,6 @@ void BOARD_InitDebugConsole(void) BOARD_DEBUG_UART_CLK_FREQ); } -#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED -void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz) -{ - lpi2c_master_config_t lpi2cConfig = {0}; - - /* - * lpi2cConfig.debugEnable = false; - * lpi2cConfig.ignoreAck = false; - * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain; - * lpi2cConfig.baudRate_Hz = 100000U; - * lpi2cConfig.busIdleTimeout_ns = 0; - * lpi2cConfig.pinLowTimeout_ns = 0; - * lpi2cConfig.sdaGlitchFilterWidth_ns = 0; - * lpi2cConfig.sclGlitchFilterWidth_ns = 0; - */ - LPI2C_MasterGetDefaultConfig(&lpi2cConfig); - LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz); -} - -status_t BOARD_LPI2C_Send(LPI2C_Type *base, - uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subAddressSize, - uint8_t *txBuff, - uint8_t txBuffSize, - uint32_t flags) -{ - lpi2c_master_transfer_t xfer; - - xfer.flags = flags; - xfer.slaveAddress = deviceAddress; - xfer.direction = kLPI2C_Write; - xfer.subaddress = subAddress; - xfer.subaddressSize = subAddressSize; - xfer.data = txBuff; - xfer.dataSize = txBuffSize; - - return LPI2C_MasterTransferBlocking(base, &xfer); -} - -status_t BOARD_LPI2C_Receive(LPI2C_Type *base, - uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subAddressSize, - uint8_t *rxBuff, - uint8_t rxBuffSize, - uint32_t flags) -{ - lpi2c_master_transfer_t xfer; - - xfer.flags = flags; - xfer.slaveAddress = deviceAddress; - xfer.direction = kLPI2C_Read; - xfer.subaddress = subAddress; - xfer.subaddressSize = subAddressSize; - xfer.data = rxBuff; - xfer.dataSize = rxBuffSize; - - return LPI2C_MasterTransferBlocking(base, &xfer); -} - -#if defined(BOARD_USE_ADP5585) && BOARD_USE_ADP5585 -void BOARD_ADP5585_I2C_Init(void) -{ - BOARD_LPI2C_Init(BOARD_ADP5585_I2C, BOARD_ADP5585_I2C_CLOCK_FREQ); -} - -status_t BOARD_ADP5585_I2C_Send(uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subAddressSize, - const uint8_t *txBuff, - uint8_t txBuffSize, - uint32_t flags) -{ - return BOARD_LPI2C_Send(BOARD_ADP5585_I2C, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff, txBuffSize, - flags); -} - -status_t BOARD_ADP5585_I2C_Receive(uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subAddressSize, - uint8_t *rxBuff, - uint8_t rxBuffSize, - uint32_t flags) -{ - return BOARD_LPI2C_Receive(BOARD_ADP5585_I2C, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize, flags); -} - -void BOARD_InitADP5585(adp5585_handle_t *handle) -{ - BOARD_ADP5585_I2C_Init(); - - static const adp5585_config_t config = { - .i2cAddr = BOARD_ADP5585_I2C_ADDR, - .I2C_SendFunc = BOARD_ADP5585_I2C_Send, - .I2C_ReceiveFunc = BOARD_ADP5585_I2C_Receive, - }; - - ADP5585_Init(handle, &config); -} - -#endif /* BOARD_USE_ADP5585. */ - -#if defined(BOARD_USE_PCAL6524) && BOARD_USE_PCAL6524 -void BOARD_PCAL6524_I2C_Init(void) -{ - BOARD_LPI2C_Init(BOARD_PCAL6524_I2C, BOARD_PCAL6524_I2C_CLOCK_FREQ); -} - -status_t BOARD_PCAL6524_I2C_Send(uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subAddressSize, - const uint8_t *txBuff, - uint8_t txBuffSize, - uint32_t flags) -{ - return BOARD_LPI2C_Send(BOARD_PCAL6524_I2C, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff, - txBuffSize, flags); -} - -status_t BOARD_PCAL6524_I2C_Receive(uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subAddressSize, - uint8_t *rxBuff, - uint8_t rxBuffSize, - uint32_t flags) -{ - return BOARD_LPI2C_Receive(BOARD_PCAL6524_I2C, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize, - flags); -} - -void BOARD_InitPCAL6524(pcal6524_handle_t *handle) -{ - BOARD_PCAL6524_I2C_Init(); - - static const pcal6524_config_t config = { - .i2cAddr = BOARD_PCAL6524_I2C_ADDR, - .I2C_SendFunc = BOARD_PCAL6524_I2C_Send, - .I2C_ReceiveFunc = BOARD_PCAL6524_I2C_Receive, - }; - - PCAL6524_Init(handle, &config); -} - -#endif /* BOARD_USE_PCAL6524. */ - -#endif void BOARD_McoreSUSPEND(void) { diff --git a/boards/som_mx93/demo_apps/ethosu_apps_rpmsg/board.h b/boards/som_mx93/demo_apps/ethosu_apps_rpmsg/board.h index 131afc6c5..5108807ef 100644 --- a/boards/som_mx93/demo_apps/ethosu_apps_rpmsg/board.h +++ b/boards/som_mx93/demo_apps/ethosu_apps_rpmsg/board.h @@ -11,12 +11,6 @@ #include "fsl_common.h" #include "fsl_debug_console.h" #include "clock_config.h" -#if defined(BOARD_USE_ADP5585) && BOARD_USE_ADP5585 -#include "fsl_adp5585.h" -#endif -#if defined(BOARD_USE_PCAL6524) && BOARD_USE_PCAL6524 -#include "fsl_pcal6524.h" -#endif /******************************************************************************* * Definitions @@ -69,58 +63,6 @@ extern "C" { ******************************************************************************/ void BOARD_InitDebugConsole(void); -#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED -status_t BOARD_LPI2C_Send(LPI2C_Type *base, - uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subaddressSize, - uint8_t *txBuff, - uint8_t txBuffSize, - uint32_t flags); -status_t BOARD_LPI2C_Receive(LPI2C_Type *base, - uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subaddressSize, - uint8_t *rxBuff, - uint8_t rxBuffSize, - uint32_t flags); -#if defined(BOARD_USE_ADP5585) && BOARD_USE_ADP5585 -void BOARD_ADP5585_I2C_Init(void); -status_t BOARD_ADP5585_I2C_Send(uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subAddressSize, - const uint8_t *txBuff, - uint8_t txBuffSize, - uint32_t flags); -status_t BOARD_ADP5585_I2C_Receive(uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subAddressSize, - uint8_t *rxBuff, - uint8_t rxBuffSize, - uint32_t flags); - -void BOARD_InitADP5585(adp5585_handle_t *handle); -#endif /* BOARD_USE_ADP5585 */ - -#if defined(BOARD_USE_PCAL6524) && BOARD_USE_PCAL6524 -void BOARD_PCAL6524_I2C_Init(void); -status_t BOARD_PCAL6524_I2C_Send(uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subAddressSize, - const uint8_t *txBuff, - uint8_t txBuffSize, - uint32_t flags); -status_t BOARD_PCAL6524_I2C_Receive(uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subAddressSize, - uint8_t *rxBuff, - uint8_t rxBuffSize, - uint32_t flags); - -void BOARD_InitPCAL6524(pcal6524_handle_t *handle); -#endif /* BOARD_USE_PCAL6524 */ - -#endif /* Mcore suspend setting */ #define OSCPLL_LPM_START 3U diff --git a/boards/som_mx93/demo_apps/ethosu_apps_rpmsg/pin_mux.c b/boards/som_mx93/demo_apps/ethosu_apps_rpmsg/pin_mux.c index ffcef4c9f..4c8d6a119 100644 --- a/boards/som_mx93/demo_apps/ethosu_apps_rpmsg/pin_mux.c +++ b/boards/som_mx93/demo_apps/ethosu_apps_rpmsg/pin_mux.c @@ -39,8 +39,8 @@ void BOARD_InitBootPins(void) BOARD_InitPins: - options: {callFromInitBoot: 'true', coreID: cm33} - pin_list: - - {pin_num: F20, peripheral: LPUART2, signal: lpuart_rx, pin_signal: UART2_RXD, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} - - {pin_num: F21, peripheral: LPUART2, signal: lpuart_tx, pin_signal: UART2_TXD, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ @@ -54,9 +54,9 @@ void BOARD_InitPins(void) { /*!< Function assigne IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); - IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, IOMUXC_PAD_PD_MASK); - IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, IOMUXC_PAD_DSE(15U)); } diff --git a/boards/som_mx93/demo_apps/hello_world/board.c b/boards/som_mx93/demo_apps/hello_world/board.c index 37894a62e..2a3b145e0 100644 --- a/boards/som_mx93/demo_apps/hello_world/board.c +++ b/boards/som_mx93/demo_apps/hello_world/board.c @@ -7,9 +7,6 @@ #include "board.h" #include "fsl_cache.h" -#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED -#include "fsl_lpi2c.h" -#endif /******************************************************************************* * Definitions @@ -39,153 +36,6 @@ void BOARD_InitDebugConsole(void) BOARD_DEBUG_UART_CLK_FREQ); } -#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED -void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz) -{ - lpi2c_master_config_t lpi2cConfig = {0}; - - /* - * lpi2cConfig.debugEnable = false; - * lpi2cConfig.ignoreAck = false; - * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain; - * lpi2cConfig.baudRate_Hz = 100000U; - * lpi2cConfig.busIdleTimeout_ns = 0; - * lpi2cConfig.pinLowTimeout_ns = 0; - * lpi2cConfig.sdaGlitchFilterWidth_ns = 0; - * lpi2cConfig.sclGlitchFilterWidth_ns = 0; - */ - LPI2C_MasterGetDefaultConfig(&lpi2cConfig); - LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz); -} - -status_t BOARD_LPI2C_Send(LPI2C_Type *base, - uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subAddressSize, - uint8_t *txBuff, - uint8_t txBuffSize, - uint32_t flags) -{ - lpi2c_master_transfer_t xfer; - - xfer.flags = flags; - xfer.slaveAddress = deviceAddress; - xfer.direction = kLPI2C_Write; - xfer.subaddress = subAddress; - xfer.subaddressSize = subAddressSize; - xfer.data = txBuff; - xfer.dataSize = txBuffSize; - - return LPI2C_MasterTransferBlocking(base, &xfer); -} - -status_t BOARD_LPI2C_Receive(LPI2C_Type *base, - uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subAddressSize, - uint8_t *rxBuff, - uint8_t rxBuffSize, - uint32_t flags) -{ - lpi2c_master_transfer_t xfer; - - xfer.flags = flags; - xfer.slaveAddress = deviceAddress; - xfer.direction = kLPI2C_Read; - xfer.subaddress = subAddress; - xfer.subaddressSize = subAddressSize; - xfer.data = rxBuff; - xfer.dataSize = rxBuffSize; - - return LPI2C_MasterTransferBlocking(base, &xfer); -} - -#if defined(BOARD_USE_ADP5585) && BOARD_USE_ADP5585 -void BOARD_ADP5585_I2C_Init(void) -{ - BOARD_LPI2C_Init(BOARD_ADP5585_I2C, BOARD_ADP5585_I2C_CLOCK_FREQ); -} - -status_t BOARD_ADP5585_I2C_Send(uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subAddressSize, - const uint8_t *txBuff, - uint8_t txBuffSize, - uint32_t flags) -{ - return BOARD_LPI2C_Send(BOARD_ADP5585_I2C, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff, txBuffSize, - flags); -} - -status_t BOARD_ADP5585_I2C_Receive(uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subAddressSize, - uint8_t *rxBuff, - uint8_t rxBuffSize, - uint32_t flags) -{ - return BOARD_LPI2C_Receive(BOARD_ADP5585_I2C, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize, flags); -} - -void BOARD_InitADP5585(adp5585_handle_t *handle) -{ - BOARD_ADP5585_I2C_Init(); - - static const adp5585_config_t config = { - .i2cAddr = BOARD_ADP5585_I2C_ADDR, - .I2C_SendFunc = BOARD_ADP5585_I2C_Send, - .I2C_ReceiveFunc = BOARD_ADP5585_I2C_Receive, - }; - - ADP5585_Init(handle, &config); -} - -#endif /* BOARD_USE_ADP5585. */ - -#if defined(BOARD_USE_PCAL6524) && BOARD_USE_PCAL6524 -void BOARD_PCAL6524_I2C_Init(void) -{ - BOARD_LPI2C_Init(BOARD_PCAL6524_I2C, BOARD_PCAL6524_I2C_CLOCK_FREQ); -} - -status_t BOARD_PCAL6524_I2C_Send(uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subAddressSize, - const uint8_t *txBuff, - uint8_t txBuffSize, - uint32_t flags) -{ - return BOARD_LPI2C_Send(BOARD_PCAL6524_I2C, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff, - txBuffSize, flags); -} - -status_t BOARD_PCAL6524_I2C_Receive(uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subAddressSize, - uint8_t *rxBuff, - uint8_t rxBuffSize, - uint32_t flags) -{ - return BOARD_LPI2C_Receive(BOARD_PCAL6524_I2C, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize, - flags); -} - -void BOARD_InitPCAL6524(pcal6524_handle_t *handle) -{ - BOARD_PCAL6524_I2C_Init(); - - static const pcal6524_config_t config = { - .i2cAddr = BOARD_PCAL6524_I2C_ADDR, - .I2C_SendFunc = BOARD_PCAL6524_I2C_Send, - .I2C_ReceiveFunc = BOARD_PCAL6524_I2C_Receive, - }; - - PCAL6524_Init(handle, &config); -} - -#endif /* BOARD_USE_PCAL6524. */ - -#endif void BOARD_McoreSUSPEND(void) { diff --git a/boards/som_mx93/demo_apps/hello_world/board.h b/boards/som_mx93/demo_apps/hello_world/board.h index 131afc6c5..5108807ef 100644 --- a/boards/som_mx93/demo_apps/hello_world/board.h +++ b/boards/som_mx93/demo_apps/hello_world/board.h @@ -11,12 +11,6 @@ #include "fsl_common.h" #include "fsl_debug_console.h" #include "clock_config.h" -#if defined(BOARD_USE_ADP5585) && BOARD_USE_ADP5585 -#include "fsl_adp5585.h" -#endif -#if defined(BOARD_USE_PCAL6524) && BOARD_USE_PCAL6524 -#include "fsl_pcal6524.h" -#endif /******************************************************************************* * Definitions @@ -69,58 +63,6 @@ extern "C" { ******************************************************************************/ void BOARD_InitDebugConsole(void); -#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED -status_t BOARD_LPI2C_Send(LPI2C_Type *base, - uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subaddressSize, - uint8_t *txBuff, - uint8_t txBuffSize, - uint32_t flags); -status_t BOARD_LPI2C_Receive(LPI2C_Type *base, - uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subaddressSize, - uint8_t *rxBuff, - uint8_t rxBuffSize, - uint32_t flags); -#if defined(BOARD_USE_ADP5585) && BOARD_USE_ADP5585 -void BOARD_ADP5585_I2C_Init(void); -status_t BOARD_ADP5585_I2C_Send(uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subAddressSize, - const uint8_t *txBuff, - uint8_t txBuffSize, - uint32_t flags); -status_t BOARD_ADP5585_I2C_Receive(uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subAddressSize, - uint8_t *rxBuff, - uint8_t rxBuffSize, - uint32_t flags); - -void BOARD_InitADP5585(adp5585_handle_t *handle); -#endif /* BOARD_USE_ADP5585 */ - -#if defined(BOARD_USE_PCAL6524) && BOARD_USE_PCAL6524 -void BOARD_PCAL6524_I2C_Init(void); -status_t BOARD_PCAL6524_I2C_Send(uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subAddressSize, - const uint8_t *txBuff, - uint8_t txBuffSize, - uint32_t flags); -status_t BOARD_PCAL6524_I2C_Receive(uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subAddressSize, - uint8_t *rxBuff, - uint8_t rxBuffSize, - uint32_t flags); - -void BOARD_InitPCAL6524(pcal6524_handle_t *handle); -#endif /* BOARD_USE_PCAL6524 */ - -#endif /* Mcore suspend setting */ #define OSCPLL_LPM_START 3U diff --git a/boards/som_mx93/demo_apps/hello_world/pin_mux.c b/boards/som_mx93/demo_apps/hello_world/pin_mux.c index 0e3f3ec04..4c8d6a119 100644 --- a/boards/som_mx93/demo_apps/hello_world/pin_mux.c +++ b/boards/som_mx93/demo_apps/hello_world/pin_mux.c @@ -39,8 +39,8 @@ void BOARD_InitBootPins(void) BOARD_InitPins: - options: {callFromInitBoot: 'true', coreID: cm33} - pin_list: - - {pin_num: F20, peripheral: LPUART2, signal: lpuart_rx, pin_signal: UART2_RXD, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} - - {pin_num: F21, peripheral: LPUART2, signal: lpuart_tx, pin_signal: UART2_TXD, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ diff --git a/boards/som_mx93/demo_apps/hello_world/readme.txt b/boards/som_mx93/demo_apps/hello_world/readme.txt index cc903df5a..d1fe9ca21 100644 --- a/boards/som_mx93/demo_apps/hello_world/readme.txt +++ b/boards/som_mx93/demo_apps/hello_world/readme.txt @@ -15,9 +15,9 @@ Toolchain supported Hardware requirements ===================== - Micro USB cable -- MCIMX93-EVK board -- J-Link Debug Probe -- 12V~20V power supply +- USB to UART Adapter +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Proper power supply - Personal Computer Board settings @@ -26,16 +26,15 @@ No special settings are required. Prepare the Demo ================ -1. Connect 12V~20V power supply and J-Link Debug Probe to the board, switch SW301 to power on the board. -2. Connect a micro USB cable between the host PC and the J1401 USB port on the target board. -3. Open a serial terminal with the following settings: +1. Connect the power supply to the board and switch on the board. +2. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +3. Open a serial terminal on the Cortex-M33 serial port with the following settings: - 115200 baud rate - 8 data bits - No parity - One stop bit - No flow control -4. Download the program to the target board. -5. Either re-power up your board or launch the debugger in your IDE to begin running the example. +4. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. Running the demo ================ diff --git a/boards/som_mx93/driver_examples/canfd/loopback/armgcc/CMakeLists.txt b/boards/som_mx93/driver_examples/canfd/loopback/armgcc/CMakeLists.txt new file mode 100644 index 000000000..52e9bfd5e --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback/armgcc/CMakeLists.txt @@ -0,0 +1,111 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(canfd_loopback) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME canfd_loopback.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../flexcan_loopback.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/devices/MIMX9352/utilities/debug_console_lite + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(utility_debug_console_lite_MIMX9352) + +include(utility_assert_lite_MIMX9352) + +include(driver_lpi2c_MIMX9352) + +include(driver_flexcan_MIMX9352) + +include(driver_clock_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_lists_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/driver_examples/canfd/loopback/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/driver_examples/canfd/loopback/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/driver_examples/canfd/loopback/armgcc/build_all.bat b/boards/som_mx93/driver_examples/canfd/loopback/armgcc/build_all.bat new file mode 100644 index 000000000..1205ab083 --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback/armgcc/build_all.bat @@ -0,0 +1,15 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/som_mx93/driver_examples/canfd/loopback/armgcc/build_all.sh b/boards/som_mx93/driver_examples/canfd/loopback/armgcc/build_all.sh new file mode 100755 index 000000000..8cc56b74f --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/driver_examples/canfd/loopback/armgcc/build_debug.bat b/boards/som_mx93/driver_examples/canfd/loopback/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/canfd/loopback/armgcc/build_debug.sh b/boards/som_mx93/driver_examples/canfd/loopback/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/canfd/loopback/armgcc/build_release.bat b/boards/som_mx93/driver_examples/canfd/loopback/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/canfd/loopback/armgcc/build_release.sh b/boards/som_mx93/driver_examples/canfd/loopback/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/canfd/loopback/armgcc/clean.bat b/boards/som_mx93/driver_examples/canfd/loopback/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/driver_examples/canfd/loopback/armgcc/clean.sh b/boards/som_mx93/driver_examples/canfd/loopback/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/driver_examples/canfd/loopback/armgcc/config.cmake b/boards/som_mx93/driver_examples/canfd/loopback/armgcc/config.cmake new file mode 100755 index 000000000..920520e3d --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/driver_examples/canfd/loopback/armgcc/flags.cmake b/boards/som_mx93/driver_examples/canfd/loopback/armgcc/flags.cmake new file mode 100755 index 000000000..b44a34afe --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback/armgcc/flags.cmake @@ -0,0 +1,187 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DFLEXCAN_WAIT_TIMEOUT=1000 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DFLEXCAN_WAIT_TIMEOUT=1000 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/driver_examples/canfd/loopback/board.c b/boards/som_mx93/driver_examples/canfd/loopback/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/driver_examples/canfd/loopback/board.h b/boards/som_mx93/driver_examples/canfd/loopback/board.h new file mode 100644 index 000000000..e20723f41 --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback/board.h @@ -0,0 +1,71 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + + + + + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/driver_examples/canfd/loopback/clock_config.c b/boards/som_mx93/driver_examples/canfd/loopback/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/driver_examples/canfd/loopback/clock_config.h b/boards/som_mx93/driver_examples/canfd/loopback/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/driver_examples/canfd/loopback/flexcan_loopback.c b/boards/som_mx93/driver_examples/canfd/loopback/flexcan_loopback.c new file mode 100644 index 000000000..650b0ace3 --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback/flexcan_loopback.c @@ -0,0 +1,298 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_debug_console.h" +#include "fsl_flexcan.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" + +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define EXAMPLE_CAN CAN1 +#define EXAMPLE_FLEXCAN_IRQn CAN1_IRQn +#define EXAMPLE_FLEXCAN_IRQHandler CAN1_IRQHandler +#define RX_MESSAGE_BUFFER_NUM (1) +#define TX_MESSAGE_BUFFER_NUM (0) +#define USE_CANFD (1) + +#define FLEXCAN_CLOCK_ROOT kCLOCK_Root_Can1 +#define EXAMPLE_CAN_CLK_FREQ (CLOCK_GetIpFreq(FLEXCAN_CLOCK_ROOT)) +/* Set USE_IMPROVED_TIMING_CONFIG macro to use api to calculates the improved CAN / CAN FD timing values. */ +#define USE_IMPROVED_TIMING_CONFIG (1U) +/* Fix MISRA_C-2012 Rule 17.7. */ +#define LOG_INFO (void)PRINTF + +#if (defined(USE_CANFD) && USE_CANFD) +/* + * DWORD_IN_MB DLC BYTES_IN_MB Maximum MBs + * 2 8 kFLEXCAN_8BperMB 64 + * 4 10 kFLEXCAN_16BperMB 42 + * 8 13 kFLEXCAN_32BperMB 25 + * 16 15 kFLEXCAN_64BperMB 14 + * + * Dword in each message buffer, Length of data in bytes, Payload size must align, + * and the Message Buffers are limited corresponding to each payload configuration: + */ +#define DWORD_IN_MB (16) +#define DLC (15) +#define BYTES_IN_MB kFLEXCAN_64BperMB +#else +#define DLC (8) +#endif +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +volatile bool rxComplete = false; +#if (defined(USE_CANFD) && USE_CANFD) +flexcan_fd_frame_t txFrame, rxFrame; +#else +flexcan_frame_t txFrame, rxFrame; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +void EXAMPLE_FLEXCAN_IRQHandler(void) +{ + /* If new data arrived. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) +#if (RX_MESSAGE_BUFFER_NUM >= 64U) + if (0U != FLEXCAN_GetHigh64MbStatusFlags(EXAMPLE_CAN, (uint64_t)1U << (RX_MESSAGE_BUFFER_NUM - 64U))) + { + FLEXCAN_ClearHigh64MbStatusFlags(EXAMPLE_CAN, (uint64_t)1U << (RX_MESSAGE_BUFFER_NUM - 64U)); + rxComplete = true; + } +#else + if (0U != FLEXCAN_GetMbStatusFlags(EXAMPLE_CAN, (uint64_t)1U << RX_MESSAGE_BUFFER_NUM)) + { + FLEXCAN_ClearMbStatusFlags(EXAMPLE_CAN, (uint64_t)1U << RX_MESSAGE_BUFFER_NUM); + rxComplete = true; + } +#endif +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) && FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) + if (0U != FLEXCAN_GetMbStatusFlags(EXAMPLE_CAN, (uint64_t)1U << RX_MESSAGE_BUFFER_NUM)) + { + FLEXCAN_ClearMbStatusFlags(EXAMPLE_CAN, (uint64_t)1U << RX_MESSAGE_BUFFER_NUM); + rxComplete = true; + } +#else + if (0U != FLEXCAN_GetMbStatusFlags(EXAMPLE_CAN, (uint32_t)1U << RX_MESSAGE_BUFFER_NUM)) + { + FLEXCAN_ClearMbStatusFlags(EXAMPLE_CAN, (uint32_t)1U << RX_MESSAGE_BUFFER_NUM); + rxComplete = true; + } +#endif + + if (rxComplete) + { +#if (defined(USE_CANFD) && USE_CANFD) + (void)FLEXCAN_ReadFDRxMb(EXAMPLE_CAN, RX_MESSAGE_BUFFER_NUM, &rxFrame); +#else + (void)FLEXCAN_ReadRxMb(EXAMPLE_CAN, RX_MESSAGE_BUFFER_NUM, &rxFrame); +#endif + } + SDK_ISR_EXIT_BARRIER; +} + +/*! + * @brief Main function + */ +int main(void) +{ + flexcan_config_t flexcanConfig; + flexcan_rx_mb_config_t mbConfig; + + /* Initialize board hardware. */ + /* clang-format off */ + + const clock_root_config_t flexcanClkCfg = { + .clockOff = false, + .mux = 0, + .div = 1 + }; + /* clang-format on */ + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + + CLOCK_SetRootClock(FLEXCAN_CLOCK_ROOT, &flexcanClkCfg); + + LOG_INFO("\r\n==FlexCAN loopback functional example -- Start.==\r\n\r\n"); + + /* Init FlexCAN module. */ + /* + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrc0; + * flexcanConfig.bitRate = 1000000U; + * flexcanConfig.bitRateFD = 2000000U; + * flexcanConfig.maxMbNum = 16; + * flexcanConfig.enableLoopBack = false; + * flexcanConfig.enableSelfWakeup = false; + * flexcanConfig.enableIndividMask = false; + * flexcanConfig.disableSelfReception = false; + * flexcanConfig.enableListenOnlyMode = false; + * flexcanConfig.enableDoze = false; + */ + FLEXCAN_GetDefaultConfig(&flexcanConfig); + +#if defined(EXAMPLE_CAN_CLK_SOURCE) + flexcanConfig.clkSrc = EXAMPLE_CAN_CLK_SOURCE; +#endif + + flexcanConfig.enableLoopBack = true; + +#if (defined(USE_IMPROVED_TIMING_CONFIG) && USE_IMPROVED_TIMING_CONFIG) + flexcan_timing_config_t timing_config; + memset(&timing_config, 0, sizeof(flexcan_timing_config_t)); +#if (defined(USE_CANFD) && USE_CANFD) + if (FLEXCAN_FDCalculateImprovedTimingValues(EXAMPLE_CAN, flexcanConfig.bitRate, flexcanConfig.bitRateFD, + EXAMPLE_CAN_CLK_FREQ, &timing_config)) + { + /* Update the improved timing configuration*/ + memcpy(&(flexcanConfig.timingConfig), &timing_config, sizeof(flexcan_timing_config_t)); + } + else + { + LOG_INFO("No found Improved Timing Configuration. Just used default configuration\r\n\r\n"); + } +#else + if (FLEXCAN_CalculateImprovedTimingValues(EXAMPLE_CAN, flexcanConfig.bitRate, EXAMPLE_CAN_CLK_FREQ, &timing_config)) + { + /* Update the improved timing configuration*/ + memcpy(&(flexcanConfig.timingConfig), &timing_config, sizeof(flexcan_timing_config_t)); + } + else + { + LOG_INFO("No found Improved Timing Configuration. Just used default configuration\r\n\r\n"); + } +#endif +#endif + +#if (defined(USE_CANFD) && USE_CANFD) + FLEXCAN_FDInit(EXAMPLE_CAN, &flexcanConfig, EXAMPLE_CAN_CLK_FREQ, BYTES_IN_MB, true); +#else + FLEXCAN_Init(EXAMPLE_CAN, &flexcanConfig, EXAMPLE_CAN_CLK_FREQ); +#endif + + /* Setup Rx Message Buffer. */ + mbConfig.format = kFLEXCAN_FrameFormatStandard; + mbConfig.type = kFLEXCAN_FrameTypeData; + mbConfig.id = FLEXCAN_ID_STD(0x123); +#if (defined(USE_CANFD) && USE_CANFD) + FLEXCAN_SetFDRxMbConfig(EXAMPLE_CAN, RX_MESSAGE_BUFFER_NUM, &mbConfig, true); +#else + FLEXCAN_SetRxMbConfig(EXAMPLE_CAN, RX_MESSAGE_BUFFER_NUM, &mbConfig, true); +#endif + +/* Setup Tx Message Buffer. */ +#if (defined(USE_CANFD) && USE_CANFD) + FLEXCAN_SetFDTxMbConfig(EXAMPLE_CAN, TX_MESSAGE_BUFFER_NUM, true); +#else + FLEXCAN_SetTxMbConfig(EXAMPLE_CAN, TX_MESSAGE_BUFFER_NUM, true); +#endif + + /* Enable Rx Message Buffer interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) +#if (RX_MESSAGE_BUFFER_NUM >= 64U) + FLEXCAN_EnableHigh64MbInterrupts(EXAMPLE_CAN, (uint64_t)1U << (RX_MESSAGE_BUFFER_NUM - 64U)); +#else + FLEXCAN_EnableMbInterrupts(EXAMPLE_CAN, (uint64_t)1U << RX_MESSAGE_BUFFER_NUM); + +#endif +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) && FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) + FLEXCAN_EnableMbInterrupts(EXAMPLE_CAN, (uint64_t)1U << RX_MESSAGE_BUFFER_NUM); + +#else + FLEXCAN_EnableMbInterrupts(EXAMPLE_CAN, (uint32_t)1U << RX_MESSAGE_BUFFER_NUM); +#endif + (void)EnableIRQ(EXAMPLE_FLEXCAN_IRQn); + + /* Prepare Tx Frame for sending. */ + txFrame.format = (uint8_t)kFLEXCAN_FrameFormatStandard; + txFrame.type = (uint8_t)kFLEXCAN_FrameTypeData; + txFrame.id = FLEXCAN_ID_STD(0x123); + txFrame.length = (uint8_t)DLC; +#if (defined(USE_CANFD) && USE_CANFD) + txFrame.brs = 1U; + txFrame.edl = 1U; +#endif +#if (defined(USE_CANFD) && USE_CANFD) + uint8_t i = 0; + for (i = 0; i < DWORD_IN_MB; i++) + { + txFrame.dataWord[i] = i; + } +#else + txFrame.dataWord0 = CAN_WORD0_DATA_BYTE_0(0x11) | CAN_WORD0_DATA_BYTE_1(0x22) | CAN_WORD0_DATA_BYTE_2(0x33) | + CAN_WORD0_DATA_BYTE_3(0x44); + txFrame.dataWord1 = CAN_WORD1_DATA_BYTE_4(0x55) | CAN_WORD1_DATA_BYTE_5(0x66) | CAN_WORD1_DATA_BYTE_6(0x77) | + CAN_WORD1_DATA_BYTE_7(0x88); +#endif + + LOG_INFO("Send message from MB%d to MB%d\r\n", TX_MESSAGE_BUFFER_NUM, RX_MESSAGE_BUFFER_NUM); +#if (defined(USE_CANFD) && USE_CANFD) + for (i = 0; i < DWORD_IN_MB; i++) + { + LOG_INFO("tx word%d = 0x%x\r\n", i, txFrame.dataWord[i]); + } +#else + LOG_INFO("tx word0 = 0x%x\r\n", txFrame.dataWord0); + LOG_INFO("tx word1 = 0x%x\r\n", txFrame.dataWord1); +#endif + +/* Send data through Tx Message Buffer using polling function. */ +#if (defined(USE_CANFD) && USE_CANFD) + (void)FLEXCAN_TransferFDSendBlocking(EXAMPLE_CAN, TX_MESSAGE_BUFFER_NUM, &txFrame); +#else + (void)FLEXCAN_TransferSendBlocking(EXAMPLE_CAN, TX_MESSAGE_BUFFER_NUM, &txFrame); +#endif + + /* Waiting for Message receive finish. */ + while (!rxComplete) + { + } + + LOG_INFO("\r\nReceived message from MB%d\r\n", RX_MESSAGE_BUFFER_NUM); +#if (defined(USE_CANFD) && USE_CANFD) + for (i = 0; i < DWORD_IN_MB; i++) + { + LOG_INFO("rx word%d = 0x%x\r\n", i, rxFrame.dataWord[i]); + } +#else + LOG_INFO("rx word0 = 0x%x\r\n", rxFrame.dataWord0); + LOG_INFO("rx word1 = 0x%x\r\n", rxFrame.dataWord1); +#endif + + /* Stop FlexCAN Send & Receive. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) +#if (RX_MESSAGE_BUFFER_NUM >= 64U) + FLEXCAN_DisableHigh64MbInterrupts(EXAMPLE_CAN, (uint64_t)1U << (RX_MESSAGE_BUFFER_NUM - 64U)); +#else + FLEXCAN_DisableMbInterrupts(EXAMPLE_CAN, (uint64_t)1U << RX_MESSAGE_BUFFER_NUM); + +#endif +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) && FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) + FLEXCAN_DisableMbInterrupts(EXAMPLE_CAN, (uint64_t)1U << RX_MESSAGE_BUFFER_NUM); + +#else + FLEXCAN_DisableMbInterrupts(EXAMPLE_CAN, (uint32_t)1U << RX_MESSAGE_BUFFER_NUM); +#endif + + LOG_INFO("\r\n==FlexCAN loopback functional example -- Finish.==\r\n"); + + while (true) + { + } +} diff --git a/boards/som_mx93/driver_examples/canfd/loopback/pin_mux.c b/boards/som_mx93/driver_examples/canfd/loopback/pin_mux.c new file mode 100644 index 000000000..10cb5de9d --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback/pin_mux.c @@ -0,0 +1,87 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: J17, peripheral: CAN1, signal: can_rx, pin_signal: PDM_BIT_STREAM0, APC: DOMAIN0_ACCESS, HYS: DISABLED} + - {pin_num: G17, peripheral: CAN1, signal: can_tx, pin_signal: PDM_CLK, HYS: DISABLED} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, HYS: DISABLED, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, HYS: DISABLED, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_I2C1_SCL__LPI2C1_SCL, 1U); + IOMUXC_SetPinMux(IOMUXC_PAD_I2C1_SDA__LPI2C1_SDA, 1U); + IOMUXC_SetPinMux(IOMUXC_PAD_PDM_BIT_STREAM0__CAN1_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_PDM_CLK__CAN1_TX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_I2C1_SCL__LPI2C1_SCL, + IOMUXC_PAD_DSE(15U) | + IOMUXC_PAD_FSEL1(2U) | + IOMUXC_PAD_OD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_I2C1_SDA__LPI2C1_SDA, + IOMUXC_PAD_DSE(15U) | + IOMUXC_PAD_FSEL1(2U) | + IOMUXC_PAD_OD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_PDM_BIT_STREAM0__CAN1_RX, + IOMUXC_PAD_DSE(15U) | + IOMUXC_PAD_FSEL1(2U) | + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_PDM_CLK__CAN1_TX, + IOMUXC_PAD_DSE(15U) | + IOMUXC_PAD_FSEL1(2U) | + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/canfd/loopback/pin_mux.h b/boards/som_mx93/driver_examples/canfd/loopback/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/canfd/loopback/readme.txt b/boards/som_mx93/driver_examples/canfd/loopback/readme.txt new file mode 100644 index 000000000..df1f84247 --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback/readme.txt @@ -0,0 +1,69 @@ +Overview +======== +The flexcan_loopback_functional example shows how to use the loopback test mode to debug your CAN Bus design: + +To demonstrates this example, only one board is needed. The example will config one FlexCAN Message +Buffer to Rx Message Buffer and the other FlexCAN Message Buffer to Tx Message Buffer with same ID. +After that, the example will send a CAN Message from the Tx Message Buffer to the Rx Message Buffer +throuth internal loopback interconnect and print out the Message payload to terminal. + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Micro USB cable +- USB to UART Adapter +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Proper power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + +Prepare the Demo +================ +1. Connect the power supply to the board and switch on the board. +2. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +3. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +When the example runs successfully, you can see the similar information from the terminal as below. + +~~~~~~~~~~~~~~~~~~~~~ +==FlexCAN loopback functional example -- Start.== + +Send message from MB0 to MB1 +tx word0 = 0x0 +tx word1 = 0x1 +tx word2 = 0x2 +tx word3 = 0x3 +tx word4 = 0x4 +tx word5 = 0x5 +tx word6 = 0x6 +tx word7 = 0x7 + +Received message from MB1 +rx word0 = 0x0 +rx word1 = 0x1 +rx word2 = 0x2 +rx word3 = 0x3 +rx word4 = 0x4 +rx word5 = 0x5 +rx word6 = 0x6 +rx word7 = 0x7 + +==FlexCAN loopback functional example -- Finish.== +~~~~~~~~~~~~~~~~~~~~~ + diff --git a/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/CMakeLists.txt b/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/CMakeLists.txt new file mode 100644 index 000000000..43916559a --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/CMakeLists.txt @@ -0,0 +1,111 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(canfd_loopback_transfer) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME canfd_loopback_transfer.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../flexcan_loopback_transfer.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/devices/MIMX9352/utilities/debug_console_lite + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(utility_debug_console_lite_MIMX9352) + +include(utility_assert_lite_MIMX9352) + +include(driver_lpi2c_MIMX9352) + +include(driver_flexcan_MIMX9352) + +include(driver_clock_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_lists_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/build_all.bat b/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/build_all.bat new file mode 100644 index 000000000..1205ab083 --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/build_all.bat @@ -0,0 +1,15 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/build_all.sh b/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/build_all.sh new file mode 100755 index 000000000..8cc56b74f --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/build_debug.bat b/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/build_debug.sh b/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/build_release.bat b/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/build_release.sh b/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/clean.bat b/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/clean.sh b/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/config.cmake b/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/config.cmake new file mode 100755 index 000000000..920520e3d --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/flags.cmake b/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/flags.cmake new file mode 100755 index 000000000..b44a34afe --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback_transfer/armgcc/flags.cmake @@ -0,0 +1,187 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DFLEXCAN_WAIT_TIMEOUT=1000 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DFLEXCAN_WAIT_TIMEOUT=1000 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/driver_examples/canfd/loopback_transfer/board.c b/boards/som_mx93/driver_examples/canfd/loopback_transfer/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback_transfer/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/driver_examples/canfd/loopback_transfer/board.h b/boards/som_mx93/driver_examples/canfd/loopback_transfer/board.h new file mode 100644 index 000000000..e20723f41 --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback_transfer/board.h @@ -0,0 +1,71 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + + + + + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/driver_examples/canfd/loopback_transfer/clock_config.c b/boards/som_mx93/driver_examples/canfd/loopback_transfer/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback_transfer/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/driver_examples/canfd/loopback_transfer/clock_config.h b/boards/som_mx93/driver_examples/canfd/loopback_transfer/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback_transfer/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/driver_examples/canfd/loopback_transfer/flexcan_loopback_transfer.c b/boards/som_mx93/driver_examples/canfd/loopback_transfer/flexcan_loopback_transfer.c new file mode 100644 index 000000000..08c3b85c7 --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback_transfer/flexcan_loopback_transfer.c @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_debug_console.h" +#include "fsl_flexcan.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" + +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define EXAMPLE_CAN CAN1 +#define RX_MESSAGE_BUFFER_NUM (7) +#define TX_MESSAGE_BUFFER_NUM (6) +#define USE_CANFD (1) + +#define FLEXCAN_CLOCK_ROOT kCLOCK_Root_Can1 +#define EXAMPLE_CAN_CLK_FREQ CLOCK_GetIpFreq(FLEXCAN_CLOCK_ROOT) +/* Set USE_IMPROVED_TIMING_CONFIG macro to use api to calculates the improved CAN / CAN FD timing values. */ +#define USE_IMPROVED_TIMING_CONFIG (1U) +/* Fix MISRA_C-2012 Rule 17.7. */ +#define LOG_INFO (void)PRINTF + +#if (defined(USE_CANFD) && USE_CANFD) +/* + * DWORD_IN_MB DLC BYTES_IN_MB Maximum MBs + * 2 8 kFLEXCAN_8BperMB 64 + * 4 10 kFLEXCAN_16BperMB 42 + * 8 13 kFLEXCAN_32BperMB 25 + * 16 15 kFLEXCAN_64BperMB 14 + * + * Dword in each message buffer, Length of data in bytes, Payload size must align, + * and the Message Buffers are limited corresponding to each payload configuration: + */ +#define DWORD_IN_MB (16) +#define DLC (15) +#define BYTES_IN_MB kFLEXCAN_64BperMB +#else +#define DLC (8) +#endif +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +volatile bool txComplete = false; +volatile bool rxComplete = false; +flexcan_handle_t flexcanHandle; +flexcan_mb_transfer_t txXfer, rxXfer; +#if (defined(USE_CANFD) && USE_CANFD) +flexcan_fd_frame_t txFrame, rxFrame; +#else +flexcan_frame_t txFrame, rxFrame; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief FlexCAN Call Back function + */ +static FLEXCAN_CALLBACK(flexcan_callback) +{ + switch (status) + { + /* Process FlexCAN Rx event. */ + case kStatus_FLEXCAN_RxIdle: + if (RX_MESSAGE_BUFFER_NUM == result) + { + rxComplete = true; + } + break; + + /* Process FlexCAN Tx event. */ + case kStatus_FLEXCAN_TxIdle: + if (TX_MESSAGE_BUFFER_NUM == result) + { + txComplete = true; + } + break; + + default: + break; + } +} + +/*! + * @brief Main function + */ +int main(void) +{ + flexcan_config_t flexcanConfig; + flexcan_rx_mb_config_t mbConfig; + + /* Initialize board hardware. */ + /* clang-format off */ + + const clock_root_config_t flexcanClkCfg = { + .clockOff = false, + .mux = 0, + .div = 1 + }; + /* clang-format on */ + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + + CLOCK_SetRootClock(FLEXCAN_CLOCK_ROOT, &flexcanClkCfg); + + LOG_INFO("\r\n==FlexCAN loopback example -- Start.==\r\n\r\n"); + + /* Init FlexCAN module. */ + /* + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrc0; + * flexcanConfig.bitRate = 1000000U; + * flexcanConfig.bitRateFD = 2000000U; + * flexcanConfig.maxMbNum = 16; + * flexcanConfig.enableLoopBack = false; + * flexcanConfig.enableSelfWakeup = false; + * flexcanConfig.enableIndividMask = false; + * flexcanConfig.disableSelfReception = false; + * flexcanConfig.enableListenOnlyMode = false; + * flexcanConfig.enableDoze = false; + */ + FLEXCAN_GetDefaultConfig(&flexcanConfig); + +#if defined(EXAMPLE_CAN_CLK_SOURCE) + flexcanConfig.clkSrc = EXAMPLE_CAN_CLK_SOURCE; +#endif + + flexcanConfig.enableLoopBack = true; + +#if (defined(USE_IMPROVED_TIMING_CONFIG) && USE_IMPROVED_TIMING_CONFIG) + flexcan_timing_config_t timing_config; + memset(&timing_config, 0, sizeof(flexcan_timing_config_t)); +#if (defined(USE_CANFD) && USE_CANFD) + if (FLEXCAN_FDCalculateImprovedTimingValues(EXAMPLE_CAN, flexcanConfig.bitRate, flexcanConfig.bitRateFD, + EXAMPLE_CAN_CLK_FREQ, &timing_config)) + { + /* Update the improved timing configuration*/ + memcpy(&(flexcanConfig.timingConfig), &timing_config, sizeof(flexcan_timing_config_t)); + } + else + { + LOG_INFO("No found Improved Timing Configuration. Just used default configuration\r\n\r\n"); + } +#else + if (FLEXCAN_CalculateImprovedTimingValues(EXAMPLE_CAN, flexcanConfig.bitRate, EXAMPLE_CAN_CLK_FREQ, &timing_config)) + { + /* Update the improved timing configuration*/ + memcpy(&(flexcanConfig.timingConfig), &timing_config, sizeof(flexcan_timing_config_t)); + } + else + { + LOG_INFO("No found Improved Timing Configuration. Just used default configuration\r\n\r\n"); + } +#endif +#endif + +#if (defined(USE_CANFD) && USE_CANFD) + FLEXCAN_FDInit(EXAMPLE_CAN, &flexcanConfig, EXAMPLE_CAN_CLK_FREQ, BYTES_IN_MB, true); +#else + FLEXCAN_Init(EXAMPLE_CAN, &flexcanConfig, EXAMPLE_CAN_CLK_FREQ); +#endif + + /* Setup Rx Message Buffer. */ + mbConfig.format = kFLEXCAN_FrameFormatStandard; + mbConfig.type = kFLEXCAN_FrameTypeData; + mbConfig.id = FLEXCAN_ID_STD(0x123); +#if (defined(USE_CANFD) && USE_CANFD) + FLEXCAN_SetFDRxMbConfig(EXAMPLE_CAN, RX_MESSAGE_BUFFER_NUM, &mbConfig, true); +#else + FLEXCAN_SetRxMbConfig(EXAMPLE_CAN, RX_MESSAGE_BUFFER_NUM, &mbConfig, true); +#endif + +/* Setup Tx Message Buffer. */ +#if (defined(USE_CANFD) && USE_CANFD) + FLEXCAN_SetFDTxMbConfig(EXAMPLE_CAN, TX_MESSAGE_BUFFER_NUM, true); +#else + FLEXCAN_SetTxMbConfig(EXAMPLE_CAN, TX_MESSAGE_BUFFER_NUM, true); +#endif + + /* Create FlexCAN handle structure and set call back function. */ + FLEXCAN_TransferCreateHandle(EXAMPLE_CAN, &flexcanHandle, flexcan_callback, NULL); + + /* Start receive data through Rx Message Buffer. */ + rxXfer.mbIdx = (uint8_t)RX_MESSAGE_BUFFER_NUM; +#if (defined(USE_CANFD) && USE_CANFD) + rxXfer.framefd = &rxFrame; + (void)FLEXCAN_TransferFDReceiveNonBlocking(EXAMPLE_CAN, &flexcanHandle, &rxXfer); +#else + rxXfer.frame = &rxFrame; + (void)FLEXCAN_TransferReceiveNonBlocking(EXAMPLE_CAN, &flexcanHandle, &rxXfer); +#endif + + /* Prepare Tx Frame for sending. */ + txFrame.format = (uint8_t)kFLEXCAN_FrameFormatStandard; + txFrame.type = (uint8_t)kFLEXCAN_FrameTypeData; + txFrame.id = FLEXCAN_ID_STD(0x123); + txFrame.length = (uint8_t)DLC; +#if (defined(USE_CANFD) && USE_CANFD) + txFrame.brs = 1U; + txFrame.edl = 1U; +#endif +#if (defined(USE_CANFD) && USE_CANFD) + uint8_t i = 0; + for (i = 0; i < DWORD_IN_MB; i++) + { + txFrame.dataWord[i] = i; + } +#else + txFrame.dataWord0 = CAN_WORD0_DATA_BYTE_0(0x11) | CAN_WORD0_DATA_BYTE_1(0x22) | CAN_WORD0_DATA_BYTE_2(0x33) | + CAN_WORD0_DATA_BYTE_3(0x44); + txFrame.dataWord1 = CAN_WORD1_DATA_BYTE_4(0x55) | CAN_WORD1_DATA_BYTE_5(0x66) | CAN_WORD1_DATA_BYTE_6(0x77) | + CAN_WORD1_DATA_BYTE_7(0x88); +#endif + + LOG_INFO("Send message from MB%d to MB%d\r\n", TX_MESSAGE_BUFFER_NUM, RX_MESSAGE_BUFFER_NUM); +#if (defined(USE_CANFD) && USE_CANFD) + for (i = 0; i < DWORD_IN_MB; i++) + { + LOG_INFO("tx word%d = 0x%x\r\n", i, txFrame.dataWord[i]); + } +#else + LOG_INFO("tx word0 = 0x%x\r\n", txFrame.dataWord0); + LOG_INFO("tx word1 = 0x%x\r\n", txFrame.dataWord1); +#endif + + /* Send data through Tx Message Buffer. */ + txXfer.mbIdx = (uint8_t)TX_MESSAGE_BUFFER_NUM; +#if (defined(USE_CANFD) && USE_CANFD) + txXfer.framefd = &txFrame; + (void)FLEXCAN_TransferFDSendNonBlocking(EXAMPLE_CAN, &flexcanHandle, &txXfer); +#else + txXfer.frame = &txFrame; + (void)FLEXCAN_TransferSendNonBlocking(EXAMPLE_CAN, &flexcanHandle, &txXfer); +#endif + + /* Waiting for Rx Message finish. */ + while ((!rxComplete) || (!txComplete)) + { + }; + + LOG_INFO("\r\nReceived message from MB%d\r\n", RX_MESSAGE_BUFFER_NUM); +#if (defined(USE_CANFD) && USE_CANFD) + for (i = 0; i < DWORD_IN_MB; i++) + { + LOG_INFO("rx word%d = 0x%x\r\n", i, rxFrame.dataWord[i]); + } +#else + LOG_INFO("rx word0 = 0x%x\r\n", rxFrame.dataWord0); + LOG_INFO("rx word1 = 0x%x\r\n", rxFrame.dataWord1); +#endif + + LOG_INFO("\r\n==FlexCAN loopback example -- Finish.==\r\n"); + + while (true) + { + } +} diff --git a/boards/som_mx93/driver_examples/canfd/loopback_transfer/pin_mux.c b/boards/som_mx93/driver_examples/canfd/loopback_transfer/pin_mux.c new file mode 100644 index 000000000..10cb5de9d --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback_transfer/pin_mux.c @@ -0,0 +1,87 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: J17, peripheral: CAN1, signal: can_rx, pin_signal: PDM_BIT_STREAM0, APC: DOMAIN0_ACCESS, HYS: DISABLED} + - {pin_num: G17, peripheral: CAN1, signal: can_tx, pin_signal: PDM_CLK, HYS: DISABLED} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, HYS: DISABLED, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, HYS: DISABLED, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_I2C1_SCL__LPI2C1_SCL, 1U); + IOMUXC_SetPinMux(IOMUXC_PAD_I2C1_SDA__LPI2C1_SDA, 1U); + IOMUXC_SetPinMux(IOMUXC_PAD_PDM_BIT_STREAM0__CAN1_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_PDM_CLK__CAN1_TX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_I2C1_SCL__LPI2C1_SCL, + IOMUXC_PAD_DSE(15U) | + IOMUXC_PAD_FSEL1(2U) | + IOMUXC_PAD_OD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_I2C1_SDA__LPI2C1_SDA, + IOMUXC_PAD_DSE(15U) | + IOMUXC_PAD_FSEL1(2U) | + IOMUXC_PAD_OD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_PDM_BIT_STREAM0__CAN1_RX, + IOMUXC_PAD_DSE(15U) | + IOMUXC_PAD_FSEL1(2U) | + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_PDM_CLK__CAN1_TX, + IOMUXC_PAD_DSE(15U) | + IOMUXC_PAD_FSEL1(2U) | + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/canfd/loopback_transfer/pin_mux.h b/boards/som_mx93/driver_examples/canfd/loopback_transfer/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback_transfer/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/canfd/loopback_transfer/readme.txt b/boards/som_mx93/driver_examples/canfd/loopback_transfer/readme.txt new file mode 100644 index 000000000..70e2d6644 --- /dev/null +++ b/boards/som_mx93/driver_examples/canfd/loopback_transfer/readme.txt @@ -0,0 +1,69 @@ +Overview +======== +The flexcan_loopback example shows how to use the loopback test mode to debug your CAN Bus design: + +To demonstrates this example, only one board is needed. The example will config one FlexCAN Message +Buffer to Rx Message Buffer and the other FlexCAN Message Buffer to Tx Message Buffer with same ID. +After that, the example will send a CAN Message from the Tx Message Buffer to the Rx Message Buffer +through internal loopback interconnect and print out the Message payload to terminal. + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Micro USB cable +- USB to UART Adapter +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Proper power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + +Prepare the Demo +================ +1. Connect the power supply to the board and switch on the board. +2. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +3. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +When the example runs successfully, you can see the similar information from the terminal as below. + +~~~~~~~~~~~~~~~~~~~~~ +==FlexCAN loopback functional example -- Start.== + +Send message from MB0 to MB1 +tx word0 = 0x0 +tx word1 = 0x1 +tx word2 = 0x2 +tx word3 = 0x3 +tx word4 = 0x4 +tx word5 = 0x5 +tx word6 = 0x6 +tx word7 = 0x7 + +Received message from MB1 +rx word0 = 0x0 +rx word1 = 0x1 +rx word2 = 0x2 +rx word3 = 0x3 +rx word4 = 0x4 +rx word5 = 0x5 +rx word6 = 0x6 +rx word7 = 0x7 + +==FlexCAN loopback functional example -- Finish.== +~~~~~~~~~~~~~~~~~~~~~ + diff --git a/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/CMakeLists.txt b/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/CMakeLists.txt new file mode 100644 index 000000000..3feb1248e --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/CMakeLists.txt @@ -0,0 +1,112 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(dma3_memory_to_memory) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME dma3_memory_to_memory.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../edma_memory_to_memory.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/devices/MIMX9352/utilities/debug_console_lite + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352/drivers/dma3 + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(utility_debug_console_lite_MIMX9352) + +include(utility_assert_lite_MIMX9352) + +include(driver_clock_MIMX9352) + +include(driver_dma3_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_lists_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(driver_memory_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/build_all.bat b/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/build_all.bat new file mode 100644 index 000000000..1205ab083 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/build_all.bat @@ -0,0 +1,15 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/build_all.sh b/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/build_all.sh new file mode 100755 index 000000000..8cc56b74f --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/build_debug.bat b/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/build_debug.sh b/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/build_release.bat b/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/build_release.sh b/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/clean.bat b/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/clean.sh b/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/config.cmake b/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/config.cmake new file mode 100755 index 000000000..920520e3d --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/flags.cmake b/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/flags.cmake new file mode 100755 index 000000000..bf4fa0ef5 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/memory_to_memory/armgcc/flags.cmake @@ -0,0 +1,185 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/driver_examples/edma/memory_to_memory/board.c b/boards/som_mx93/driver_examples/edma/memory_to_memory/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/memory_to_memory/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/driver_examples/edma/memory_to_memory/board.h b/boards/som_mx93/driver_examples/edma/memory_to_memory/board.h new file mode 100644 index 000000000..5108807ef --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/memory_to_memory/board.h @@ -0,0 +1,89 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + +/* ADP5585 */ +#define BOARD_ADP5585_I2C LPI2C2 +#define BOARD_ADP5585_I2C_ADDR (0x34U) +#define BOARD_ADP5585_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_ADP5585_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_ADP5585_I2C_CLOCK_ROOT) + +#define BOARD_ADP5585_PDM_MQS_SEL (2U) +#define BOARD_ADP5585_EXP_SEL (4U) +#define BOARD_ADP5585_CAN_STBY (8U) + +/* PCAL6524 */ +#define BOARD_PCAL6524_I2C LPI2C2 +#define BOARD_PCAL6524_I2C_ADDR (0x22U) +#define BOARD_PCAL6524_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_PCAL6524_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_PCAL6524_I2C_CLOCK_ROOT) + +#define BOARD_PCAL6524_ENET1_NRST (8U + 7U) +#define BOARD_PCAL6524_ENET2_NRST (16U + 0U) +#define BOARD_PCAL6524_MIC_CAN_SEL (16U + 1U) +#define BOARD_PCAL6524_EXP_SEL (16U + 6U) +#define BOARD_PCAL6524_CAN_STBY (16U + 7U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/driver_examples/edma/memory_to_memory/clock_config.c b/boards/som_mx93/driver_examples/edma/memory_to_memory/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/memory_to_memory/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/driver_examples/edma/memory_to_memory/clock_config.h b/boards/som_mx93/driver_examples/edma/memory_to_memory/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/memory_to_memory/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/driver_examples/edma/memory_to_memory/edma_memory_to_memory.c b/boards/som_mx93/driver_examples/edma/memory_to_memory/edma_memory_to_memory.c new file mode 100644 index 000000000..1e27e6d89 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/memory_to_memory/edma_memory_to_memory.c @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_debug_console.h" +#include "fsl_edma.h" + +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define EXAMPLE_DMA_CHANNEL 30U +#define EXAMPLE_DMA_BASEADDR DMA3 +#define EXAMPLE_DMA_CLOCK_ROOT kCLOCK_Root_WakeupAxi +#define BUFF_LENGTH 4U + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +edma_handle_t g_EDMA_Handle; +volatile bool g_Transfer_Done = false; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* User callback function for EDMA transfer. */ +void EDMA_Callback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) +{ + if (transferDone) + { + g_Transfer_Done = true; + } +} + +AT_NONCACHEABLE_SECTION_INIT(uint32_t srcAddr[BUFF_LENGTH]) = {0x01, 0x02, 0x03, 0x04}; +AT_NONCACHEABLE_SECTION_INIT(uint32_t destAddr[BUFF_LENGTH]) = {0x00, 0x00, 0x00, 0x00}; + +/*! + * @brief Main function + */ +int main(void) +{ + uint32_t i; + edma_transfer_config_t transferConfig; + edma_config_t userConfig; + + /* clang-format off */ + + /* 250MHz DMA clock */ + const clock_root_config_t dmaClkCfg = { + .clockOff = false, + .mux = kCLOCK_WAKEUPAXI_ClockRoot_MuxSysPll1Pfd0, // 1000MHz + .div = 4 + }; + /* clang-format on */ + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + + CLOCK_SetRootClock(EXAMPLE_DMA_CLOCK_ROOT, &dmaClkCfg); + /* Print destination buffer */ + PRINTF("EDMA memory to memory transfer example begin.\r\n\r\n"); + PRINTF("Destination Buffer:\r\n"); + for (i = 0; i < BUFF_LENGTH; i++) + { + PRINTF("%d\t", destAddr[i]); + } + /* Configure EDMA one shot transfer */ + /* + * userConfig.enableMasterIdReplication = true; + * userConfig.enableHaltOnError = true; + * userConfig.enableRoundRobinArbitration = false; + * userConfig.enableDebugMode = false; + * userConfig.enableBufferedWrites = false; + */ + EDMA_GetDefaultConfig(&userConfig); + EDMA_Init(EXAMPLE_DMA_BASEADDR, &userConfig); + EDMA_CreateHandle(&g_EDMA_Handle, EXAMPLE_DMA_BASEADDR, EXAMPLE_DMA_CHANNEL); + EDMA_SetCallback(&g_EDMA_Handle, EDMA_Callback, NULL); + EDMA_PrepareTransfer(&transferConfig, srcAddr, sizeof(srcAddr[0]), destAddr, sizeof(destAddr[0]), sizeof(srcAddr), + sizeof(srcAddr), kEDMA_MemoryToMemory); + EDMA_SubmitTransfer(&g_EDMA_Handle, &transferConfig); + + /* Trigger transfer start */ + EDMA_TriggerChannelStart(EXAMPLE_DMA_BASEADDR, EXAMPLE_DMA_CHANNEL); + + /* Wait for EDMA transfer finish */ + while (g_Transfer_Done != true) + { + } + /* Print destination buffer */ + PRINTF("\r\n\r\nEDMA memory to memory transfer example finish.\r\n\r\n"); + PRINTF("Destination Buffer:\r\n"); + for (i = 0; i < BUFF_LENGTH; i++) + { + PRINTF("%d\t", destAddr[i]); + } + while (1) + { + } +} diff --git a/boards/som_mx93/driver_examples/edma/memory_to_memory/pin_mux.c b/boards/som_mx93/driver_examples/edma/memory_to_memory/pin_mux.c new file mode 100644 index 000000000..4c8d6a119 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/memory_to_memory/pin_mux.c @@ -0,0 +1,65 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/edma/memory_to_memory/pin_mux.h b/boards/som_mx93/driver_examples/edma/memory_to_memory/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/memory_to_memory/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/edma/memory_to_memory/readme.txt b/boards/som_mx93/driver_examples/edma/memory_to_memory/readme.txt new file mode 100644 index 000000000..e3a762778 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/memory_to_memory/readme.txt @@ -0,0 +1,51 @@ +Overview +======== +The EDMA memory to memory example is a simple demonstration program that uses the SDK software. +It executes one shot transfer from source buffer to destination buffer using the SDK EDMA drivers. +The purpose of this example is to show how to use the EDMA and to provide a simple example for +debugging and further development. + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Micro USB cable +- USB to UART Adapter +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Proper power supply +- Personal Computer + +Board settings +============== +No special is needed. + +Prepare the Demo +================ +1. Connect the power supply to the board and switch on the board. +2. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +3. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +When the example runs successfully, you can see the similar information from the terminal as below. +~~~~~~~~~~~~~~~~~~~~~ +EDMA memory to memory transfer example begin. + +Destination Buffer: +0 0 0 0 + +EDMA memory to memory transfer example finish. + +Destination Buffer: +1 2 3 4 +~~~~~~~~~~~~~~~~~~~~~ + diff --git a/boards/som_mx93/driver_examples/edma/scatter_gather/armgcc/CMakeLists.txt b/boards/som_mx93/driver_examples/edma/scatter_gather/armgcc/CMakeLists.txt new file mode 100644 index 000000000..835d7c560 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/scatter_gather/armgcc/CMakeLists.txt @@ -0,0 +1,112 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(dma3_scatter_gather) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME dma3_scatter_gather.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../edma_scatter_gather.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/devices/MIMX9352/utilities/debug_console_lite + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352/drivers/dma3 + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(utility_debug_console_lite_MIMX9352) + +include(utility_assert_lite_MIMX9352) + +include(driver_clock_MIMX9352) + +include(driver_dma3_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_lists_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(driver_memory_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/driver_examples/edma/scatter_gather/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/driver_examples/edma/scatter_gather/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/scatter_gather/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/driver_examples/edma/scatter_gather/armgcc/build_all.bat b/boards/som_mx93/driver_examples/edma/scatter_gather/armgcc/build_all.bat new file mode 100644 index 000000000..1205ab083 --- /dev/null +++ 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-DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/edma/scatter_gather/armgcc/build_release.sh b/boards/som_mx93/driver_examples/edma/scatter_gather/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/scatter_gather/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/edma/scatter_gather/armgcc/clean.bat b/boards/som_mx93/driver_examples/edma/scatter_gather/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/scatter_gather/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/driver_examples/edma/scatter_gather/armgcc/clean.sh b/boards/som_mx93/driver_examples/edma/scatter_gather/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/scatter_gather/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/driver_examples/edma/scatter_gather/armgcc/config.cmake b/boards/som_mx93/driver_examples/edma/scatter_gather/armgcc/config.cmake new file mode 100755 index 000000000..920520e3d --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/scatter_gather/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/driver_examples/edma/scatter_gather/armgcc/flags.cmake b/boards/som_mx93/driver_examples/edma/scatter_gather/armgcc/flags.cmake new file mode 100755 index 000000000..bf4fa0ef5 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/scatter_gather/armgcc/flags.cmake @@ -0,0 +1,185 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/driver_examples/edma/scatter_gather/board.c b/boards/som_mx93/driver_examples/edma/scatter_gather/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/scatter_gather/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/driver_examples/edma/scatter_gather/board.h b/boards/som_mx93/driver_examples/edma/scatter_gather/board.h new file mode 100644 index 000000000..5108807ef --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/scatter_gather/board.h @@ -0,0 +1,89 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + +/* ADP5585 */ +#define BOARD_ADP5585_I2C LPI2C2 +#define BOARD_ADP5585_I2C_ADDR (0x34U) +#define BOARD_ADP5585_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_ADP5585_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_ADP5585_I2C_CLOCK_ROOT) + +#define BOARD_ADP5585_PDM_MQS_SEL (2U) +#define BOARD_ADP5585_EXP_SEL (4U) +#define BOARD_ADP5585_CAN_STBY (8U) + +/* PCAL6524 */ +#define BOARD_PCAL6524_I2C LPI2C2 +#define BOARD_PCAL6524_I2C_ADDR (0x22U) +#define BOARD_PCAL6524_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_PCAL6524_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_PCAL6524_I2C_CLOCK_ROOT) + +#define BOARD_PCAL6524_ENET1_NRST (8U + 7U) +#define BOARD_PCAL6524_ENET2_NRST (16U + 0U) +#define BOARD_PCAL6524_MIC_CAN_SEL (16U + 1U) +#define BOARD_PCAL6524_EXP_SEL (16U + 6U) +#define BOARD_PCAL6524_CAN_STBY (16U + 7U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/driver_examples/edma/scatter_gather/clock_config.c b/boards/som_mx93/driver_examples/edma/scatter_gather/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/scatter_gather/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/driver_examples/edma/scatter_gather/clock_config.h b/boards/som_mx93/driver_examples/edma/scatter_gather/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/scatter_gather/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/driver_examples/edma/scatter_gather/edma_scatter_gather.c b/boards/som_mx93/driver_examples/edma/scatter_gather/edma_scatter_gather.c new file mode 100644 index 000000000..a7a47ae3d --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/scatter_gather/edma_scatter_gather.c @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_debug_console.h" +#include "fsl_edma.h" +#include + +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define EXAMPLE_DMA_CHANNEL 30U +#define EXAMPLE_DMA_BASEADDR DMA3 +#define EXAMPLE_DMA_CLOCK_ROOT kCLOCK_Root_WakeupAxi +#define BUFF_LENGTH 8U +#define HALF_BUFF_LENGTH (BUFF_LENGTH / 2U) +#define TCD_QUEUE_SIZE 2U + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +edma_handle_t g_EDMA_Handle; +volatile bool g_Transfer_Done[TCD_QUEUE_SIZE] = {0}; + +AT_NONCACHEABLE_SECTION_INIT(uint32_t srcAddr[BUFF_LENGTH]) = {0x01U, 0x02U, 0x03U, 0x04U, 0x05U, 0x06U, 0x07U, 0x08U}; +AT_NONCACHEABLE_SECTION_INIT(uint32_t destAddr[BUFF_LENGTH]) = {0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U}; +/* Allocate TCD memory poll */ +AT_QUICKACCESS_SECTION_DATA_ALIGN(edma_tcd_t tcdMemoryPoolPtr[TCD_QUEUE_SIZE], sizeof(edma_tcd_t)); +static volatile uint32_t count = 0; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* User callback function for EDMA transfer. */ +void EDMA_Callback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) +{ + if (transferDone) + { + g_Transfer_Done[count] = true; + } + count++; +} + +/*! + * @brief Main function + */ +int main(void) +{ + uint32_t i = 0; + edma_transfer_config_t transferConfig; + edma_config_t userConfig; + + /* clang-format off */ + + /* 250MHz DMA clock */ + const clock_root_config_t dmaClkCfg = { + .clockOff = false, + .mux = kCLOCK_WAKEUPAXI_ClockRoot_MuxSysPll1Pfd0, // 1000MHz + .div = 4 + }; + /* clang-format on */ + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + + CLOCK_SetRootClock(EXAMPLE_DMA_CLOCK_ROOT, &dmaClkCfg); + /* Print source buffer */ + PRINTF("\r\nEDMA scatter gather transfer example begin.\r\n\r\n"); + PRINTF("\r\nDestination Buffer:\r\n"); + for (i = 0; i < BUFF_LENGTH; i++) + { + PRINTF("%d\t", destAddr[i]); + } + /* Configure EDMA one shot transfer */ + /* + * userConfig.enableMasterIdReplication = true; + * userConfig.enableHaltOnError = true; + * userConfig.enableRoundRobinArbitration = false; + * userConfig.enableDebugMode = false; + * userConfig.enableBufferedWrites = false; + */ + EDMA_GetDefaultConfig(&userConfig); + EDMA_Init(EXAMPLE_DMA_BASEADDR, &userConfig); + EDMA_CreateHandle(&g_EDMA_Handle, EXAMPLE_DMA_BASEADDR, EXAMPLE_DMA_CHANNEL); + EDMA_SetCallback(&g_EDMA_Handle, EDMA_Callback, NULL); + EDMA_ResetChannel(g_EDMA_Handle.base, g_EDMA_Handle.channel); + + EDMA_InstallTCDMemory(&g_EDMA_Handle, tcdMemoryPoolPtr, TCD_QUEUE_SIZE); + /* Configure and submit transfer structure 1 */ + EDMA_PrepareTransfer(&transferConfig, srcAddr, sizeof(srcAddr[0]), destAddr, sizeof(destAddr[0]), + sizeof(srcAddr[0]) * HALF_BUFF_LENGTH, sizeof(srcAddr[0]) * HALF_BUFF_LENGTH, + kEDMA_MemoryToMemory); + EDMA_SubmitTransfer(&g_EDMA_Handle, &transferConfig); + /* Configure and submit transfer structure 2 */ + EDMA_PrepareTransfer(&transferConfig, &srcAddr[4], sizeof(srcAddr[0]), &destAddr[4], sizeof(destAddr[0]), + sizeof(srcAddr[0]) * HALF_BUFF_LENGTH, sizeof(srcAddr[0]) * HALF_BUFF_LENGTH, + kEDMA_MemoryToMemory); + EDMA_SubmitTransfer(&g_EDMA_Handle, &transferConfig); + + /* Trigger transfer start */ + EDMA_TriggerChannelStart(EXAMPLE_DMA_BASEADDR, EXAMPLE_DMA_CHANNEL); + /* Wait for the first TCD finished */ + while (g_Transfer_Done[0] != true) + { + } + + /* Trigger the second tcd */ + EDMA_TriggerChannelStart(EXAMPLE_DMA_BASEADDR, EXAMPLE_DMA_CHANNEL); + /* Wait for the second TCD finished */ + while (g_Transfer_Done[1] != true) + { + } + + /* Print destination buffer */ + PRINTF("\r\n\r\nEDMA scatter gather transfer example finish.\r\n\r\n"); + PRINTF("Destination Buffer:\r\n"); + for (i = 0; i < BUFF_LENGTH; i++) + { + PRINTF("%d\t", destAddr[i]); + } + /* Free the memory space allocated */ + while (1) + { + } +} diff --git a/boards/som_mx93/driver_examples/edma/scatter_gather/pin_mux.c b/boards/som_mx93/driver_examples/edma/scatter_gather/pin_mux.c new file mode 100644 index 000000000..4c8d6a119 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/scatter_gather/pin_mux.c @@ -0,0 +1,65 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/edma/scatter_gather/pin_mux.h b/boards/som_mx93/driver_examples/edma/scatter_gather/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/scatter_gather/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/edma/scatter_gather/readme.txt b/boards/som_mx93/driver_examples/edma/scatter_gather/readme.txt new file mode 100644 index 000000000..1a4227cc6 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma/scatter_gather/readme.txt @@ -0,0 +1,52 @@ +Overview +======== +The EDMA memory to memory example is a simple demonstration program that uses the SDK software. +It excuates one shot transfer from source buffer to destination buffer using the SDK EDMA drivers. +The purpose of this example is to show how to use the EDMA and to provide a simple example for +debugging and further development. + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Micro USB cable +- USB to UART Adapter +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Proper power supply +- Personal Computer + +Board settings +============== +No special is needed. + +Prepare the Demo +================ +1. Connect the power supply to the board and switch on the board. +2. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +3. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + + +Running the demo +================ +When the example runs successfully, you can see the similar information from the terminal as below. + +~~~~~~~~~~~~~~~~~~~~~ +EDMA scatter_gather transfer example begin. + +Destination Buffer: +0 0 0 0 0 0 0 0 + +EDMA scatter_gather transfer example finish. + +Destination Buffer: +1 2 3 4 5 6 7 8 +~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/CMakeLists.txt b/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/CMakeLists.txt new file mode 100644 index 000000000..c089a81f2 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/CMakeLists.txt @@ -0,0 +1,114 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(edma4_channel_link) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME edma4_channel_link.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../edma_channel_link.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/devices/MIMX9352/utilities/debug_console_lite + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352/drivers/edma4 + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(utility_debug_console_lite_MIMX9352) + +include(utility_assert_lite_MIMX9352) + +include(driver_memory_MIMX9352) + +include(driver_clock_MIMX9352) + +include(driver_edma4_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_lists_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(driver_edma_soc_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/build_all.bat b/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/build_all.bat new file mode 100644 index 000000000..1205ab083 --- /dev/null +++ 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b/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/build_all.sh new file mode 100755 index 000000000..8cc56b74f --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/build_debug.bat b/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/build_debug.sh b/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/build_release.bat b/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/build_release.sh b/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/clean.bat b/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/clean.sh b/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/config.cmake b/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/config.cmake new file mode 100755 index 000000000..920520e3d --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/flags.cmake b/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/flags.cmake new file mode 100755 index 000000000..bf4fa0ef5 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/channel_link/armgcc/flags.cmake @@ -0,0 +1,185 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/driver_examples/edma4/channel_link/board.c b/boards/som_mx93/driver_examples/edma4/channel_link/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/channel_link/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/driver_examples/edma4/channel_link/board.h b/boards/som_mx93/driver_examples/edma4/channel_link/board.h new file mode 100644 index 000000000..5108807ef --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/channel_link/board.h @@ -0,0 +1,89 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + +/* ADP5585 */ +#define BOARD_ADP5585_I2C LPI2C2 +#define BOARD_ADP5585_I2C_ADDR (0x34U) +#define BOARD_ADP5585_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_ADP5585_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_ADP5585_I2C_CLOCK_ROOT) + +#define BOARD_ADP5585_PDM_MQS_SEL (2U) +#define BOARD_ADP5585_EXP_SEL (4U) +#define BOARD_ADP5585_CAN_STBY (8U) + +/* PCAL6524 */ +#define BOARD_PCAL6524_I2C LPI2C2 +#define BOARD_PCAL6524_I2C_ADDR (0x22U) +#define BOARD_PCAL6524_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_PCAL6524_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_PCAL6524_I2C_CLOCK_ROOT) + +#define BOARD_PCAL6524_ENET1_NRST (8U + 7U) +#define BOARD_PCAL6524_ENET2_NRST (16U + 0U) +#define BOARD_PCAL6524_MIC_CAN_SEL (16U + 1U) +#define BOARD_PCAL6524_EXP_SEL (16U + 6U) +#define BOARD_PCAL6524_CAN_STBY (16U + 7U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/driver_examples/edma4/channel_link/clock_config.c b/boards/som_mx93/driver_examples/edma4/channel_link/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/channel_link/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/driver_examples/edma4/channel_link/clock_config.h b/boards/som_mx93/driver_examples/edma4/channel_link/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/channel_link/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/driver_examples/edma4/channel_link/edma_channel_link.c b/boards/som_mx93/driver_examples/edma4/channel_link/edma_channel_link.c new file mode 100644 index 000000000..2fcfb1f29 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/channel_link/edma_channel_link.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_debug_console.h" +#include "fsl_edma.h" + +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define EXAMPLE_DMA_BASEADDR DMA4 +#define EXAMPLE_DMA_CLOCK_ROOT kCLOCK_Root_WakeupAxi +#define DEMO_DMA_CHANNEL_0 0 +#define DEMO_DMA_CHANNEL_1 1 +#define DEMO_DMA_CHANNEL_2 2 +#define APP_DMA_IRQ DMA4_2_3_IRQn +#define APP_DMA_IRQ_HANDLER DMA4_2_3_IRQHandler + +#define BUFFER_LENGTH 4U + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +volatile bool g_Transfer_Done = false; + +AT_NONCACHEABLE_SECTION_INIT(uint32_t srcAddr[BUFFER_LENGTH]) = {0x01U, 0x02U, 0x03U, 0x04U}; +AT_NONCACHEABLE_SECTION_INIT(uint32_t destAddr0[BUFFER_LENGTH]) = {0x00U, 0x00U, 0x00U, 0x00U}; +AT_NONCACHEABLE_SECTION_INIT(uint32_t destAddr1[BUFFER_LENGTH]) = {0x00U, 0x00U, 0x00U, 0x00U}; +AT_NONCACHEABLE_SECTION_INIT(uint32_t destAddr2[BUFFER_LENGTH]) = {0x00U, 0x00U, 0x00U, 0x00U}; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* EDMA transfer channel 0 IRQ handler */ +void APP_DMA_IRQ_HANDLER(void) +{ + if ((EDMA_GetChannelStatusFlags(EXAMPLE_DMA_BASEADDR, DEMO_DMA_CHANNEL_2) & kEDMA_InterruptFlag) != 0U) + { + EDMA_ClearChannelStatusFlags(EXAMPLE_DMA_BASEADDR, DEMO_DMA_CHANNEL_2, kEDMA_InterruptFlag); + g_Transfer_Done = true; + } +} + +/*! + * @brief Main function + */ +int main(void) +{ + uint32_t i; + edma_transfer_config_t transferConfig0; + edma_transfer_config_t transferConfig1; + edma_transfer_config_t transferConfig2; + edma_config_t userConfig; + + /* clang-format off */ + /* 250MHz DMA clock */ + const clock_root_config_t dmaClkCfg = { + .clockOff = false, + .mux = kCLOCK_WAKEUPAXI_ClockRoot_MuxSysPll1Pfd0, // 1000MHz + .div = 4 + }; + /* clang-format on */ + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + + CLOCK_SetRootClock(EXAMPLE_DMA_CLOCK_ROOT, &dmaClkCfg); + + /* Print destination buffer */ + PRINTF("EDMA channel link example begin.\r\n\r\n"); + PRINTF("Destination Buffer 0:\r\n"); + for (i = 0; i < BUFFER_LENGTH; i++) + { + PRINTF("%d\t", destAddr0[i]); + } + PRINTF("\r\n\r\nDestination Buffer 1:\r\n"); + for (i = 0; i < BUFFER_LENGTH; i++) + { + PRINTF("%d\t", destAddr1[i]); + } + PRINTF("\r\n\r\nDestination Buffer 2:\r\n"); + for (i = 0; i < BUFFER_LENGTH; i++) + { + PRINTF("%d\t", destAddr2[i]); + } + + EDMA_GetDefaultConfig(&userConfig); + EDMA_Init(EXAMPLE_DMA_BASEADDR, &userConfig); + + EDMA_PrepareTransfer(&transferConfig0, srcAddr, sizeof(srcAddr[0]), destAddr0, sizeof(destAddr0[0]), + sizeof(destAddr0) / 2, sizeof(destAddr0), kEDMA_MemoryToMemory); + transferConfig0.enabledInterruptMask = 0U; + transferConfig0.enableChannelMinorLoopLink = true; + transferConfig0.enableChannelMajorLoopLink = true; + transferConfig0.minorLoopLinkChannel = DEMO_DMA_CHANNEL_1; + transferConfig0.majorLoopLinkChannel = DEMO_DMA_CHANNEL_2; + + EDMA_PrepareTransfer(&transferConfig1, srcAddr, sizeof(srcAddr[0]), destAddr1, sizeof(destAddr0[0]), + sizeof(uint32_t) * BUFFER_LENGTH, sizeof(destAddr1), kEDMA_MemoryToMemory); + transferConfig1.enabledInterruptMask = 0U; + EDMA_PrepareTransfer(&transferConfig2, srcAddr, sizeof(srcAddr[0]), destAddr2, sizeof(destAddr0[0]), + sizeof(uint32_t) * BUFFER_LENGTH, sizeof(destAddr2), kEDMA_MemoryToMemory); + + EDMA_SetTransferConfig(EXAMPLE_DMA_BASEADDR, DEMO_DMA_CHANNEL_0, &transferConfig0, NULL); + EDMA_SetTransferConfig(EXAMPLE_DMA_BASEADDR, DEMO_DMA_CHANNEL_1, &transferConfig1, NULL); + EDMA_SetTransferConfig(EXAMPLE_DMA_BASEADDR, DEMO_DMA_CHANNEL_2, &transferConfig2, NULL); + + EnableIRQ(APP_DMA_IRQ); + + EDMA_TriggerChannelStart(EXAMPLE_DMA_BASEADDR, DEMO_DMA_CHANNEL_0); + EDMA_TriggerChannelStart(EXAMPLE_DMA_BASEADDR, DEMO_DMA_CHANNEL_0); + + /* Wait for EDMA transfer finish */ + while (g_Transfer_Done != true) + { + } + + /* Print destination buffer */ + PRINTF("\r\n\r\nEDMA channel link example finish.\r\n\r\n"); + PRINTF("Destination Buffer 0:\r\n"); + for (i = 0; i < BUFFER_LENGTH; i++) + { + PRINTF("%d\t", destAddr0[i]); + } + PRINTF("\r\n\r\nDestination Buffer 1:\r\n"); + for (i = 0; i < BUFFER_LENGTH; i++) + { + PRINTF("%d\t", destAddr1[i]); + } + PRINTF("\r\n\r\nDestination Buffer 2:\r\n"); + for (i = 0; i < BUFFER_LENGTH; i++) + { + PRINTF("%d\t", destAddr2[i]); + } + + while (1) + { + } +} diff --git a/boards/som_mx93/driver_examples/edma4/channel_link/pin_mux.c b/boards/som_mx93/driver_examples/edma4/channel_link/pin_mux.c new file mode 100644 index 000000000..4c8d6a119 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/channel_link/pin_mux.c @@ -0,0 +1,65 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/edma4/channel_link/pin_mux.h b/boards/som_mx93/driver_examples/edma4/channel_link/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/channel_link/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/edma4/channel_link/readme.txt b/boards/som_mx93/driver_examples/edma4/channel_link/readme.txt new file mode 100644 index 000000000..8dc23c2ee --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/channel_link/readme.txt @@ -0,0 +1,74 @@ +Overview +======== +The EDMA channel link example is a simple demonstration program that uses the SDK software. +It excuates channel link transfer using the SDK EDMA drivers. +The purpose of this example is to show how to use the EDMA and to provide a simple example for +debugging and further development, it demostrates how to use the minor loop link and major loop link: +Since each transfer request can be divided into MAJOR_LOOPS_COUNTS * MINOR_LOOPS_BYTES, +such as you want to request EDMA transfer 8 bytes total, 4 bytes each request, then MAJOR_LOOPS_COUNTS = 2, MINOR_LOOPS_BYTES = 4. +The minor loop channel linking occurs at the completion of the minor loop 4 byte transferred. +The major loop channel linking is occurs at the major loop exhausted. +The example demostrate the channel link transfer by the feature of edma4: + + + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Mini/micro USB cable +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Personal Computer + +Board settings +============== +No special settings are required. + +Prepare the Demo +================ +1. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +2. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +3. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +When the example runs successfully, you can see the similar information from the terminal as below. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +EDMA channel link example begin. + +Destination Buffer 0: + +0 0 0 0 + +Destination Buffer 1: + +0 0 0 0 + +Destination Buffer 2: + +0 0 0 0 + +EDMA channel link example finish. + +Destination Buffer 0: + +1 2 3 4 + + +Destination Buffer 1: + +1 2 3 4 + +Destination Buffer 2: + +1 2 3 4 +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + diff --git a/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/CMakeLists.txt b/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/CMakeLists.txt new file mode 100644 index 000000000..0eeced0ac --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/CMakeLists.txt @@ -0,0 +1,114 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(edma4_interleave_transfer) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME edma4_interleave_transfer.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../edma_interleave_transfer.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/devices/MIMX9352/utilities/debug_console_lite + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352/drivers/edma4 + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(utility_debug_console_lite_MIMX9352) + +include(utility_assert_lite_MIMX9352) + +include(driver_memory_MIMX9352) + +include(driver_clock_MIMX9352) + +include(driver_edma4_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_lists_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(driver_edma_soc_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/build_all.bat b/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/build_all.bat new file mode 100644 index 000000000..1205ab083 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/build_all.bat @@ -0,0 +1,15 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/build_all.sh b/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/build_all.sh new file mode 100755 index 000000000..8cc56b74f --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/build_debug.bat b/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/build_debug.sh b/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/build_release.bat b/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/build_release.sh b/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/clean.bat b/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/clean.sh b/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/config.cmake b/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/config.cmake new file mode 100755 index 000000000..920520e3d --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/flags.cmake b/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/flags.cmake new file mode 100755 index 000000000..bf4fa0ef5 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/interleave_transfer/armgcc/flags.cmake @@ -0,0 +1,185 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/driver_examples/edma4/interleave_transfer/board.c b/boards/som_mx93/driver_examples/edma4/interleave_transfer/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/interleave_transfer/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/driver_examples/edma4/interleave_transfer/board.h b/boards/som_mx93/driver_examples/edma4/interleave_transfer/board.h new file mode 100644 index 000000000..5108807ef --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/interleave_transfer/board.h @@ -0,0 +1,89 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + +/* ADP5585 */ +#define BOARD_ADP5585_I2C LPI2C2 +#define BOARD_ADP5585_I2C_ADDR (0x34U) +#define BOARD_ADP5585_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_ADP5585_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_ADP5585_I2C_CLOCK_ROOT) + +#define BOARD_ADP5585_PDM_MQS_SEL (2U) +#define BOARD_ADP5585_EXP_SEL (4U) +#define BOARD_ADP5585_CAN_STBY (8U) + +/* PCAL6524 */ +#define BOARD_PCAL6524_I2C LPI2C2 +#define BOARD_PCAL6524_I2C_ADDR (0x22U) +#define BOARD_PCAL6524_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_PCAL6524_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_PCAL6524_I2C_CLOCK_ROOT) + +#define BOARD_PCAL6524_ENET1_NRST (8U + 7U) +#define BOARD_PCAL6524_ENET2_NRST (16U + 0U) +#define BOARD_PCAL6524_MIC_CAN_SEL (16U + 1U) +#define BOARD_PCAL6524_EXP_SEL (16U + 6U) +#define BOARD_PCAL6524_CAN_STBY (16U + 7U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/driver_examples/edma4/interleave_transfer/clock_config.c b/boards/som_mx93/driver_examples/edma4/interleave_transfer/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/interleave_transfer/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/driver_examples/edma4/interleave_transfer/clock_config.h b/boards/som_mx93/driver_examples/edma4/interleave_transfer/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/interleave_transfer/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/driver_examples/edma4/interleave_transfer/edma_interleave_transfer.c b/boards/som_mx93/driver_examples/edma4/interleave_transfer/edma_interleave_transfer.c new file mode 100644 index 000000000..638b58689 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/interleave_transfer/edma_interleave_transfer.c @@ -0,0 +1,109 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_debug_console.h" +#include "fsl_edma.h" + +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define EXAMPLE_DMA_BASEADDR DMA4 +#define EXAMPLE_DMA_CLOCK_ROOT kCLOCK_Root_WakeupAxi +#define DEMO_DMA_CHANNEL_0 0U +#define BUFFER_LENGTH 16U +#define HALF_BUFF_LENGTH (BUFFER_LENGTH / 2) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +AT_NONCACHEABLE_SECTION_INIT(uint32_t srcAddr[HALF_BUFF_LENGTH]) = {0x01U, 0x02U, 0x03U, 0x04U, + 0x05U, 0x06U, 0x07U, 0x08U}; +AT_NONCACHEABLE_SECTION_INIT(uint32_t destAddr[BUFFER_LENGTH]) = {0x00U}; +edma_handle_t g_DMA_Handle; +volatile bool g_Transfer_Done = false; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* User callback function for EDMA transfer. */ +void DMA_Callback(edma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds) +{ + if (transferDone) + { + g_Transfer_Done = true; + } +} + +/*! + * @brief Main function + */ +int main(void) +{ + uint32_t i; + edma_transfer_config_t transferConfig; + edma_config_t userConfig; + + /* clang-format off */ + /* 250MHz DMA clock */ + const clock_root_config_t dmaClkCfg = { + .clockOff = false, + .mux = kCLOCK_WAKEUPAXI_ClockRoot_MuxSysPll1Pfd0, // 1000MHz + .div = 4 + }; + /* clang-format on */ + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + + CLOCK_SetRootClock(EXAMPLE_DMA_CLOCK_ROOT, &dmaClkCfg); + /* Print destination buffer */ + PRINTF("EDMA interleave transfer example begin.\r\n\r\n"); + PRINTF("Destination Buffer:\r\n"); + for (i = 0; i < BUFFER_LENGTH; i++) + { + PRINTF("%d\t", destAddr[i]); + } + + EDMA_GetDefaultConfig(&userConfig); + EDMA_Init(EXAMPLE_DMA_BASEADDR, &userConfig); + + EDMA_CreateHandle(&g_DMA_Handle, EXAMPLE_DMA_BASEADDR, DEMO_DMA_CHANNEL_0); + EDMA_SetCallback(&g_DMA_Handle, DMA_Callback, NULL); + EDMA_PrepareTransfer(&transferConfig, srcAddr, sizeof(srcAddr[0]), destAddr, sizeof(destAddr[0]), + sizeof(uint32_t) * HALF_BUFF_LENGTH, sizeof(srcAddr), kEDMA_MemoryToMemory); + transferConfig.srcOffset = 4U; + transferConfig.destOffset = 8U; + EDMA_SubmitTransfer(&g_DMA_Handle, &transferConfig); + + EDMA_StartTransfer(&g_DMA_Handle); + + /* Wait for EDMA transfer finish */ + while (g_Transfer_Done != true) + { + } + + /* Print destination buffer */ + PRINTF("\r\n\r\nEDMA interleave transfer example finish.\r\n\r\n"); + PRINTF("Destination Buffer:\r\n"); + for (i = 0; i < BUFFER_LENGTH; i++) + { + PRINTF("%d\t", destAddr[i]); + } + while (1) + { + } +} diff --git a/boards/som_mx93/driver_examples/edma4/interleave_transfer/pin_mux.c b/boards/som_mx93/driver_examples/edma4/interleave_transfer/pin_mux.c new file mode 100644 index 000000000..4c8d6a119 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/interleave_transfer/pin_mux.c @@ -0,0 +1,65 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/edma4/interleave_transfer/pin_mux.h b/boards/som_mx93/driver_examples/edma4/interleave_transfer/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/interleave_transfer/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/edma4/interleave_transfer/readme.txt b/boards/som_mx93/driver_examples/edma4/interleave_transfer/readme.txt new file mode 100644 index 000000000..ee45888b8 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/interleave_transfer/readme.txt @@ -0,0 +1,52 @@ +Overview +======== +The EDMA interleave transfer example is a simple demonstration program that uses the SDK software. +It excuates interleave transfer from source buffer to destination buffer using the SDK EDMA drivers. +The purpose of this example is to show how to use the interleave feature of EDMA and to provide a simple example for +debugging and further development. +The example demostrates the interleave transfer by features: + + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Mini/micro USB cable +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Personal Computer + +Board settings +============== +No special settings are required. + +Prepare the Demo +================ +1. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +2. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +3. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +When the example runs successfully, you can see the similar information from the terminal as below. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +EDMA interleave transfer example begin. + +Destination Buffer: + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +EDMA interleave transfer example finish. + +Destination Buffer: + +1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/CMakeLists.txt b/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/CMakeLists.txt new file mode 100644 index 000000000..1dc977e3c --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/CMakeLists.txt @@ -0,0 +1,114 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(edma4_memory_to_memory) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME edma4_memory_to_memory.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../edma_memory_to_memory.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/devices/MIMX9352/utilities/debug_console_lite + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352/drivers/edma4 + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(utility_debug_console_lite_MIMX9352) + +include(utility_assert_lite_MIMX9352) + +include(driver_memory_MIMX9352) + +include(driver_clock_MIMX9352) + +include(driver_edma4_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_lists_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(driver_edma_soc_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/build_all.bat b/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/build_all.bat new file mode 100644 index 000000000..1205ab083 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/build_all.bat @@ -0,0 +1,15 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/build_all.sh b/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/build_all.sh new file mode 100755 index 000000000..8cc56b74f --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/build_debug.bat b/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/build_debug.sh b/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/build_release.bat b/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/build_release.sh b/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/clean.bat b/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/clean.sh b/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/config.cmake b/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/config.cmake new file mode 100755 index 000000000..920520e3d --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/flags.cmake b/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/flags.cmake new file mode 100755 index 000000000..bf4fa0ef5 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory/armgcc/flags.cmake @@ -0,0 +1,185 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory/board.c b/boards/som_mx93/driver_examples/edma4/memory_to_memory/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory/board.h b/boards/som_mx93/driver_examples/edma4/memory_to_memory/board.h new file mode 100644 index 000000000..5108807ef --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory/board.h @@ -0,0 +1,89 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + +/* ADP5585 */ +#define BOARD_ADP5585_I2C LPI2C2 +#define BOARD_ADP5585_I2C_ADDR (0x34U) +#define BOARD_ADP5585_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_ADP5585_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_ADP5585_I2C_CLOCK_ROOT) + +#define BOARD_ADP5585_PDM_MQS_SEL (2U) +#define BOARD_ADP5585_EXP_SEL (4U) +#define BOARD_ADP5585_CAN_STBY (8U) + +/* PCAL6524 */ +#define BOARD_PCAL6524_I2C LPI2C2 +#define BOARD_PCAL6524_I2C_ADDR (0x22U) +#define BOARD_PCAL6524_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_PCAL6524_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_PCAL6524_I2C_CLOCK_ROOT) + +#define BOARD_PCAL6524_ENET1_NRST (8U + 7U) +#define BOARD_PCAL6524_ENET2_NRST (16U + 0U) +#define BOARD_PCAL6524_MIC_CAN_SEL (16U + 1U) +#define BOARD_PCAL6524_EXP_SEL (16U + 6U) +#define BOARD_PCAL6524_CAN_STBY (16U + 7U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory/clock_config.c b/boards/som_mx93/driver_examples/edma4/memory_to_memory/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory/clock_config.h b/boards/som_mx93/driver_examples/edma4/memory_to_memory/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory/edma_memory_to_memory.c b/boards/som_mx93/driver_examples/edma4/memory_to_memory/edma_memory_to_memory.c new file mode 100644 index 000000000..7e74f992b --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory/edma_memory_to_memory.c @@ -0,0 +1,104 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_debug_console.h" +#include "fsl_edma.h" + +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define EXAMPLE_DMA_BASEADDR DMA4 +#define EXAMPLE_DMA_CLOCK_ROOT kCLOCK_Root_WakeupAxi +#define DEMO_DMA_CHANNEL_0 0U +#define APP_DMA_IRQ DMA4_0_1_IRQn +#define APP_DMA_IRQ_HANDLER DMA4_0_1_IRQHandler +#define BUFFER_LENGTH 4U + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +AT_NONCACHEABLE_SECTION_INIT(uint32_t srcAddr[BUFFER_LENGTH]) = {0x01, 0x02, 0x03, 0x04}; +AT_NONCACHEABLE_SECTION_INIT(uint32_t destAddr[BUFFER_LENGTH]) = {0x00, 0x00, 0x00, 0x00}; +volatile bool g_Transfer_Done = false; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* EDMA transfer channel 0 IRQ handler */ +void APP_DMA_IRQ_HANDLER(void) +{ + if ((EDMA_GetChannelStatusFlags(EXAMPLE_DMA_BASEADDR, DEMO_DMA_CHANNEL_0) & kEDMA_InterruptFlag) != 0U) + { + EDMA_ClearChannelStatusFlags(EXAMPLE_DMA_BASEADDR, DEMO_DMA_CHANNEL_0, kEDMA_InterruptFlag); + g_Transfer_Done = true; + } +} + +/*! + * @brief Main function + */ +int main(void) +{ + uint32_t i; + edma_transfer_config_t transferConfig; + edma_config_t userConfig; + + /* clang-format off */ + /* 250MHz DMA clock */ + const clock_root_config_t dmaClkCfg = { + .clockOff = false, + .mux = kCLOCK_WAKEUPAXI_ClockRoot_MuxSysPll1Pfd0, // 1000MHz + .div = 4 + }; + /* clang-format on */ + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + + CLOCK_SetRootClock(EXAMPLE_DMA_CLOCK_ROOT, &dmaClkCfg); + /* Print destination buffer */ + PRINTF("EDMA memory to memory example begin.\r\n\r\n"); + PRINTF("Destination Buffer:\r\n"); + for (i = 0; i < BUFFER_LENGTH; i++) + { + PRINTF("%d\t", destAddr[i]); + } + + /* Configure EDMA channel for one shot transfer */ + EDMA_GetDefaultConfig(&userConfig); + EDMA_Init(EXAMPLE_DMA_BASEADDR, &userConfig); + EDMA_PrepareTransfer(&transferConfig, srcAddr, sizeof(srcAddr[0]), destAddr, sizeof(destAddr[0]), sizeof(destAddr), + sizeof(destAddr), kEDMA_MemoryToMemory); + EDMA_SetTransferConfig(EXAMPLE_DMA_BASEADDR, DEMO_DMA_CHANNEL_0, &transferConfig, NULL); + EnableIRQ(APP_DMA_IRQ); + EDMA_TriggerChannelStart(EXAMPLE_DMA_BASEADDR, DEMO_DMA_CHANNEL_0); + + /* Wait for EDMA transfer finish */ + while (g_Transfer_Done != true) + { + } + /* Print destination buffer */ + PRINTF("\r\n\r\nEDMA memory to memory example finish.\r\n\r\n"); + PRINTF("Destination Buffer:\r\n"); + for (i = 0; i < BUFFER_LENGTH; i++) + { + PRINTF("%d\t", destAddr[i]); + } + while (1) + { + } +} diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory/pin_mux.c b/boards/som_mx93/driver_examples/edma4/memory_to_memory/pin_mux.c new file mode 100644 index 000000000..4c8d6a119 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory/pin_mux.c @@ -0,0 +1,65 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory/pin_mux.h b/boards/som_mx93/driver_examples/edma4/memory_to_memory/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory/readme.txt b/boards/som_mx93/driver_examples/edma4/memory_to_memory/readme.txt new file mode 100644 index 000000000..321ff5bfa --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory/readme.txt @@ -0,0 +1,48 @@ +Overview +======== +The EDMA memory to memory example is a simple demonstration program that uses the SDK software. +It executes one shot transfer from source buffer to destination buffer using the SDK EDMA drivers. +The purpose of this example is to show how to use the EDMA and to provide a simple example for +debugging and further development. + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Mini/micro USB cable +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Personal Computer + +Board settings +============== +No special settings are required. + +Prepare the Demo +================ +1. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +2. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +3. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +When the example runs successfully, you can see the similar information from the terminal as below. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +EDMA memory to memory example begin. + +Destination Buffer: +0 0 0 0 + +EDMA memory to memory example finish. + +Destination Buffer: +1 2 3 4 +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/CMakeLists.txt b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/CMakeLists.txt new file mode 100644 index 000000000..29a0a3c9d --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/CMakeLists.txt @@ -0,0 +1,114 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(edma4_memory_to_memory_transfer) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME edma4_memory_to_memory_transfer.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../edma_memory_to_memory_transfer.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/devices/MIMX9352/utilities/debug_console_lite + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352/drivers/edma4 + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(utility_debug_console_lite_MIMX9352) + +include(utility_assert_lite_MIMX9352) + +include(driver_memory_MIMX9352) + +include(driver_clock_MIMX9352) + +include(driver_edma4_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_lists_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(driver_edma_soc_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/build_all.bat b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/build_all.bat new file mode 100644 index 000000000..1205ab083 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/build_all.bat @@ -0,0 +1,15 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/build_all.sh b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/build_all.sh new file mode 100755 index 000000000..8cc56b74f --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/build_debug.bat b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/build_debug.sh b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/build_release.bat b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/build_release.sh b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/clean.bat b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/clean.sh b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/config.cmake b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/config.cmake new file mode 100755 index 000000000..920520e3d --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/flags.cmake b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/flags.cmake new file mode 100755 index 000000000..bf4fa0ef5 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/armgcc/flags.cmake @@ -0,0 +1,185 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/board.c b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/board.h b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/board.h new file mode 100644 index 000000000..5108807ef --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/board.h @@ -0,0 +1,89 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + +/* ADP5585 */ +#define BOARD_ADP5585_I2C LPI2C2 +#define BOARD_ADP5585_I2C_ADDR (0x34U) +#define BOARD_ADP5585_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_ADP5585_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_ADP5585_I2C_CLOCK_ROOT) + +#define BOARD_ADP5585_PDM_MQS_SEL (2U) +#define BOARD_ADP5585_EXP_SEL (4U) +#define BOARD_ADP5585_CAN_STBY (8U) + +/* PCAL6524 */ +#define BOARD_PCAL6524_I2C LPI2C2 +#define BOARD_PCAL6524_I2C_ADDR (0x22U) +#define BOARD_PCAL6524_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_PCAL6524_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_PCAL6524_I2C_CLOCK_ROOT) + +#define BOARD_PCAL6524_ENET1_NRST (8U + 7U) +#define BOARD_PCAL6524_ENET2_NRST (16U + 0U) +#define BOARD_PCAL6524_MIC_CAN_SEL (16U + 1U) +#define BOARD_PCAL6524_EXP_SEL (16U + 6U) +#define BOARD_PCAL6524_CAN_STBY (16U + 7U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/clock_config.c b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/clock_config.h b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/edma_memory_to_memory_transfer.c b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/edma_memory_to_memory_transfer.c new file mode 100644 index 000000000..aa3d7d863 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/edma_memory_to_memory_transfer.c @@ -0,0 +1,104 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_debug_console.h" +#include "fsl_edma.h" + +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define EXAMPLE_DMA_BASEADDR DMA4 +#define EXAMPLE_DMA_CLOCK_ROOT kCLOCK_Root_WakeupAxi +#define DEMO_DMA_CHANNEL_0 0U +#define BUFFER_LENGTH 4U + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +AT_NONCACHEABLE_SECTION_INIT(uint32_t srcAddr[BUFFER_LENGTH]) = {0x01, 0x02, 0x03, 0x04}; +AT_NONCACHEABLE_SECTION_INIT(uint32_t destAddr[BUFFER_LENGTH]) = {0x00, 0x00, 0x00, 0x00}; +edma_handle_t g_DMA_Handle; +volatile bool g_Transfer_Done = false; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* User callback function for EDMA transfer. */ +void DMA_Callback(edma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds) +{ + if (transferDone) + { + g_Transfer_Done = true; + } +} + +/*! + * @brief Main function + */ +int main(void) +{ + uint32_t i; + edma_transfer_config_t transferConfig; + edma_config_t userConfig; + + /* clang-format off */ + /* 250MHz DMA clock */ + const clock_root_config_t dmaClkCfg = { + .clockOff = false, + .mux = kCLOCK_WAKEUPAXI_ClockRoot_MuxSysPll1Pfd0, // 1000MHz + .div = 4 + }; + /* clang-format on */ + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + + CLOCK_SetRootClock(EXAMPLE_DMA_CLOCK_ROOT, &dmaClkCfg); + /* Print destination buffer */ + PRINTF("EDMA memory to memory transfer example begin.\r\n\r\n"); + PRINTF("Destination Buffer:\r\n"); + for (i = 0; i < BUFFER_LENGTH; i++) + { + PRINTF("%d\t", destAddr[i]); + } + + /* Configure EDMA channel for one shot transfer */ + EDMA_GetDefaultConfig(&userConfig); + EDMA_Init(EXAMPLE_DMA_BASEADDR, &userConfig); + + EDMA_CreateHandle(&g_DMA_Handle, EXAMPLE_DMA_BASEADDR, DEMO_DMA_CHANNEL_0); + EDMA_SetCallback(&g_DMA_Handle, DMA_Callback, NULL); + EDMA_PrepareTransfer(&transferConfig, srcAddr, sizeof(srcAddr[0]), destAddr, sizeof(destAddr[0]), + sizeof(uint32_t) * BUFFER_LENGTH, sizeof(destAddr), kEDMA_MemoryToMemory); + EDMA_SubmitTransfer(&g_DMA_Handle, &transferConfig); + EDMA_StartTransfer(&g_DMA_Handle); + + /* Wait for EDMA transfer finish */ + while (g_Transfer_Done != true) + { + } + /* Print destination buffer */ + PRINTF("\r\n\r\nEDMA memory to memory transfer example finish.\r\n\r\n"); + PRINTF("Destination Buffer:\r\n"); + for (i = 0; i < BUFFER_LENGTH; i++) + { + PRINTF("%d\t", destAddr[i]); + } + while (1) + { + } +} diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/pin_mux.c b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/pin_mux.c new file mode 100644 index 000000000..4c8d6a119 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/pin_mux.c @@ -0,0 +1,65 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/pin_mux.h b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/readme.txt b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/readme.txt new file mode 100644 index 000000000..9eb02a5de --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memory_to_memory_transfer/readme.txt @@ -0,0 +1,48 @@ +Overview +======== +The EDMA memory to memory transfer example is a simple demonstration program that uses the SDK software. +It executes one shot transfer from source buffer to destination buffer using the SDK EDMA drivers. +The purpose of this example is to show how to use the EDMA and to provide a simple example for +debugging and further development. + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Mini/micro USB cable +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Personal Computer + +Board settings +============== +No special settings are required. + +Prepare the Demo +================ +1. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +2. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +3. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +When the example runs successfully, you can see the similar information from the terminal as below. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +EDMA memory to memory transfer example begin. + +Destination Buffer: +0 0 0 0 + +EDMA memory to memory transfer example finish. + +Destination Buffer: +1 2 3 4 +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + diff --git a/boards/som_mx93/driver_examples/edma4/memset/armgcc/CMakeLists.txt b/boards/som_mx93/driver_examples/edma4/memset/armgcc/CMakeLists.txt new file mode 100644 index 000000000..c5ba4fc1e --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memset/armgcc/CMakeLists.txt @@ -0,0 +1,114 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(edma4_memset) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME edma4_memset.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../edma_memset.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/devices/MIMX9352/utilities/debug_console_lite + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352/drivers/edma4 + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(utility_debug_console_lite_MIMX9352) + +include(utility_assert_lite_MIMX9352) + +include(driver_memory_MIMX9352) + +include(driver_clock_MIMX9352) + +include(driver_edma4_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_lists_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(driver_edma_soc_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/driver_examples/edma4/memset/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/driver_examples/edma4/memset/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memset/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/driver_examples/edma4/memset/armgcc/build_all.bat b/boards/som_mx93/driver_examples/edma4/memset/armgcc/build_all.bat new file mode 100644 index 000000000..1205ab083 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memset/armgcc/build_all.bat @@ -0,0 +1,15 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/som_mx93/driver_examples/edma4/memset/armgcc/build_all.sh b/boards/som_mx93/driver_examples/edma4/memset/armgcc/build_all.sh new file mode 100755 index 000000000..8cc56b74f --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memset/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/driver_examples/edma4/memset/armgcc/build_debug.bat b/boards/som_mx93/driver_examples/edma4/memset/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memset/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/memset/armgcc/build_debug.sh b/boards/som_mx93/driver_examples/edma4/memset/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memset/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/memset/armgcc/build_release.bat b/boards/som_mx93/driver_examples/edma4/memset/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memset/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/memset/armgcc/build_release.sh b/boards/som_mx93/driver_examples/edma4/memset/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memset/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/memset/armgcc/clean.bat b/boards/som_mx93/driver_examples/edma4/memset/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memset/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/driver_examples/edma4/memset/armgcc/clean.sh b/boards/som_mx93/driver_examples/edma4/memset/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memset/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/driver_examples/edma4/memset/armgcc/config.cmake b/boards/som_mx93/driver_examples/edma4/memset/armgcc/config.cmake new file mode 100755 index 000000000..920520e3d --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memset/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/driver_examples/edma4/memset/armgcc/flags.cmake b/boards/som_mx93/driver_examples/edma4/memset/armgcc/flags.cmake new file mode 100755 index 000000000..bf4fa0ef5 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memset/armgcc/flags.cmake @@ -0,0 +1,185 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/driver_examples/edma4/memset/board.c b/boards/som_mx93/driver_examples/edma4/memset/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memset/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/driver_examples/edma4/memset/board.h b/boards/som_mx93/driver_examples/edma4/memset/board.h new file mode 100644 index 000000000..5108807ef --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memset/board.h @@ -0,0 +1,89 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + +/* ADP5585 */ +#define BOARD_ADP5585_I2C LPI2C2 +#define BOARD_ADP5585_I2C_ADDR (0x34U) +#define BOARD_ADP5585_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_ADP5585_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_ADP5585_I2C_CLOCK_ROOT) + +#define BOARD_ADP5585_PDM_MQS_SEL (2U) +#define BOARD_ADP5585_EXP_SEL (4U) +#define BOARD_ADP5585_CAN_STBY (8U) + +/* PCAL6524 */ +#define BOARD_PCAL6524_I2C LPI2C2 +#define BOARD_PCAL6524_I2C_ADDR (0x22U) +#define BOARD_PCAL6524_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_PCAL6524_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_PCAL6524_I2C_CLOCK_ROOT) + +#define BOARD_PCAL6524_ENET1_NRST (8U + 7U) +#define BOARD_PCAL6524_ENET2_NRST (16U + 0U) +#define BOARD_PCAL6524_MIC_CAN_SEL (16U + 1U) +#define BOARD_PCAL6524_EXP_SEL (16U + 6U) +#define BOARD_PCAL6524_CAN_STBY (16U + 7U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/driver_examples/edma4/memset/clock_config.c b/boards/som_mx93/driver_examples/edma4/memset/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memset/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/driver_examples/edma4/memset/clock_config.h b/boards/som_mx93/driver_examples/edma4/memset/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memset/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/driver_examples/edma4/memset/edma_memset.c b/boards/som_mx93/driver_examples/edma4/memset/edma_memset.c new file mode 100644 index 000000000..45a91147f --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memset/edma_memset.c @@ -0,0 +1,110 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_debug_console.h" +#include "fsl_edma.h" + +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define EXAMPLE_DMA_BASEADDR DMA4 +#define EXAMPLE_DMA_CLOCK_ROOT kCLOCK_Root_WakeupAxi +#define DEMO_DMA_CHANNEL_0 0U +#define APP_DMA_IRQ DMA4_0_1_IRQn +#define APP_DMA_IRQ_HANDLER DMA4_0_1_IRQHandler +#define BUFFER_LENGTH 4U + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +AT_NONCACHEABLE_SECTION_INIT(uint32_t srcAddr[BUFFER_LENGTH]) = {0x01, 0x02, 0x03, 0x04}; +AT_NONCACHEABLE_SECTION_INIT(uint32_t destAddr[BUFFER_LENGTH]) = {0x00, 0x00, 0x00, 0x00}; +volatile bool g_Transfer_Done = false; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* EDMA transfer channel 0 IRQ handler */ +void APP_DMA_IRQ_HANDLER(void) +{ + if ((EDMA_GetChannelStatusFlags(EXAMPLE_DMA_BASEADDR, DEMO_DMA_CHANNEL_0) & kEDMA_InterruptFlag) != 0U) + { + EDMA_ClearChannelStatusFlags(EXAMPLE_DMA_BASEADDR, DEMO_DMA_CHANNEL_0, kEDMA_InterruptFlag); + g_Transfer_Done = true; + } +} + +/*! + * @brief Main function + */ +int main(void) +{ + uint32_t i; + edma_transfer_config_t transferConfig; + edma_config_t userConfig; + + /* clang-format off */ + /* 250MHz DMA clock */ + const clock_root_config_t dmaClkCfg = { + .clockOff = false, + .mux = kCLOCK_WAKEUPAXI_ClockRoot_MuxSysPll1Pfd0, // 1000MHz + .div = 4 + }; + /* clang-format on */ + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + + CLOCK_SetRootClock(EXAMPLE_DMA_CLOCK_ROOT, &dmaClkCfg); + /* Print destination buffer */ + PRINTF("EDMA memset begin.\r\n\r\n"); + PRINTF("Source Buffer:\r\n"); + for (i = 0; i < BUFFER_LENGTH; i++) + { + PRINTF("%d\t", srcAddr[i]); + } + PRINTF("\r\n\r\nDestination Buffer:\r\n"); + for (i = 0; i < BUFFER_LENGTH; i++) + { + PRINTF("%d\t", destAddr[i]); + } + + /* Configure EDMA channel for one shot transfer */ + EDMA_GetDefaultConfig(&userConfig); + EDMA_Init(EXAMPLE_DMA_BASEADDR, &userConfig); + EDMA_PrepareTransferConfig(&transferConfig, srcAddr, sizeof(srcAddr[0]), 0U, destAddr, sizeof(destAddr[0]), + sizeof(destAddr[0]), sizeof(destAddr), sizeof(destAddr)); + EDMA_SetTransferConfig(EXAMPLE_DMA_BASEADDR, DEMO_DMA_CHANNEL_0, &transferConfig, NULL); + EnableIRQ(APP_DMA_IRQ); + + EDMA_TriggerChannelStart(EXAMPLE_DMA_BASEADDR, DEMO_DMA_CHANNEL_0); + + /* Wait for EDMA transfer finish */ + while (g_Transfer_Done != true) + { + } + /* Print destination buffer */ + PRINTF("\r\n\r\nEDMA memset finish.\r\n\r\n"); + PRINTF("Destination Buffer:\r\n"); + for (i = 0; i < BUFFER_LENGTH; i++) + { + PRINTF("%d\t", destAddr[i]); + } + while (1) + { + } +} diff --git a/boards/som_mx93/driver_examples/edma4/memset/pin_mux.c b/boards/som_mx93/driver_examples/edma4/memset/pin_mux.c new file mode 100644 index 000000000..4c8d6a119 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memset/pin_mux.c @@ -0,0 +1,65 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/edma4/memset/pin_mux.h b/boards/som_mx93/driver_examples/edma4/memset/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memset/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/edma4/memset/readme.txt b/boards/som_mx93/driver_examples/edma4/memset/readme.txt new file mode 100644 index 000000000..f02ce3d23 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/memset/readme.txt @@ -0,0 +1,54 @@ +Overview +======== +The EDMA memset example is a simple demonstration program that uses the SDK software. +It executes one shot transfer from source buffer to destination buffer using the SDK EDMA drivers. +The purpose of this example is to show how to use the EDMA and to provide a simple example for +debugging and further development. + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Mini/micro USB cable +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Personal Computer + +Board settings +============== +No special settings are required. + +Prepare the Demo +================ +1. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +2. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +3. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +When the example runs successfully, you can see the similar information from the terminal as below. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +EDMA memset begin. + +Source Buffer: + +1 2 3 4 + +Destination Buffer: + +0 0 0 0 + +EDMA memset finish. + +Destination Buffer: + +1 1 1 1 +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + diff --git a/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/CMakeLists.txt b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/CMakeLists.txt new file mode 100644 index 000000000..3281304ee --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/CMakeLists.txt @@ -0,0 +1,114 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(edma4_ping_pong_transfer) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME edma4_ping_pong_transfer.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../edma_ping_pong_transfer.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/devices/MIMX9352/utilities/debug_console_lite + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352/drivers/edma4 + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(utility_debug_console_lite_MIMX9352) + +include(utility_assert_lite_MIMX9352) + +include(driver_memory_MIMX9352) + +include(driver_clock_MIMX9352) + +include(driver_edma4_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_lists_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(driver_edma_soc_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/build_all.bat b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/build_all.bat new file mode 100644 index 000000000..1205ab083 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/build_all.bat @@ -0,0 +1,15 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/build_all.sh b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/build_all.sh new file mode 100755 index 000000000..8cc56b74f --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/build_debug.bat b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/build_debug.sh b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/build_release.bat b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/build_release.sh b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/clean.bat b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/clean.sh b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/config.cmake b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/config.cmake new file mode 100755 index 000000000..920520e3d --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/flags.cmake b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/flags.cmake new file mode 100755 index 000000000..bf4fa0ef5 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/armgcc/flags.cmake @@ -0,0 +1,185 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/board.c b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/board.h b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/board.h new file mode 100644 index 000000000..5108807ef --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/board.h @@ -0,0 +1,89 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + +/* ADP5585 */ +#define BOARD_ADP5585_I2C LPI2C2 +#define BOARD_ADP5585_I2C_ADDR (0x34U) +#define BOARD_ADP5585_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_ADP5585_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_ADP5585_I2C_CLOCK_ROOT) + +#define BOARD_ADP5585_PDM_MQS_SEL (2U) +#define BOARD_ADP5585_EXP_SEL (4U) +#define BOARD_ADP5585_CAN_STBY (8U) + +/* PCAL6524 */ +#define BOARD_PCAL6524_I2C LPI2C2 +#define BOARD_PCAL6524_I2C_ADDR (0x22U) +#define BOARD_PCAL6524_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_PCAL6524_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_PCAL6524_I2C_CLOCK_ROOT) + +#define BOARD_PCAL6524_ENET1_NRST (8U + 7U) +#define BOARD_PCAL6524_ENET2_NRST (16U + 0U) +#define BOARD_PCAL6524_MIC_CAN_SEL (16U + 1U) +#define BOARD_PCAL6524_EXP_SEL (16U + 6U) +#define BOARD_PCAL6524_CAN_STBY (16U + 7U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/clock_config.c b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/clock_config.h b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/edma_ping_pong_transfer.c b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/edma_ping_pong_transfer.c new file mode 100644 index 000000000..2bf9d914d --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/edma_ping_pong_transfer.c @@ -0,0 +1,124 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_debug_console.h" +#include "fsl_edma.h" + +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define EXAMPLE_DMA_BASEADDR DMA4 +#define EXAMPLE_DMA_CLOCK_ROOT kCLOCK_Root_WakeupAxi +#define DEMO_DMA_CHANNEL_0 0U +#define BUFFER_LENGTH 8U +#define HALF_BUFFER_LENGTH (BUFFER_LENGTH / 2U) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +edma_handle_t g_DMA_Handle; +volatile bool g_transferDone = false; + +AT_NONCACHEABLE_SECTION_INIT(uint32_t srcAddr[BUFFER_LENGTH]) = {0x01U, 0x02U, 0x03U, 0x04U, + 0x05U, 0x06U, 0x07U, 0x08U}; +AT_NONCACHEABLE_SECTION_INIT(uint32_t destAddr[BUFFER_LENGTH]) = {0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U}; +AT_NONCACHEABLE_SECTION_ALIGN(edma_tcd_t g_DMA_Tcd[2], sizeof(edma_tcd_t)); + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* User callback function for EDMA transfer. */ +void DMA_Callback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) +{ + if (transferDone) + { + g_transferDone = true; + } +} + +/*! + * @brief Main function + */ +int main(void) +{ + uint32_t i = 0; + edma_transfer_config_t transferConfig[2]; + edma_config_t userConfig; + + /* clang-format off */ + /* 250MHz DMA clock */ + const clock_root_config_t dmaClkCfg = { + .clockOff = false, + .mux = kCLOCK_WAKEUPAXI_ClockRoot_MuxSysPll1Pfd0, // 1000MHz + .div = 4 + }; + /* clang-format on */ + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + + CLOCK_SetRootClock(EXAMPLE_DMA_CLOCK_ROOT, &dmaClkCfg); + + PRINTF("EDMA ping pong transfer example begin.\r\n\r\n"); + PRINTF("Destination Buffer:\r\n"); + for (i = 0; i < BUFFER_LENGTH; i++) + { + PRINTF("%d\t", destAddr[i]); + } + + EDMA_GetDefaultConfig(&userConfig); + EDMA_Init(EXAMPLE_DMA_BASEADDR, &userConfig); + + EDMA_CreateHandle(&g_DMA_Handle, EXAMPLE_DMA_BASEADDR, DEMO_DMA_CHANNEL_0); + EDMA_SetCallback(&g_DMA_Handle, DMA_Callback, NULL); + EDMA_InstallTCDMemory(&g_DMA_Handle, g_DMA_Tcd, 2); + EDMA_PrepareTransfer(&transferConfig[0], &srcAddr[0], sizeof(srcAddr[0]), &destAddr[0], sizeof(destAddr[0]), + sizeof(uint32_t) * HALF_BUFFER_LENGTH, sizeof(uint32_t) * HALF_BUFFER_LENGTH, + kEDMA_MemoryToMemory); + EDMA_PrepareTransfer(&transferConfig[1], &srcAddr[4], sizeof(srcAddr[0]), &destAddr[4], sizeof(destAddr[0]), + sizeof(uint32_t) * HALF_BUFFER_LENGTH, sizeof(uint32_t) * HALF_BUFFER_LENGTH, + kEDMA_MemoryToMemory); + EDMA_SubmitLoopTransfer(&g_DMA_Handle, transferConfig, 2); + EDMA_StartTransfer(&g_DMA_Handle); + + /* Wait for EDMA transfer finish */ + while (!g_transferDone) + { + } + + g_transferDone = false; + + EDMA_StartTransfer(&g_DMA_Handle); + + /* Wait for EDMA transfer finish */ + while (!g_transferDone) + { + } + + /* Print destination buffer */ + PRINTF("\r\n\r\nEDMA ping pong transfer example finish.\r\n\r\n"); + PRINTF("Destination Buffer:\r\n"); + for (i = 0; i < BUFFER_LENGTH; i++) + { + PRINTF("%d\t", destAddr[i]); + } + /* Free the memory space allocated */ + while (1) + { + } +} diff --git a/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/pin_mux.c b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/pin_mux.c new file mode 100644 index 000000000..4c8d6a119 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/pin_mux.c @@ -0,0 +1,65 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/pin_mux.h b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/readme.txt b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/readme.txt new file mode 100644 index 000000000..4bfe36114 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/ping_pong_transfer/readme.txt @@ -0,0 +1,53 @@ +Overview +======== +The EDMA ping pong transfer example is a simple demonstration program that uses the SDK software. +It excuates ping pong transfer from source buffer to destination buffer using the SDK EDMA drivers. +The purpose of this example is to show how to use ping pong buffer by the EDMA and to provide a simple example for +debugging and further development. +The example demostrate the ping pong transfer by the EDMA scatter gather feature. +Please reference user manual for the detail of the feature. + + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Mini/micro USB cable +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Personal Computer + +Board settings +============== +No special settings are required. + +Prepare the Demo +================ +1. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +2. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +3. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +When the example runs successfully, you can see the similar information from the terminal as below. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +EDMA ping pong transfer example begin. + +Destination Buffer: + +0 0 0 0 0 0 0 0 + +EDMA ping pong transfer example finish. + +Destination Buffer: + +1 2 3 4 5 6 7 8 +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + diff --git a/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/CMakeLists.txt b/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/CMakeLists.txt new file mode 100644 index 000000000..cd7e2eb8b --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/CMakeLists.txt @@ -0,0 +1,114 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(edma4_scatter_gather) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME edma4_scatter_gather.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../edma_scatter_gather.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/devices/MIMX9352/utilities/debug_console_lite + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352/drivers/edma4 + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(utility_debug_console_lite_MIMX9352) + +include(utility_assert_lite_MIMX9352) + +include(driver_memory_MIMX9352) + +include(driver_clock_MIMX9352) + +include(driver_edma4_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_lists_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(driver_edma_soc_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/build_all.bat b/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/build_all.bat new file mode 100644 index 000000000..1205ab083 --- /dev/null +++ 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b/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/build_all.sh new file mode 100755 index 000000000..8cc56b74f --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/build_debug.bat b/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/build_debug.sh b/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/build_release.bat b/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/build_release.sh b/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/clean.bat b/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/clean.sh b/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/config.cmake b/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/config.cmake new file mode 100755 index 000000000..920520e3d --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/flags.cmake b/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/flags.cmake new file mode 100755 index 000000000..bf4fa0ef5 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/scatter_gather/armgcc/flags.cmake @@ -0,0 +1,185 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/driver_examples/edma4/scatter_gather/board.c b/boards/som_mx93/driver_examples/edma4/scatter_gather/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/scatter_gather/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/driver_examples/edma4/scatter_gather/board.h b/boards/som_mx93/driver_examples/edma4/scatter_gather/board.h new file mode 100644 index 000000000..5108807ef --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/scatter_gather/board.h @@ -0,0 +1,89 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + +/* ADP5585 */ +#define BOARD_ADP5585_I2C LPI2C2 +#define BOARD_ADP5585_I2C_ADDR (0x34U) +#define BOARD_ADP5585_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_ADP5585_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_ADP5585_I2C_CLOCK_ROOT) + +#define BOARD_ADP5585_PDM_MQS_SEL (2U) +#define BOARD_ADP5585_EXP_SEL (4U) +#define BOARD_ADP5585_CAN_STBY (8U) + +/* PCAL6524 */ +#define BOARD_PCAL6524_I2C LPI2C2 +#define BOARD_PCAL6524_I2C_ADDR (0x22U) +#define BOARD_PCAL6524_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_PCAL6524_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_PCAL6524_I2C_CLOCK_ROOT) + +#define BOARD_PCAL6524_ENET1_NRST (8U + 7U) +#define BOARD_PCAL6524_ENET2_NRST (16U + 0U) +#define BOARD_PCAL6524_MIC_CAN_SEL (16U + 1U) +#define BOARD_PCAL6524_EXP_SEL (16U + 6U) +#define BOARD_PCAL6524_CAN_STBY (16U + 7U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/driver_examples/edma4/scatter_gather/clock_config.c b/boards/som_mx93/driver_examples/edma4/scatter_gather/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/scatter_gather/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/driver_examples/edma4/scatter_gather/clock_config.h b/boards/som_mx93/driver_examples/edma4/scatter_gather/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/scatter_gather/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/driver_examples/edma4/scatter_gather/edma_scatter_gather.c b/boards/som_mx93/driver_examples/edma4/scatter_gather/edma_scatter_gather.c new file mode 100644 index 000000000..606d1bd31 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/scatter_gather/edma_scatter_gather.c @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_debug_console.h" +#include "fsl_edma.h" +#include + +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define EXAMPLE_DMA_BASEADDR DMA4 +#define EXAMPLE_DMA_CLOCK_ROOT kCLOCK_Root_WakeupAxi +#define EXAMPLE_DMA_CHANNEL 0U +#define BUFF_LENGTH 8U +#define HALF_BUFF_LENGTH (BUFF_LENGTH / 2U) +#define TCD_QUEUE_SIZE 2U + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +edma_handle_t g_EDMA_Handle; +volatile bool g_Transfer_Done = false; + +AT_NONCACHEABLE_SECTION_INIT(uint32_t srcAddr[BUFF_LENGTH]) = {0x01U, 0x02U, 0x03U, 0x04U, 0x05U, 0x06U, 0x07U, 0x08U}; +AT_NONCACHEABLE_SECTION_INIT(uint32_t destAddr[BUFF_LENGTH]) = {0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U}; +/* Allocate TCD memory poll */ +AT_QUICKACCESS_SECTION_DATA_ALIGN(edma_tcd_t tcdMemoryPoolPtr[TCD_QUEUE_SIZE], sizeof(edma_tcd_t)); + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* User callback function for EDMA transfer. */ +void EDMA_Callback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) +{ + if (transferDone) + { + g_Transfer_Done = true; + } +} + +/*! + * @brief Main function + */ +int main(void) +{ + uint32_t i = 0; + edma_transfer_config_t transferConfig; + edma_config_t userConfig; + + /* clang-format off */ + /* 250MHz DMA clock */ + const clock_root_config_t dmaClkCfg = { + .clockOff = false, + .mux = kCLOCK_WAKEUPAXI_ClockRoot_MuxSysPll1Pfd0, // 1000MHz + .div = 4 + }; + /* clang-format on */ + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + + CLOCK_SetRootClock(EXAMPLE_DMA_CLOCK_ROOT, &dmaClkCfg); + /* Print source buffer */ + PRINTF("\r\nEDMA scatter gather transfer example begin.\r\n\r\n"); + PRINTF("\r\nDestination Buffer:\r\n"); + for (i = 0; i < BUFF_LENGTH; i++) + { + PRINTF("%d\t", destAddr[i]); + } + /* Configure EDMA one shot transfer */ + /* + * userConfig.enableMasterIdReplication = true; + * userConfig.enableHaltOnError = true; + * userConfig.enableRoundRobinArbitration = false; + * userConfig.enableDebugMode = false; + * userConfig.enableBufferedWrites = false; + */ + EDMA_GetDefaultConfig(&userConfig); + EDMA_Init(EXAMPLE_DMA_BASEADDR, &userConfig); + EDMA_CreateHandle(&g_EDMA_Handle, EXAMPLE_DMA_BASEADDR, EXAMPLE_DMA_CHANNEL); + EDMA_SetCallback(&g_EDMA_Handle, EDMA_Callback, NULL); + EDMA_ResetChannel(g_EDMA_Handle.base, g_EDMA_Handle.channel); + + EDMA_InstallTCDMemory(&g_EDMA_Handle, tcdMemoryPoolPtr, TCD_QUEUE_SIZE); + /* Configure and submit transfer structure 1 */ + EDMA_PrepareTransfer(&transferConfig, srcAddr, sizeof(srcAddr[0]), destAddr, sizeof(destAddr[0]), + sizeof(srcAddr[0]) * HALF_BUFF_LENGTH, sizeof(srcAddr[0]) * HALF_BUFF_LENGTH, + kEDMA_MemoryToMemory); + EDMA_SubmitTransfer(&g_EDMA_Handle, &transferConfig); + /* Configure and submit transfer structure 2 */ + EDMA_PrepareTransfer(&transferConfig, &srcAddr[4], sizeof(srcAddr[0]), &destAddr[4], sizeof(destAddr[0]), + sizeof(srcAddr[0]) * HALF_BUFF_LENGTH, sizeof(srcAddr[0]) * HALF_BUFF_LENGTH, + kEDMA_MemoryToMemory); + EDMA_SubmitTransfer(&g_EDMA_Handle, &transferConfig); + /* Trigger transfer start */ + EDMA_StartTransfer(&g_EDMA_Handle); + /* Wait for the first TCD finished */ + while (g_Transfer_Done != true) + { + } + g_Transfer_Done = false; + /* Trigger the second tcd */ + EDMA_StartTransfer(&g_EDMA_Handle); + /* Wait for the second TCD finished */ + while (g_Transfer_Done != true) + { + } + + /* Print destination buffer */ + PRINTF("\r\n\r\nEDMA scatter gather transfer example finish.\r\n\r\n"); + PRINTF("Destination Buffer:\r\n"); + for (i = 0; i < BUFF_LENGTH; i++) + { + PRINTF("%d\t", destAddr[i]); + } + /* Free the memory space allocated */ + while (1) + { + } +} diff --git a/boards/som_mx93/driver_examples/edma4/scatter_gather/pin_mux.c b/boards/som_mx93/driver_examples/edma4/scatter_gather/pin_mux.c new file mode 100644 index 000000000..4c8d6a119 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/scatter_gather/pin_mux.c @@ -0,0 +1,65 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/edma4/scatter_gather/pin_mux.h b/boards/som_mx93/driver_examples/edma4/scatter_gather/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/scatter_gather/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/edma4/scatter_gather/readme.txt b/boards/som_mx93/driver_examples/edma4/scatter_gather/readme.txt new file mode 100644 index 000000000..a206ba876 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/scatter_gather/readme.txt @@ -0,0 +1,48 @@ +Overview +======== +The EDMA memory to memory example is a simple demonstration program thatuses the SDK software. +It executes one shot transfer from source buffer todestination buffer using the SDK EDMA drivers. +The purpose of this example is to show how to use the EDMA and to provide a simple example for +debugging and further development. + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Mini/micro USB cable +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Personal Computer + +Board settings +============== +No special settings are required. + +Prepare the Demo +================ +1. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +2. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +3. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +When the example runs successfully, you can see the similar information from the terminal as below. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +EDMA scatter_gather example begin. + +Destination Buffer: +0 0 0 0 0 0 0 0 + +EDMA scatter_gather example finish. + +Destination Buffer: +1 2 3 4 5 6 7 8 +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + diff --git a/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/CMakeLists.txt b/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/CMakeLists.txt new file mode 100644 index 000000000..0a7723fe2 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/CMakeLists.txt @@ -0,0 +1,114 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(edma4_wrap_transfer) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME edma4_wrap_transfer.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../edma_wrap_transfer.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/devices/MIMX9352/utilities/debug_console_lite + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352/drivers/edma4 + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(utility_debug_console_lite_MIMX9352) + +include(utility_assert_lite_MIMX9352) + +include(driver_memory_MIMX9352) + +include(driver_clock_MIMX9352) + +include(driver_edma4_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_lists_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(driver_edma_soc_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/build_all.bat b/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/build_all.bat new file mode 100644 index 000000000..1205ab083 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/build_all.bat @@ -0,0 +1,15 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/build_all.sh b/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/build_all.sh new file mode 100755 index 000000000..8cc56b74f --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/build_debug.bat b/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/build_debug.sh b/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/build_release.bat b/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/build_release.sh b/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/clean.bat b/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/clean.sh b/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/config.cmake b/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/config.cmake new file mode 100755 index 000000000..920520e3d --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/flags.cmake b/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/flags.cmake new file mode 100755 index 000000000..bf4fa0ef5 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/wrap_transfer/armgcc/flags.cmake @@ -0,0 +1,185 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/driver_examples/edma4/wrap_transfer/board.c b/boards/som_mx93/driver_examples/edma4/wrap_transfer/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/wrap_transfer/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/driver_examples/edma4/wrap_transfer/board.h b/boards/som_mx93/driver_examples/edma4/wrap_transfer/board.h new file mode 100644 index 000000000..5108807ef --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/wrap_transfer/board.h @@ -0,0 +1,89 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + +/* ADP5585 */ +#define BOARD_ADP5585_I2C LPI2C2 +#define BOARD_ADP5585_I2C_ADDR (0x34U) +#define BOARD_ADP5585_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_ADP5585_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_ADP5585_I2C_CLOCK_ROOT) + +#define BOARD_ADP5585_PDM_MQS_SEL (2U) +#define BOARD_ADP5585_EXP_SEL (4U) +#define BOARD_ADP5585_CAN_STBY (8U) + +/* PCAL6524 */ +#define BOARD_PCAL6524_I2C LPI2C2 +#define BOARD_PCAL6524_I2C_ADDR (0x22U) +#define BOARD_PCAL6524_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_PCAL6524_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_PCAL6524_I2C_CLOCK_ROOT) + +#define BOARD_PCAL6524_ENET1_NRST (8U + 7U) +#define BOARD_PCAL6524_ENET2_NRST (16U + 0U) +#define BOARD_PCAL6524_MIC_CAN_SEL (16U + 1U) +#define BOARD_PCAL6524_EXP_SEL (16U + 6U) +#define BOARD_PCAL6524_CAN_STBY (16U + 7U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/driver_examples/edma4/wrap_transfer/clock_config.c b/boards/som_mx93/driver_examples/edma4/wrap_transfer/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/wrap_transfer/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/driver_examples/edma4/wrap_transfer/clock_config.h b/boards/som_mx93/driver_examples/edma4/wrap_transfer/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/wrap_transfer/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/driver_examples/edma4/wrap_transfer/edma_wrap_transfer.c b/boards/som_mx93/driver_examples/edma4/wrap_transfer/edma_wrap_transfer.c new file mode 100644 index 000000000..4e6afb520 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/wrap_transfer/edma_wrap_transfer.c @@ -0,0 +1,105 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_debug_console.h" +#include "fsl_edma.h" + +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define EXAMPLE_DMA_BASEADDR DMA4 +#define EXAMPLE_DMA_CLOCK_ROOT kCLOCK_Root_WakeupAxi +#define EXAMPLE_DMA_CHANNEL 0U +#define BUFF_LENGTH 8U +#define HALF_BUFF_LENGTH (BUFF_LENGTH / 2) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +AT_NONCACHEABLE_SECTION_ALIGN_INIT(uint32_t srcAddr[HALF_BUFF_LENGTH], 16) = {0x01U, 0x02U, 0x03U, 0x04}; +AT_NONCACHEABLE_SECTION_ALIGN_INIT(uint32_t destAddr[BUFF_LENGTH], 16) = {0x00U}; +edma_handle_t g_EDMA_Handle; +volatile bool g_Transfer_Done = false; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* User callback function for EDMA transfer. */ +void EDMA_Callback(edma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds) +{ + if (transferDone) + { + g_Transfer_Done = true; + } +} + +/*! + * @brief Main function + */ +int main(void) +{ + uint32_t i; + edma_transfer_config_t transferConfig; + edma_config_t userConfig; + + /* clang-format off */ + /* 250MHz DMA clock */ + const clock_root_config_t dmaClkCfg = { + .clockOff = false, + .mux = kCLOCK_WAKEUPAXI_ClockRoot_MuxSysPll1Pfd0, // 1000MHz + .div = 4 + }; + /* clang-format on */ + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + + CLOCK_SetRootClock(EXAMPLE_DMA_CLOCK_ROOT, &dmaClkCfg); + /* Print destination buffer */ + PRINTF("EDMA wrap transfer example begin.\r\n\r\n"); + PRINTF("Destination Buffer:\r\n"); + for (i = 0; i < BUFF_LENGTH; i++) + { + PRINTF("%d\t", destAddr[i]); + } + + /* Configure EDMA channel for one shot transfer */ + EDMA_GetDefaultConfig(&userConfig); + EDMA_Init(EXAMPLE_DMA_BASEADDR, &userConfig); + + EDMA_CreateHandle(&g_EDMA_Handle, EXAMPLE_DMA_BASEADDR, EXAMPLE_DMA_CHANNEL); + EDMA_SetCallback(&g_EDMA_Handle, EDMA_Callback, NULL); + EDMA_PrepareTransfer(&transferConfig, srcAddr, sizeof(srcAddr[0]), destAddr, sizeof(destAddr[0]), + sizeof(srcAddr[0]) * BUFF_LENGTH, sizeof(srcAddr[0]) * BUFF_LENGTH, kEDMA_MemoryToMemory); + transferConfig.srcAddrModulo = kEDMA_Modulo16bytes; + EDMA_SubmitTransfer(&g_EDMA_Handle, &transferConfig); + EDMA_StartTransfer(&g_EDMA_Handle); + /* Wait for EDMA transfer finish */ + while (g_Transfer_Done != true) + { + } + /* Print destination buffer */ + PRINTF("\r\n\r\nEDMA wrap transfer example finish.\r\n\r\n"); + PRINTF("Destination Buffer:\r\n"); + for (i = 0; i < BUFF_LENGTH; i++) + { + PRINTF("%d\t", destAddr[i]); + } + while (1) + { + } +} diff --git a/boards/som_mx93/driver_examples/edma4/wrap_transfer/pin_mux.c b/boards/som_mx93/driver_examples/edma4/wrap_transfer/pin_mux.c new file mode 100644 index 000000000..4c8d6a119 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/wrap_transfer/pin_mux.c @@ -0,0 +1,65 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/edma4/wrap_transfer/pin_mux.h b/boards/som_mx93/driver_examples/edma4/wrap_transfer/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/wrap_transfer/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/edma4/wrap_transfer/readme.txt b/boards/som_mx93/driver_examples/edma4/wrap_transfer/readme.txt new file mode 100644 index 000000000..4c7a96940 --- /dev/null +++ b/boards/som_mx93/driver_examples/edma4/wrap_transfer/readme.txt @@ -0,0 +1,51 @@ +Overview +======== +The EDMA wrap transfer example is a simple demonstration program that uses the SDK software. +It excuates wrap transfer from source buffer to destination buffer using the SDK EDMA drivers. +The purpose of this example is to show how to use the wrap feature of EDMA and to provide a simple example for +debugging and further development. + + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Mini/micro USB cable +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Personal Computer + +Board settings +============== +No special settings are required. + +Prepare the Demo +================ +1. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +2. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +3. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +When the example runs successfully, you can see the similar information from the terminal as below. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +EDMA wrap transfer example begin. + +Destination Buffer: + +0 0 0 0 0 0 0 0 + +EDMA wrap transfer example finish. + +Destination Buffer: + +1 2 3 4 1 2 3 4 +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + diff --git a/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/CMakeLists.txt b/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/CMakeLists.txt new file mode 100644 index 000000000..5a4cb6cd4 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/CMakeLists.txt @@ -0,0 +1,111 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(flexcan_loopback) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME flexcan_loopback.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../flexcan_loopback.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/devices/MIMX9352/utilities/debug_console_lite + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(utility_debug_console_lite_MIMX9352) + +include(utility_assert_lite_MIMX9352) + +include(driver_lpi2c_MIMX9352) + +include(driver_flexcan_MIMX9352) + +include(driver_clock_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_lists_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/build_all.bat b/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/build_all.bat new file mode 100644 index 000000000..1205ab083 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/build_all.bat @@ -0,0 +1,15 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/build_all.sh b/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/build_all.sh new file mode 100755 index 000000000..8cc56b74f --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/build_debug.bat b/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/build_debug.sh b/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/build_release.bat b/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/build_release.sh b/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/clean.bat b/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/clean.sh b/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/config.cmake b/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/config.cmake new file mode 100755 index 000000000..920520e3d --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/flags.cmake b/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/flags.cmake new file mode 100755 index 000000000..b44a34afe --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback/armgcc/flags.cmake @@ -0,0 +1,187 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DFLEXCAN_WAIT_TIMEOUT=1000 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DFLEXCAN_WAIT_TIMEOUT=1000 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/driver_examples/flexcan/loopback/board.c b/boards/som_mx93/driver_examples/flexcan/loopback/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/driver_examples/flexcan/loopback/board.h b/boards/som_mx93/driver_examples/flexcan/loopback/board.h new file mode 100644 index 000000000..e20723f41 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback/board.h @@ -0,0 +1,71 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + + + + + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/driver_examples/flexcan/loopback/clock_config.c b/boards/som_mx93/driver_examples/flexcan/loopback/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/driver_examples/flexcan/loopback/clock_config.h b/boards/som_mx93/driver_examples/flexcan/loopback/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/driver_examples/flexcan/loopback/flexcan_loopback.c b/boards/som_mx93/driver_examples/flexcan/loopback/flexcan_loopback.c new file mode 100644 index 000000000..db3adfdd4 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback/flexcan_loopback.c @@ -0,0 +1,297 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_debug_console.h" +#include "fsl_flexcan.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" + +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define EXAMPLE_CAN CAN1 +#define EXAMPLE_FLEXCAN_IRQn CAN1_IRQn +#define EXAMPLE_FLEXCAN_IRQHandler CAN1_IRQHandler +#define RX_MESSAGE_BUFFER_NUM (1) +#define TX_MESSAGE_BUFFER_NUM (0) + +#define FLEXCAN_CLOCK_ROOT kCLOCK_Root_Can1 +#define EXAMPLE_CAN_CLK_FREQ (CLOCK_GetIpFreq(FLEXCAN_CLOCK_ROOT)) +/* Set USE_IMPROVED_TIMING_CONFIG macro to use api to calculates the improved CAN / CAN FD timing values. */ +#define USE_IMPROVED_TIMING_CONFIG (1U) +/* Fix MISRA_C-2012 Rule 17.7. */ +#define LOG_INFO (void)PRINTF + +#if (defined(USE_CANFD) && USE_CANFD) +/* + * DWORD_IN_MB DLC BYTES_IN_MB Maximum MBs + * 2 8 kFLEXCAN_8BperMB 64 + * 4 10 kFLEXCAN_16BperMB 42 + * 8 13 kFLEXCAN_32BperMB 25 + * 16 15 kFLEXCAN_64BperMB 14 + * + * Dword in each message buffer, Length of data in bytes, Payload size must align, + * and the Message Buffers are limited corresponding to each payload configuration: + */ +#define DWORD_IN_MB (16) +#define DLC (15) +#define BYTES_IN_MB kFLEXCAN_64BperMB +#else +#define DLC (8) +#endif +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +volatile bool rxComplete = false; +#if (defined(USE_CANFD) && USE_CANFD) +flexcan_fd_frame_t txFrame, rxFrame; +#else +flexcan_frame_t txFrame, rxFrame; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +void EXAMPLE_FLEXCAN_IRQHandler(void) +{ + /* If new data arrived. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) +#if (RX_MESSAGE_BUFFER_NUM >= 64U) + if (0U != FLEXCAN_GetHigh64MbStatusFlags(EXAMPLE_CAN, (uint64_t)1U << (RX_MESSAGE_BUFFER_NUM - 64U))) + { + FLEXCAN_ClearHigh64MbStatusFlags(EXAMPLE_CAN, (uint64_t)1U << (RX_MESSAGE_BUFFER_NUM - 64U)); + rxComplete = true; + } +#else + if (0U != FLEXCAN_GetMbStatusFlags(EXAMPLE_CAN, (uint64_t)1U << RX_MESSAGE_BUFFER_NUM)) + { + FLEXCAN_ClearMbStatusFlags(EXAMPLE_CAN, (uint64_t)1U << RX_MESSAGE_BUFFER_NUM); + rxComplete = true; + } +#endif +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) && FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) + if (0U != FLEXCAN_GetMbStatusFlags(EXAMPLE_CAN, (uint64_t)1U << RX_MESSAGE_BUFFER_NUM)) + { + FLEXCAN_ClearMbStatusFlags(EXAMPLE_CAN, (uint64_t)1U << RX_MESSAGE_BUFFER_NUM); + rxComplete = true; + } +#else + if (0U != FLEXCAN_GetMbStatusFlags(EXAMPLE_CAN, (uint32_t)1U << RX_MESSAGE_BUFFER_NUM)) + { + FLEXCAN_ClearMbStatusFlags(EXAMPLE_CAN, (uint32_t)1U << RX_MESSAGE_BUFFER_NUM); + rxComplete = true; + } +#endif + + if (rxComplete) + { +#if (defined(USE_CANFD) && USE_CANFD) + (void)FLEXCAN_ReadFDRxMb(EXAMPLE_CAN, RX_MESSAGE_BUFFER_NUM, &rxFrame); +#else + (void)FLEXCAN_ReadRxMb(EXAMPLE_CAN, RX_MESSAGE_BUFFER_NUM, &rxFrame); +#endif + } + SDK_ISR_EXIT_BARRIER; +} + +/*! + * @brief Main function + */ +int main(void) +{ + flexcan_config_t flexcanConfig; + flexcan_rx_mb_config_t mbConfig; + + /* Initialize board hardware. */ + /* clang-format off */ + + const clock_root_config_t flexcanClkCfg = { + .clockOff = false, + .mux = 0, + .div = 1 + }; + /* clang-format on */ + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + + CLOCK_SetRootClock(FLEXCAN_CLOCK_ROOT, &flexcanClkCfg); + + LOG_INFO("\r\n==FlexCAN loopback functional example -- Start.==\r\n\r\n"); + + /* Init FlexCAN module. */ + /* + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrc0; + * flexcanConfig.bitRate = 1000000U; + * flexcanConfig.bitRateFD = 2000000U; + * flexcanConfig.maxMbNum = 16; + * flexcanConfig.enableLoopBack = false; + * flexcanConfig.enableSelfWakeup = false; + * flexcanConfig.enableIndividMask = false; + * flexcanConfig.disableSelfReception = false; + * flexcanConfig.enableListenOnlyMode = false; + * flexcanConfig.enableDoze = false; + */ + FLEXCAN_GetDefaultConfig(&flexcanConfig); + +#if defined(EXAMPLE_CAN_CLK_SOURCE) + flexcanConfig.clkSrc = EXAMPLE_CAN_CLK_SOURCE; +#endif + + flexcanConfig.enableLoopBack = true; + +#if (defined(USE_IMPROVED_TIMING_CONFIG) && USE_IMPROVED_TIMING_CONFIG) + flexcan_timing_config_t timing_config; + memset(&timing_config, 0, sizeof(flexcan_timing_config_t)); +#if (defined(USE_CANFD) && USE_CANFD) + if (FLEXCAN_FDCalculateImprovedTimingValues(EXAMPLE_CAN, flexcanConfig.bitRate, flexcanConfig.bitRateFD, + EXAMPLE_CAN_CLK_FREQ, &timing_config)) + { + /* Update the improved timing configuration*/ + memcpy(&(flexcanConfig.timingConfig), &timing_config, sizeof(flexcan_timing_config_t)); + } + else + { + LOG_INFO("No found Improved Timing Configuration. Just used default configuration\r\n\r\n"); + } +#else + if (FLEXCAN_CalculateImprovedTimingValues(EXAMPLE_CAN, flexcanConfig.bitRate, EXAMPLE_CAN_CLK_FREQ, &timing_config)) + { + /* Update the improved timing configuration*/ + memcpy(&(flexcanConfig.timingConfig), &timing_config, sizeof(flexcan_timing_config_t)); + } + else + { + LOG_INFO("No found Improved Timing Configuration. Just used default configuration\r\n\r\n"); + } +#endif +#endif + +#if (defined(USE_CANFD) && USE_CANFD) + FLEXCAN_FDInit(EXAMPLE_CAN, &flexcanConfig, EXAMPLE_CAN_CLK_FREQ, BYTES_IN_MB, true); +#else + FLEXCAN_Init(EXAMPLE_CAN, &flexcanConfig, EXAMPLE_CAN_CLK_FREQ); +#endif + + /* Setup Rx Message Buffer. */ + mbConfig.format = kFLEXCAN_FrameFormatStandard; + mbConfig.type = kFLEXCAN_FrameTypeData; + mbConfig.id = FLEXCAN_ID_STD(0x123); +#if (defined(USE_CANFD) && USE_CANFD) + FLEXCAN_SetFDRxMbConfig(EXAMPLE_CAN, RX_MESSAGE_BUFFER_NUM, &mbConfig, true); +#else + FLEXCAN_SetRxMbConfig(EXAMPLE_CAN, RX_MESSAGE_BUFFER_NUM, &mbConfig, true); +#endif + +/* Setup Tx Message Buffer. */ +#if (defined(USE_CANFD) && USE_CANFD) + FLEXCAN_SetFDTxMbConfig(EXAMPLE_CAN, TX_MESSAGE_BUFFER_NUM, true); +#else + FLEXCAN_SetTxMbConfig(EXAMPLE_CAN, TX_MESSAGE_BUFFER_NUM, true); +#endif + + /* Enable Rx Message Buffer interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) +#if (RX_MESSAGE_BUFFER_NUM >= 64U) + FLEXCAN_EnableHigh64MbInterrupts(EXAMPLE_CAN, (uint64_t)1U << (RX_MESSAGE_BUFFER_NUM - 64U)); +#else + FLEXCAN_EnableMbInterrupts(EXAMPLE_CAN, (uint64_t)1U << RX_MESSAGE_BUFFER_NUM); + +#endif +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) && FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) + FLEXCAN_EnableMbInterrupts(EXAMPLE_CAN, (uint64_t)1U << RX_MESSAGE_BUFFER_NUM); + +#else + FLEXCAN_EnableMbInterrupts(EXAMPLE_CAN, (uint32_t)1U << RX_MESSAGE_BUFFER_NUM); +#endif + (void)EnableIRQ(EXAMPLE_FLEXCAN_IRQn); + + /* Prepare Tx Frame for sending. */ + txFrame.format = (uint8_t)kFLEXCAN_FrameFormatStandard; + txFrame.type = (uint8_t)kFLEXCAN_FrameTypeData; + txFrame.id = FLEXCAN_ID_STD(0x123); + txFrame.length = (uint8_t)DLC; +#if (defined(USE_CANFD) && USE_CANFD) + txFrame.brs = 1U; + txFrame.edl = 1U; +#endif +#if (defined(USE_CANFD) && USE_CANFD) + uint8_t i = 0; + for (i = 0; i < DWORD_IN_MB; i++) + { + txFrame.dataWord[i] = i; + } +#else + txFrame.dataWord0 = CAN_WORD0_DATA_BYTE_0(0x11) | CAN_WORD0_DATA_BYTE_1(0x22) | CAN_WORD0_DATA_BYTE_2(0x33) | + CAN_WORD0_DATA_BYTE_3(0x44); + txFrame.dataWord1 = CAN_WORD1_DATA_BYTE_4(0x55) | CAN_WORD1_DATA_BYTE_5(0x66) | CAN_WORD1_DATA_BYTE_6(0x77) | + CAN_WORD1_DATA_BYTE_7(0x88); +#endif + + LOG_INFO("Send message from MB%d to MB%d\r\n", TX_MESSAGE_BUFFER_NUM, RX_MESSAGE_BUFFER_NUM); +#if (defined(USE_CANFD) && USE_CANFD) + for (i = 0; i < DWORD_IN_MB; i++) + { + LOG_INFO("tx word%d = 0x%x\r\n", i, txFrame.dataWord[i]); + } +#else + LOG_INFO("tx word0 = 0x%x\r\n", txFrame.dataWord0); + LOG_INFO("tx word1 = 0x%x\r\n", txFrame.dataWord1); +#endif + +/* Send data through Tx Message Buffer using polling function. */ +#if (defined(USE_CANFD) && USE_CANFD) + (void)FLEXCAN_TransferFDSendBlocking(EXAMPLE_CAN, TX_MESSAGE_BUFFER_NUM, &txFrame); +#else + (void)FLEXCAN_TransferSendBlocking(EXAMPLE_CAN, TX_MESSAGE_BUFFER_NUM, &txFrame); +#endif + + /* Waiting for Message receive finish. */ + while (!rxComplete) + { + } + + LOG_INFO("\r\nReceived message from MB%d\r\n", RX_MESSAGE_BUFFER_NUM); +#if (defined(USE_CANFD) && USE_CANFD) + for (i = 0; i < DWORD_IN_MB; i++) + { + LOG_INFO("rx word%d = 0x%x\r\n", i, rxFrame.dataWord[i]); + } +#else + LOG_INFO("rx word0 = 0x%x\r\n", rxFrame.dataWord0); + LOG_INFO("rx word1 = 0x%x\r\n", rxFrame.dataWord1); +#endif + + /* Stop FlexCAN Send & Receive. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) +#if (RX_MESSAGE_BUFFER_NUM >= 64U) + FLEXCAN_DisableHigh64MbInterrupts(EXAMPLE_CAN, (uint64_t)1U << (RX_MESSAGE_BUFFER_NUM - 64U)); +#else + FLEXCAN_DisableMbInterrupts(EXAMPLE_CAN, (uint64_t)1U << RX_MESSAGE_BUFFER_NUM); + +#endif +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) && FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) + FLEXCAN_DisableMbInterrupts(EXAMPLE_CAN, (uint64_t)1U << RX_MESSAGE_BUFFER_NUM); + +#else + FLEXCAN_DisableMbInterrupts(EXAMPLE_CAN, (uint32_t)1U << RX_MESSAGE_BUFFER_NUM); +#endif + + LOG_INFO("\r\n==FlexCAN loopback functional example -- Finish.==\r\n"); + + while (true) + { + } +} diff --git a/boards/som_mx93/driver_examples/flexcan/loopback/pin_mux.c b/boards/som_mx93/driver_examples/flexcan/loopback/pin_mux.c new file mode 100644 index 000000000..10cb5de9d --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback/pin_mux.c @@ -0,0 +1,87 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: J17, peripheral: CAN1, signal: can_rx, pin_signal: PDM_BIT_STREAM0, APC: DOMAIN0_ACCESS, HYS: DISABLED} + - {pin_num: G17, peripheral: CAN1, signal: can_tx, pin_signal: PDM_CLK, HYS: DISABLED} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, HYS: DISABLED, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, HYS: DISABLED, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_I2C1_SCL__LPI2C1_SCL, 1U); + IOMUXC_SetPinMux(IOMUXC_PAD_I2C1_SDA__LPI2C1_SDA, 1U); + IOMUXC_SetPinMux(IOMUXC_PAD_PDM_BIT_STREAM0__CAN1_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_PDM_CLK__CAN1_TX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_I2C1_SCL__LPI2C1_SCL, + IOMUXC_PAD_DSE(15U) | + IOMUXC_PAD_FSEL1(2U) | + IOMUXC_PAD_OD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_I2C1_SDA__LPI2C1_SDA, + IOMUXC_PAD_DSE(15U) | + IOMUXC_PAD_FSEL1(2U) | + IOMUXC_PAD_OD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_PDM_BIT_STREAM0__CAN1_RX, + IOMUXC_PAD_DSE(15U) | + IOMUXC_PAD_FSEL1(2U) | + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_PDM_CLK__CAN1_TX, + IOMUXC_PAD_DSE(15U) | + IOMUXC_PAD_FSEL1(2U) | + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/flexcan/loopback/pin_mux.h b/boards/som_mx93/driver_examples/flexcan/loopback/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/flexcan/loopback/readme.txt b/boards/som_mx93/driver_examples/flexcan/loopback/readme.txt new file mode 100644 index 000000000..7490689ae --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback/readme.txt @@ -0,0 +1,65 @@ +Overview +======== +The flexcan_loopback_functional example shows how to use the loopback test mode to debug your CAN Bus design: + +To demonstrates this example, only one board is needed. The example will config one FlexCAN Message +Buffer to Rx Message Buffer and the other FlexCAN Message Buffer to Tx Message Buffer with same ID. +After that, the example will send a CAN Message from the Tx Message Buffer to the Rx Message Buffer +throuth internal loopback interconnect and print out the Message payload to terminal. + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Micro USB cable +- USB to UART Adapter +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- JLink Plus +- Proper power supply +- Personal Computer + +Board settings +============== +No special is needed. + + +Prepare the Demo +================ +1. Connect the power supply to the board and switch on the board +2. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +3. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +When the example runs successfully, following information can be seen on the terminal: + +~~~~~~~~~~~~~~~~~~~~~ + +==FlexCAN loopback functional example -- Start.== + + +Send message from MB8 to MB9 + +tx word0 = 0x11223344 + +tx word1 = 0x55667788 + + +Receved message from MB9 + +rx word0 = 0x11223344 + +rx word1 = 0x55667788 + + +==FlexCAN loopback functional example -- Finish.== +~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/CMakeLists.txt b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/CMakeLists.txt new file mode 100644 index 000000000..d1102761a --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/CMakeLists.txt @@ -0,0 +1,118 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(flexcan_loopback_edma_transfer) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME flexcan_loopback_edma_transfer.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../flexcan_loopback_edma_transfer.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/devices/MIMX9352/drivers/dma3 + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/devices/MIMX9352/utilities/debug_console_lite + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(driver_dma3_MIMX9352) + +include(utility_debug_console_lite_MIMX9352) + +include(utility_assert_lite_MIMX9352) + +include(driver_lpi2c_MIMX9352) + +include(driver_flexcan_MIMX9352) + +include(driver_flexcan_edma_MIMX9352) + +include(driver_clock_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_lists_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(driver_memory_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/build_all.bat b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/build_all.bat new file mode 100644 index 000000000..1205ab083 --- /dev/null +++ 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b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/build_all.sh new file mode 100755 index 000000000..8cc56b74f --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/build_debug.bat b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/build_debug.sh b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/build_release.bat b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/build_release.sh b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/clean.bat b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/clean.sh b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/config.cmake b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/config.cmake new file mode 100755 index 000000000..920520e3d --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/flags.cmake b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/flags.cmake new file mode 100755 index 000000000..b44a34afe --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/armgcc/flags.cmake @@ -0,0 +1,187 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DFLEXCAN_WAIT_TIMEOUT=1000 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DFLEXCAN_WAIT_TIMEOUT=1000 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/board.c b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/board.h b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/board.h new file mode 100644 index 000000000..e20723f41 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/board.h @@ -0,0 +1,71 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + + + + + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/clock_config.c b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/clock_config.h b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/flexcan_loopback_edma_transfer.c b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/flexcan_loopback_edma_transfer.c new file mode 100644 index 000000000..45046b8cf --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/flexcan_loopback_edma_transfer.c @@ -0,0 +1,236 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_device_registers.h" +#include "fsl_debug_console.h" +#include "fsl_flexcan.h" +#include "fsl_flexcan_edma.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#if defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT +#include "fsl_dmamux.h" +#endif +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define EXAMPLE_CAN CAN1 +#define TX_MESSAGE_BUFFER_NUM (9) + +#define EXAMPLE_CAN_DMA (DMA3) +#define EXAMPLE_CAN_DMA_CHANNEL kDma3RequestMuxCAN1 + +#define FLEXCAN_CLOCK_ROOT kCLOCK_Root_Can1 +#define EXAMPLE_CAN_CLK_FREQ CLOCK_GetIpFreq(FLEXCAN_CLOCK_ROOT) +#define EXAMPLE_DMA_CLOCK_ROOT kCLOCK_Root_WakeupAxi +#define USE_IMPROVED_TIMING_CONFIG (1U) +/* Fix MISRA_C-2012 Rule 17.7. */ +#define LOG_INFO (void)PRINTF +#ifndef EXAMPLE_RX_MESSAGE_NUM +#define EXAMPLE_RX_MESSAGE_NUM (4) +#endif +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +volatile bool txComplete = false; +volatile bool rxComplete = false; +flexcan_handle_t flexcanHandle; +flexcan_edma_handle_t flexcanEdmaHandle; +edma_handle_t flexcanRxFifoEdmaHandle; +flexcan_mb_transfer_t txXfer; +flexcan_fifo_transfer_t rxFifoXfer; +flexcan_frame_t txFrame; +AT_NONCACHEABLE_SECTION(flexcan_frame_t rxFrame[EXAMPLE_RX_MESSAGE_NUM]); + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * @brief FlexCAN Call Back function + */ +static FLEXCAN_CALLBACK(flexcan_callback) +{ + /* Process FlexCAN Tx event. */ + if ((kStatus_FLEXCAN_TxIdle == status) && (TX_MESSAGE_BUFFER_NUM == result)) + { + txComplete = true; + } +} + +/*! + * @brief FlexCAN DMA Call Back function + */ +static void flexcan_dma_callback(CAN_Type *base, flexcan_edma_handle_t *handle, status_t status, void *userData) +{ + /* Process FlexCAN Rx event. */ + if (kStatus_FLEXCAN_RxFifoIdle == status) + { + rxComplete = true; + } +} + +/*! + * @brief Main function + */ +int main(void) +{ + edma_config_t edmaConfig; + flexcan_config_t flexcanConfig; + flexcan_rx_fifo_config_t rxFifoConfig; + uint32_t rxFifoFilter[] = { + FLEXCAN_RX_FIFO_STD_FILTER_TYPE_A(0x321, 0, 0), FLEXCAN_RX_FIFO_STD_FILTER_TYPE_A(0x321, 1, 0), + FLEXCAN_RX_FIFO_STD_FILTER_TYPE_A(0x123, 0, 0), FLEXCAN_RX_FIFO_STD_FILTER_TYPE_A(0x123, 1, 0)}; + + /* Initialize board hardware. */ + /* clang-format off */ + /* 250MHz DMA clock */ + const clock_root_config_t dmaClkCfg = { + .clockOff = false, + .mux = kCLOCK_WAKEUPAXI_ClockRoot_MuxSysPll1Pfd0, // 1000MHz + .div = 4 + }; + const clock_root_config_t flexcanClkCfg = { + .clockOff = false, + .mux = 0, + .div = 1 + }; + /* clang-format on */ + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + + CLOCK_SetRootClock(EXAMPLE_DMA_CLOCK_ROOT, &dmaClkCfg); + CLOCK_SetRootClock(FLEXCAN_CLOCK_ROOT, &flexcanClkCfg); + + LOG_INFO("\r\n==FlexCAN loopback edma example -- Start.==\r\n\r\n"); + + /* Init FlexCAN module. */ + /* + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrc0; + * flexcanConfig.bitRate = 1000000U; + * flexcanConfig.bitRateFD = 2000000U; + * flexcanConfig.maxMbNum = 16; + * flexcanConfig.enableLoopBack = false; + * flexcanConfig.enableSelfWakeup = false; + * flexcanConfig.enableIndividMask = false; + * flexcanConfig.disableSelfReception = false; + * flexcanConfig.enableListenOnlyMode = false; + * flexcanConfig.enableDoze = false; + */ + FLEXCAN_GetDefaultConfig(&flexcanConfig); + +#if defined(EXAMPLE_CAN_CLK_SOURCE) + flexcanConfig.clkSrc = EXAMPLE_CAN_CLK_SOURCE; +#endif + /* Enable internal loopback. */ + flexcanConfig.enableLoopBack = true; + +#if (defined(USE_IMPROVED_TIMING_CONFIG) && USE_IMPROVED_TIMING_CONFIG) + flexcan_timing_config_t timing_config; + memset(&timing_config, 0, sizeof(flexcan_timing_config_t)); + if (FLEXCAN_CalculateImprovedTimingValues(EXAMPLE_CAN, flexcanConfig.bitRate, EXAMPLE_CAN_CLK_FREQ, &timing_config)) + { + /* Update the improved timing configuration*/ + memcpy(&(flexcanConfig.timingConfig), &timing_config, sizeof(flexcan_timing_config_t)); + } + else + { + LOG_INFO("No found Improved Timing Configuration. Just used default configuration\r\n\r\n"); + } +#endif + + FLEXCAN_Init(EXAMPLE_CAN, &flexcanConfig, EXAMPLE_CAN_CLK_FREQ); + +#if defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT + /* Configure DMA. */ + DMAMUX_Init(EXAMPLE_CAN_DMAMUX); + DMAMUX_SetSource(EXAMPLE_CAN_DMAMUX, EXAMPLE_CAN_DMA_CHANNEL, EXAMPLE_CAN_DMA_REQUEST); + DMAMUX_EnableChannel(EXAMPLE_CAN_DMAMUX, EXAMPLE_CAN_DMA_CHANNEL); +#endif + + /* + * edmaConfig.enableRoundRobinArbitration = false; + * edmaConfig.enableHaltOnError = true; + * edmaConfig.enableContinuousLinkMode = false; + * edmaConfig.enableDebugMode = false; + */ + EDMA_GetDefaultConfig(&edmaConfig); + EDMA_Init(EXAMPLE_CAN_DMA, &edmaConfig); + + /* Create EDMA handle. */ + EDMA_CreateHandle(&flexcanRxFifoEdmaHandle, EXAMPLE_CAN_DMA, EXAMPLE_CAN_DMA_CHANNEL); +#if defined(FSL_FEATURE_EDMA_HAS_CHANNEL_MUX) && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX + EDMA_SetChannelMux(EXAMPLE_CAN_DMA, EXAMPLE_CAN_DMA_CHANNEL, FLEXCAN_DMA_REQUEST_SOURCE); +#endif + + /* Setup Tx Message Buffer. */ + FLEXCAN_SetTxMbConfig(EXAMPLE_CAN, TX_MESSAGE_BUFFER_NUM, true); + + /* Setup Rx FIFO. */ + rxFifoConfig.idFilterTable = rxFifoFilter; + rxFifoConfig.idFilterType = kFLEXCAN_RxFifoFilterTypeA; + rxFifoConfig.idFilterNum = sizeof(rxFifoFilter) / sizeof(rxFifoFilter[0]); + rxFifoConfig.priority = kFLEXCAN_RxFifoPrioHigh; + FLEXCAN_SetRxFifoConfig(EXAMPLE_CAN, &rxFifoConfig, true); + + /* Create FlexCAN handle structure and set call back function. */ + FLEXCAN_TransferCreateHandle(EXAMPLE_CAN, &flexcanHandle, flexcan_callback, NULL); + + /* Create FlexCAN EDMA handle structure and set call back function. */ + FLEXCAN_TransferCreateHandleEDMA(EXAMPLE_CAN, &flexcanEdmaHandle, flexcan_dma_callback, NULL, + &flexcanRxFifoEdmaHandle); + /* Receive data through Rx FIFO. */ + rxFifoXfer.frame = &rxFrame[0]; + rxFifoXfer.frameNum = EXAMPLE_RX_MESSAGE_NUM; + (void)FLEXCAN_TransferReceiveFifoEDMA(EXAMPLE_CAN, &flexcanEdmaHandle, &rxFifoXfer); + + for (uint32_t i = 1; i <= EXAMPLE_RX_MESSAGE_NUM; i++) + { + /* Send message through Tx Message Buffer. */ + txFrame.format = (uint8_t)kFLEXCAN_FrameFormatStandard; + txFrame.type = (uint8_t)kFLEXCAN_FrameTypeData; + txFrame.id = FLEXCAN_ID_STD(0x123); + txFrame.length = 8U; + txFrame.dataWord0 = CAN_WORD0_DATA_BYTE_0(0x11 * i) | CAN_WORD0_DATA_BYTE_1(0x11 * i) | + CAN_WORD0_DATA_BYTE_2(0x11 * i) | CAN_WORD0_DATA_BYTE_3(0x11 * i); + txFrame.dataWord1 = CAN_WORD1_DATA_BYTE_4(0x11 * i) | CAN_WORD1_DATA_BYTE_5(0x11 * i) | + CAN_WORD1_DATA_BYTE_6(0x11 * i) | CAN_WORD1_DATA_BYTE_7(0x11 * i); + + txXfer.frame = &txFrame; + txXfer.mbIdx = (uint8_t)TX_MESSAGE_BUFFER_NUM; + (void)FLEXCAN_TransferSendNonBlocking(EXAMPLE_CAN, &flexcanHandle, &txXfer); + while (!txComplete) + { + } + txComplete = false; + LOG_INFO("Send Msg%d to Rx FIFO: word0 = 0x%x, word1 = 0x%x.\r\n", i, txFrame.dataWord0, txFrame.dataWord1); + } + + while (!rxComplete) + { + } + rxComplete = false; + for (uint32_t i = 0; i < EXAMPLE_RX_MESSAGE_NUM; i++) + { + LOG_INFO("Receive Msg%d from FIFO: word0 = 0x%x, word1 = 0x%x, ID Filter Hit%d.\r\n", i + 1, + rxFrame[i].dataWord0, rxFrame[i].dataWord1, rxFrame[i].idhit); + } + + LOG_INFO("\r\n==FlexCAN loopback EDMA example -- Finish.==\r\n"); + + while (true) + { + __WFI(); + } +} diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/pin_mux.c b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/pin_mux.c new file mode 100644 index 000000000..10cb5de9d --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/pin_mux.c @@ -0,0 +1,87 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: J17, peripheral: CAN1, signal: can_rx, pin_signal: PDM_BIT_STREAM0, APC: DOMAIN0_ACCESS, HYS: DISABLED} + - {pin_num: G17, peripheral: CAN1, signal: can_tx, pin_signal: PDM_CLK, HYS: DISABLED} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, HYS: DISABLED, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, HYS: DISABLED, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_I2C1_SCL__LPI2C1_SCL, 1U); + IOMUXC_SetPinMux(IOMUXC_PAD_I2C1_SDA__LPI2C1_SDA, 1U); + IOMUXC_SetPinMux(IOMUXC_PAD_PDM_BIT_STREAM0__CAN1_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_PDM_CLK__CAN1_TX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_I2C1_SCL__LPI2C1_SCL, + IOMUXC_PAD_DSE(15U) | + IOMUXC_PAD_FSEL1(2U) | + IOMUXC_PAD_OD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_I2C1_SDA__LPI2C1_SDA, + IOMUXC_PAD_DSE(15U) | + IOMUXC_PAD_FSEL1(2U) | + IOMUXC_PAD_OD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_PDM_BIT_STREAM0__CAN1_RX, + IOMUXC_PAD_DSE(15U) | + IOMUXC_PAD_FSEL1(2U) | + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_PDM_CLK__CAN1_TX, + IOMUXC_PAD_DSE(15U) | + IOMUXC_PAD_FSEL1(2U) | + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/pin_mux.h b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/readme.txt b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/readme.txt new file mode 100644 index 000000000..c85702ee0 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_edma_transfer/readme.txt @@ -0,0 +1,61 @@ +Overview +======== +The flexcan_loopback_edma example shows how to use the EDMA version transactional driver to receive +CAN Message from Rx FIFO: + +To demonstrates this example, only one board is needed. The example will config one FlexCAN Message +Buffer to Tx Message Buffer and also setup Rx FIFO. After that, the example will send 4 CAN Messages +from Tx Message Buffer to Rx FIFO through internal loopback interconnect and read them out using +EDMA version FlexCAN transactional driver. The Sent and received message will be print out to terminal +at last. + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Micro USB cable +- USB to UART Adapter +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- JLink Plus +- Proper power supply +- Personal Computer + +Board settings +============== +No special is needed. + +Prepare the Demo +================ +1. Connect the power supply to the board and switch on the board +2. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +3. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +When the example runs successfully, following information can be seen on the terminal: + +~~~~~~~~~~~~~~~~~~~~~ + +==FlexCAN loopback edma example -- Start.== + +Send Msg1 to Rx FIFO: word0 = 0x11111111, word1 = 0x11111111. +Send Msg2 to Rx FIFO: word0 = 0x22222222, word1 = 0x22222222. +Send Msg3 to Rx FIFO: word0 = 0x33333333, word1 = 0x33333333. +Send Msg4 to Rx FIFO: word0 = 0x44444444, word1 = 0x44444444. + +Receive Msg1 from FIFO: word0 = 0x11111111, word1 = 0x11111111, ID Filter Hit2. +Receive Msg2 from FIFO: word0 = 0x22222222, word1 = 0x22222222, ID Filter Hit2. +Receive Msg3 from FIFO: word0 = 0x33333333, word1 = 0x33333333, ID Filter Hit2. +Receive Msg4 from FIFO: word0 = 0x44444444, word1 = 0x44444444, ID Filter Hit2. + +==FlexCAN loopback EDMA example -- Finish.== +~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/CMakeLists.txt b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/CMakeLists.txt new file mode 100644 index 000000000..639b880d0 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/CMakeLists.txt @@ -0,0 +1,111 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(flexcan_loopback_transfer) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME flexcan_loopback_transfer.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../flexcan_loopback_transfer.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/devices/MIMX9352/utilities/debug_console_lite + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(utility_debug_console_lite_MIMX9352) + +include(utility_assert_lite_MIMX9352) + +include(driver_lpi2c_MIMX9352) + +include(driver_flexcan_MIMX9352) + +include(driver_clock_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_lists_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/build_all.bat b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/build_all.bat new file mode 100644 index 000000000..1205ab083 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/build_all.bat @@ -0,0 +1,15 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/build_all.sh b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/build_all.sh new file mode 100755 index 000000000..8cc56b74f --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/build_debug.bat b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/build_debug.sh b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/build_release.bat b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/build_release.sh b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/clean.bat b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/clean.sh b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/config.cmake b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/config.cmake new file mode 100755 index 000000000..920520e3d --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/flags.cmake b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/flags.cmake new file mode 100755 index 000000000..b44a34afe --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/armgcc/flags.cmake @@ -0,0 +1,187 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DFLEXCAN_WAIT_TIMEOUT=1000 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DFLEXCAN_WAIT_TIMEOUT=1000 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_transfer/board.c b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_transfer/board.h b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/board.h new file mode 100644 index 000000000..e20723f41 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/board.h @@ -0,0 +1,71 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + + + + + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_transfer/clock_config.c b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_transfer/clock_config.h b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_transfer/flexcan_loopback_transfer.c b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/flexcan_loopback_transfer.c new file mode 100644 index 000000000..6e0f0cc4b --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/flexcan_loopback_transfer.c @@ -0,0 +1,268 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_debug_console.h" +#include "fsl_flexcan.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" + +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define EXAMPLE_CAN CAN1 +#define RX_MESSAGE_BUFFER_NUM (1) +#define TX_MESSAGE_BUFFER_NUM (0) + +#define FLEXCAN_CLOCK_ROOT kCLOCK_Root_Can1 +#define EXAMPLE_CAN_CLK_FREQ (CLOCK_GetIpFreq(FLEXCAN_CLOCK_ROOT)) +/* Set USE_IMPROVED_TIMING_CONFIG macro to use api to calculates the improved CAN / CAN FD timing values. */ +#define USE_IMPROVED_TIMING_CONFIG (1U) +/* Fix MISRA_C-2012 Rule 17.7. */ +#define LOG_INFO (void)PRINTF + +#if (defined(USE_CANFD) && USE_CANFD) +/* + * DWORD_IN_MB DLC BYTES_IN_MB Maximum MBs + * 2 8 kFLEXCAN_8BperMB 64 + * 4 10 kFLEXCAN_16BperMB 42 + * 8 13 kFLEXCAN_32BperMB 25 + * 16 15 kFLEXCAN_64BperMB 14 + * + * Dword in each message buffer, Length of data in bytes, Payload size must align, + * and the Message Buffers are limited corresponding to each payload configuration: + */ +#define DWORD_IN_MB (16) +#define DLC (15) +#define BYTES_IN_MB kFLEXCAN_64BperMB +#else +#define DLC (8) +#endif +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +volatile bool txComplete = false; +volatile bool rxComplete = false; +flexcan_handle_t flexcanHandle; +flexcan_mb_transfer_t txXfer, rxXfer; +#if (defined(USE_CANFD) && USE_CANFD) +flexcan_fd_frame_t txFrame, rxFrame; +#else +flexcan_frame_t txFrame, rxFrame; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief FlexCAN Call Back function + */ +static FLEXCAN_CALLBACK(flexcan_callback) +{ + switch (status) + { + /* Process FlexCAN Rx event. */ + case kStatus_FLEXCAN_RxIdle: + if (RX_MESSAGE_BUFFER_NUM == result) + { + rxComplete = true; + } + break; + + /* Process FlexCAN Tx event. */ + case kStatus_FLEXCAN_TxIdle: + if (TX_MESSAGE_BUFFER_NUM == result) + { + txComplete = true; + } + break; + + default: + break; + } +} + +/*! + * @brief Main function + */ +int main(void) +{ + flexcan_config_t flexcanConfig; + flexcan_rx_mb_config_t mbConfig; + + /* Initialize board hardware. */ + /* clang-format off */ + + const clock_root_config_t flexcanClkCfg = { + .clockOff = false, + .mux = 2, + .div = 10 + }; + /* clang-format on */ + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + + CLOCK_SetRootClock(FLEXCAN_CLOCK_ROOT, &flexcanClkCfg); + + LOG_INFO("\r\n==FlexCAN loopback example -- Start.==\r\n\r\n"); + + /* Init FlexCAN module. */ + /* + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrc0; + * flexcanConfig.bitRate = 1000000U; + * flexcanConfig.bitRateFD = 2000000U; + * flexcanConfig.maxMbNum = 16; + * flexcanConfig.enableLoopBack = false; + * flexcanConfig.enableSelfWakeup = false; + * flexcanConfig.enableIndividMask = false; + * flexcanConfig.disableSelfReception = false; + * flexcanConfig.enableListenOnlyMode = false; + * flexcanConfig.enableDoze = false; + */ + FLEXCAN_GetDefaultConfig(&flexcanConfig); + +#if defined(EXAMPLE_CAN_CLK_SOURCE) + flexcanConfig.clkSrc = EXAMPLE_CAN_CLK_SOURCE; +#endif + + flexcanConfig.enableLoopBack = true; + +#if (defined(USE_IMPROVED_TIMING_CONFIG) && USE_IMPROVED_TIMING_CONFIG) + flexcan_timing_config_t timing_config; + memset(&timing_config, 0, sizeof(flexcan_timing_config_t)); +#if (defined(USE_CANFD) && USE_CANFD) + if (FLEXCAN_FDCalculateImprovedTimingValues(EXAMPLE_CAN, flexcanConfig.bitRate, flexcanConfig.bitRateFD, + EXAMPLE_CAN_CLK_FREQ, &timing_config)) + { + /* Update the improved timing configuration*/ + memcpy(&(flexcanConfig.timingConfig), &timing_config, sizeof(flexcan_timing_config_t)); + } + else + { + LOG_INFO("No found Improved Timing Configuration. Just used default configuration\r\n\r\n"); + } +#else + if (FLEXCAN_CalculateImprovedTimingValues(EXAMPLE_CAN, flexcanConfig.bitRate, EXAMPLE_CAN_CLK_FREQ, &timing_config)) + { + /* Update the improved timing configuration*/ + memcpy(&(flexcanConfig.timingConfig), &timing_config, sizeof(flexcan_timing_config_t)); + } + else + { + LOG_INFO("No found Improved Timing Configuration. Just used default configuration\r\n\r\n"); + } +#endif +#endif + +#if (defined(USE_CANFD) && USE_CANFD) + FLEXCAN_FDInit(EXAMPLE_CAN, &flexcanConfig, EXAMPLE_CAN_CLK_FREQ, BYTES_IN_MB, true); +#else + FLEXCAN_Init(EXAMPLE_CAN, &flexcanConfig, EXAMPLE_CAN_CLK_FREQ); +#endif + + /* Setup Rx Message Buffer. */ + mbConfig.format = kFLEXCAN_FrameFormatStandard; + mbConfig.type = kFLEXCAN_FrameTypeData; + mbConfig.id = FLEXCAN_ID_STD(0x123); +#if (defined(USE_CANFD) && USE_CANFD) + FLEXCAN_SetFDRxMbConfig(EXAMPLE_CAN, RX_MESSAGE_BUFFER_NUM, &mbConfig, true); +#else + FLEXCAN_SetRxMbConfig(EXAMPLE_CAN, RX_MESSAGE_BUFFER_NUM, &mbConfig, true); +#endif + +/* Setup Tx Message Buffer. */ +#if (defined(USE_CANFD) && USE_CANFD) + FLEXCAN_SetFDTxMbConfig(EXAMPLE_CAN, TX_MESSAGE_BUFFER_NUM, true); +#else + FLEXCAN_SetTxMbConfig(EXAMPLE_CAN, TX_MESSAGE_BUFFER_NUM, true); +#endif + + /* Create FlexCAN handle structure and set call back function. */ + FLEXCAN_TransferCreateHandle(EXAMPLE_CAN, &flexcanHandle, flexcan_callback, NULL); + + /* Start receive data through Rx Message Buffer. */ + rxXfer.mbIdx = (uint8_t)RX_MESSAGE_BUFFER_NUM; +#if (defined(USE_CANFD) && USE_CANFD) + rxXfer.framefd = &rxFrame; + (void)FLEXCAN_TransferFDReceiveNonBlocking(EXAMPLE_CAN, &flexcanHandle, &rxXfer); +#else + rxXfer.frame = &rxFrame; + (void)FLEXCAN_TransferReceiveNonBlocking(EXAMPLE_CAN, &flexcanHandle, &rxXfer); +#endif + + /* Prepare Tx Frame for sending. */ + txFrame.format = (uint8_t)kFLEXCAN_FrameFormatStandard; + txFrame.type = (uint8_t)kFLEXCAN_FrameTypeData; + txFrame.id = FLEXCAN_ID_STD(0x123); + txFrame.length = (uint8_t)DLC; +#if (defined(USE_CANFD) && USE_CANFD) + txFrame.brs = 1U; + txFrame.edl = 1U; +#endif +#if (defined(USE_CANFD) && USE_CANFD) + uint8_t i = 0; + for (i = 0; i < DWORD_IN_MB; i++) + { + txFrame.dataWord[i] = i; + } +#else + txFrame.dataWord0 = CAN_WORD0_DATA_BYTE_0(0x11) | CAN_WORD0_DATA_BYTE_1(0x22) | CAN_WORD0_DATA_BYTE_2(0x33) | + CAN_WORD0_DATA_BYTE_3(0x44); + txFrame.dataWord1 = CAN_WORD1_DATA_BYTE_4(0x55) | CAN_WORD1_DATA_BYTE_5(0x66) | CAN_WORD1_DATA_BYTE_6(0x77) | + CAN_WORD1_DATA_BYTE_7(0x88); +#endif + + LOG_INFO("Send message from MB%d to MB%d\r\n", TX_MESSAGE_BUFFER_NUM, RX_MESSAGE_BUFFER_NUM); +#if (defined(USE_CANFD) && USE_CANFD) + for (i = 0; i < DWORD_IN_MB; i++) + { + LOG_INFO("tx word%d = 0x%x\r\n", i, txFrame.dataWord[i]); + } +#else + LOG_INFO("tx word0 = 0x%x\r\n", txFrame.dataWord0); + LOG_INFO("tx word1 = 0x%x\r\n", txFrame.dataWord1); +#endif + + /* Send data through Tx Message Buffer. */ + txXfer.mbIdx = (uint8_t)TX_MESSAGE_BUFFER_NUM; +#if (defined(USE_CANFD) && USE_CANFD) + txXfer.framefd = &txFrame; + (void)FLEXCAN_TransferFDSendNonBlocking(EXAMPLE_CAN, &flexcanHandle, &txXfer); +#else + txXfer.frame = &txFrame; + (void)FLEXCAN_TransferSendNonBlocking(EXAMPLE_CAN, &flexcanHandle, &txXfer); +#endif + + /* Waiting for Rx Message finish. */ + while ((!rxComplete) || (!txComplete)) + { + }; + + LOG_INFO("\r\nReceived message from MB%d\r\n", RX_MESSAGE_BUFFER_NUM); +#if (defined(USE_CANFD) && USE_CANFD) + for (i = 0; i < DWORD_IN_MB; i++) + { + LOG_INFO("rx word%d = 0x%x\r\n", i, rxFrame.dataWord[i]); + } +#else + LOG_INFO("rx word0 = 0x%x\r\n", rxFrame.dataWord0); + LOG_INFO("rx word1 = 0x%x\r\n", rxFrame.dataWord1); +#endif + + LOG_INFO("\r\n==FlexCAN loopback example -- Finish.==\r\n"); + + while (true) + { + } +} diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_transfer/pin_mux.c b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/pin_mux.c new file mode 100644 index 000000000..5c80c431d --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/pin_mux.c @@ -0,0 +1,77 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, HYS: DISABLED, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, HYS: DISABLED, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: J17, peripheral: CAN1, signal: can_rx, pin_signal: PDM_BIT_STREAM0, HYS: DISABLED} + - {pin_num: G17, peripheral: CAN1, signal: can_tx, pin_signal: PDM_CLK, HYS: DISABLED} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_PDM_CLK__CAN1_TX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_PDM_BIT_STREAM0__CAN1_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_PDM_CLK__CAN1_TX, + IOMUXC_PAD_DSE(15U) | + IOMUXC_PAD_FSEL1(2U) | + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_PDM_BIT_STREAM0__CAN1_RX, + IOMUXC_PAD_DSE(15U) | + IOMUXC_PAD_FSEL1(2U) | + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_transfer/pin_mux.h b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/flexcan/loopback_transfer/readme.txt b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/readme.txt new file mode 100644 index 000000000..67ff1eec6 --- /dev/null +++ b/boards/som_mx93/driver_examples/flexcan/loopback_transfer/readme.txt @@ -0,0 +1,65 @@ +Overview +======== +The flexcan_loopback example shows how to use the loopback test mode to debug your CAN Bus design: + +To demonstrates this example, only one board is needed. The example will config one FlexCAN Message +Buffer to Rx Message Buffer and the other FlexCAN Message Buffer to Tx Message Buffer with same ID. +After that, the example will send a CAN Message from the Tx Message Buffer to the Rx Message Buffer +through internal loopback interconnect and print out the Message payload to terminal. + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Micro USB cable +- USB to UART Adapter +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- JLink Plus +- Proper power supply +- Personal Computer + +Board settings +============== +No special is needed. + + +Prepare the Demo +================ +1. Connect the power supply to the board and switch on the board +2. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +3. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +When the example runs successfully, following information can be seen on the terminal: + +~~~~~~~~~~~~~~~~~~~~~ + +==FlexCAN loopback functional example -- Start.== + + +Send message from MB8 to MB9 + +tx word0 = 0x11223344 + +tx word1 = 0x55667788 + + +Receved message from MB9 + +rx word0 = 0x11223344 + +rx word1 = 0x55667788 + + +==FlexCAN loopback functional example -- Finish.== +~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/CMakeLists.txt b/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/CMakeLists.txt new file mode 100644 index 000000000..9c5a01995 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/CMakeLists.txt @@ -0,0 +1,109 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(lpit_chained_channel) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME lpit_chained_channel.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../lpit_chained_channel.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/devices/MIMX9352/utilities/debug_console_lite + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(utility_debug_console_lite_MIMX9352) + +include(utility_assert_lite_MIMX9352) + +include(driver_lpit_MIMX9352) + +include(driver_clock_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_lists_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/build_all.bat b/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/build_all.bat new file mode 100644 index 000000000..1205ab083 --- /dev/null +++ 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b/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/build_all.sh new file mode 100755 index 000000000..8cc56b74f --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/build_debug.bat b/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/build_debug.sh b/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/build_release.bat b/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/build_release.sh b/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/clean.bat b/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/clean.sh b/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/config.cmake b/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/config.cmake new file mode 100755 index 000000000..920520e3d --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/flags.cmake b/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/flags.cmake new file mode 100755 index 000000000..bf4fa0ef5 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/chained_channel/armgcc/flags.cmake @@ -0,0 +1,185 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/driver_examples/lpit/chained_channel/board.c b/boards/som_mx93/driver_examples/lpit/chained_channel/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/chained_channel/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/driver_examples/lpit/chained_channel/board.h b/boards/som_mx93/driver_examples/lpit/chained_channel/board.h new file mode 100644 index 000000000..5108807ef --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/chained_channel/board.h @@ -0,0 +1,89 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + +/* ADP5585 */ +#define BOARD_ADP5585_I2C LPI2C2 +#define BOARD_ADP5585_I2C_ADDR (0x34U) +#define BOARD_ADP5585_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_ADP5585_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_ADP5585_I2C_CLOCK_ROOT) + +#define BOARD_ADP5585_PDM_MQS_SEL (2U) +#define BOARD_ADP5585_EXP_SEL (4U) +#define BOARD_ADP5585_CAN_STBY (8U) + +/* PCAL6524 */ +#define BOARD_PCAL6524_I2C LPI2C2 +#define BOARD_PCAL6524_I2C_ADDR (0x22U) +#define BOARD_PCAL6524_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_PCAL6524_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_PCAL6524_I2C_CLOCK_ROOT) + +#define BOARD_PCAL6524_ENET1_NRST (8U + 7U) +#define BOARD_PCAL6524_ENET2_NRST (16U + 0U) +#define BOARD_PCAL6524_MIC_CAN_SEL (16U + 1U) +#define BOARD_PCAL6524_EXP_SEL (16U + 6U) +#define BOARD_PCAL6524_CAN_STBY (16U + 7U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/driver_examples/lpit/chained_channel/clock_config.c b/boards/som_mx93/driver_examples/lpit/chained_channel/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/chained_channel/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/driver_examples/lpit/chained_channel/clock_config.h b/boards/som_mx93/driver_examples/lpit/chained_channel/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/chained_channel/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/driver_examples/lpit/chained_channel/lpit_chained_channel.c b/boards/som_mx93/driver_examples/lpit/chained_channel/lpit_chained_channel.c new file mode 100644 index 000000000..2de9cb4dd --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/chained_channel/lpit_chained_channel.c @@ -0,0 +1,232 @@ +/* + * Copyright 2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" + +#include "fsl_lpit.h" + +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define DEMO_LPIT_BASE LPIT1 +#define DEMO_LPIT_IRQn LPIT1_IRQn +#define DEMO_LPIT_IRQHandler LPIT1_IRQHandler +/* Get source clock for LPIT driver */ +#define LPIT_MASTER_CLOCK_ROOT kCLOCK_Root_Lpit1 +#define LPIT_SOURCECLOCK CLOCK_GetIpFreq(LPIT_MASTER_CLOCK_ROOT) +#define LED_INIT() +#define LED_TOGGLE() +#define DEMO_MAX_CHAINED_COUNTS (5U) +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +volatile bool lpitIsrFlag0 = false; +volatile bool lpitIsrFlag1 = false; +#if (defined(FSL_FEATURE_LPIT_TIMER_COUNT) && (FSL_FEATURE_LPIT_TIMER_COUNT >= 3U)) +volatile bool lpitIsrFlag2 = false; +#endif +#if (defined(FSL_FEATURE_LPIT_TIMER_COUNT) && (FSL_FEATURE_LPIT_TIMER_COUNT >= 4U)) +volatile bool lpitIsrFlag3 = false; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +void DEMO_LPIT_IRQHandler(void) +{ + uint32_t tempFlag = LPIT_GetStatusFlags(DEMO_LPIT_BASE); + + if (0U != (tempFlag & kLPIT_Channel0TimerFlag)) + { + /* Clear interrupt flag.*/ + LPIT_ClearStatusFlags(DEMO_LPIT_BASE, kLPIT_Channel0TimerFlag); + lpitIsrFlag0 = true; + } + + if (0U != (tempFlag & kLPIT_Channel1TimerFlag)) + { + /* Clear interrupt flag.*/ + LPIT_ClearStatusFlags(DEMO_LPIT_BASE, kLPIT_Channel1TimerFlag); + lpitIsrFlag1 = true; + } + +#if (defined(FSL_FEATURE_LPIT_TIMER_COUNT) && (FSL_FEATURE_LPIT_TIMER_COUNT >= 3U)) + if (0U != (tempFlag & kLPIT_Channel2TimerFlag)) + { + /* Clear interrupt flag.*/ + LPIT_ClearStatusFlags(DEMO_LPIT_BASE, kLPIT_Channel2TimerFlag); + lpitIsrFlag2 = true; + } +#endif +#if (defined(FSL_FEATURE_LPIT_TIMER_COUNT) && (FSL_FEATURE_LPIT_TIMER_COUNT >= 4U)) + if (0U != (tempFlag & kLPIT_Channel3TimerFlag)) + { + /* Clear interrupt flag.*/ + LPIT_ClearStatusFlags(DEMO_LPIT_BASE, kLPIT_Channel3TimerFlag); + lpitIsrFlag3 = true; + } +#endif + SDK_ISR_EXIT_BARRIER; +} + +/*! + * @brief Main function + */ +int main(void) +{ + /* Structure of initialize LPIT */ + lpit_config_t lpitConfig; + lpit_chnl_params_t lpitChannelConfig; + + /* Board pin, clock, debug console init */ + /* clang-format off */ + + const clock_root_config_t lpitClkCfg = { + .clockOff = false, + .mux = 0, + .div = 1 + }; + /* clang-format on */ + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + + CLOCK_SetRootClock(LPIT_MASTER_CLOCK_ROOT, &lpitClkCfg); + + /* Initialize and enable LED */ + LED_INIT(); + + /* + * lpitConfig.enableRunInDebug = false; + * lpitConfig.enableRunInDoze = false; + */ + LPIT_GetDefaultConfig(&lpitConfig); + + /* Init lpit module */ + LPIT_Init(DEMO_LPIT_BASE, &lpitConfig); + + /* SETUP 0: Configure Channel 0. */ + lpitChannelConfig.chainChannel = false; + lpitChannelConfig.enableReloadOnTrigger = false; + lpitChannelConfig.enableStartOnTrigger = false; + lpitChannelConfig.enableStopOnTimeout = false; + lpitChannelConfig.timerMode = kLPIT_PeriodicCounter; + /* Set default values for the trigger source */ + lpitChannelConfig.triggerSelect = kLPIT_Trigger_TimerChn0; + lpitChannelConfig.triggerSource = kLPIT_TriggerSource_External; + + /* Init lpit channel 0 */ + LPIT_SetupChannel(DEMO_LPIT_BASE, kLPIT_Chnl_0, &lpitChannelConfig); + + /* Set timer period for channel 0 */ + LPIT_SetTimerPeriod(DEMO_LPIT_BASE, kLPIT_Chnl_0, USEC_TO_COUNT(1000000U, LPIT_SOURCECLOCK)); + + /* SETUP 1: Configure Channel 1. */ + lpitChannelConfig.chainChannel = true; + + /* Init lpit channel 1 */ + LPIT_SetupChannel(DEMO_LPIT_BASE, kLPIT_Chnl_1, &lpitChannelConfig); + + /* Set timer period for channel 1 */ + LPIT_SetTimerPeriod(DEMO_LPIT_BASE, kLPIT_Chnl_1, DEMO_MAX_CHAINED_COUNTS); + +#if (defined(FSL_FEATURE_LPIT_TIMER_COUNT) && (FSL_FEATURE_LPIT_TIMER_COUNT >= 3U)) + /* SETUP 2: Configure Channel 2. */ + lpitChannelConfig.chainChannel = true; + + /* Init lpit channel 2 */ + LPIT_SetupChannel(DEMO_LPIT_BASE, kLPIT_Chnl_2, &lpitChannelConfig); + + /* Set timer period for channel 2 */ + LPIT_SetTimerPeriod(DEMO_LPIT_BASE, kLPIT_Chnl_2, DEMO_MAX_CHAINED_COUNTS); +#endif + +#if (defined(FSL_FEATURE_LPIT_TIMER_COUNT) && (FSL_FEATURE_LPIT_TIMER_COUNT >= 4U)) + /* SETUP 3: Configure Channel 3. */ + lpitChannelConfig.chainChannel = true; + + /* Init lpit channel 3 */ + LPIT_SetupChannel(DEMO_LPIT_BASE, kLPIT_Chnl_3, &lpitChannelConfig); + + /* Set timer period for channel 3 */ + LPIT_SetTimerPeriod(DEMO_LPIT_BASE, kLPIT_Chnl_3, DEMO_MAX_CHAINED_COUNTS); +#endif + + /* Enable timer interrupts for channel 0 and 1. */ + LPIT_EnableInterrupts(DEMO_LPIT_BASE, kLPIT_Channel0TimerInterruptEnable | kLPIT_Channel1TimerInterruptEnable); +#if (defined(FSL_FEATURE_LPIT_TIMER_COUNT) && (FSL_FEATURE_LPIT_TIMER_COUNT >= 3U)) + /* Enable timer interrupts for channel 2. */ + LPIT_EnableInterrupts(DEMO_LPIT_BASE, kLPIT_Channel2TimerInterruptEnable); +#endif +#if (defined(FSL_FEATURE_LPIT_TIMER_COUNT) && (FSL_FEATURE_LPIT_TIMER_COUNT >= 4U)) + /* Enable timer interrupts for channel 3. */ + LPIT_EnableInterrupts(DEMO_LPIT_BASE, kLPIT_Channel3TimerInterruptEnable); +#endif + + /* Enable at the NVIC */ + EnableIRQ(DEMO_LPIT_IRQn); + + /* Start channel 0 */ + PRINTF("\r\nStarting channel No.0 ..."); + LPIT_StartTimer(DEMO_LPIT_BASE, kLPIT_Chnl_0); + + /* Start channel 1 */ + PRINTF("\r\nStarting channel No.1 ..."); + LPIT_StartTimer(DEMO_LPIT_BASE, kLPIT_Chnl_1); + +#if (defined(FSL_FEATURE_LPIT_TIMER_COUNT) && (FSL_FEATURE_LPIT_TIMER_COUNT >= 3U)) + /* Start channel 2 */ + PRINTF("\r\nStarting channel No.2 ..."); + LPIT_StartTimer(DEMO_LPIT_BASE, kLPIT_Chnl_2); +#endif +#if (defined(FSL_FEATURE_LPIT_TIMER_COUNT) && (FSL_FEATURE_LPIT_TIMER_COUNT >= 4U)) + /* Start channel 3 */ + PRINTF("\r\nStarting channel No.3 ...\r\n"); + LPIT_StartTimer(DEMO_LPIT_BASE, kLPIT_Chnl_3); +#endif + + while (true) + { + /* Check whether occur interupt. */ + if (true == lpitIsrFlag0) + { + PRINTF("\r\n Channel No.0 interrupt is occurred !"); + LED_TOGGLE(); + lpitIsrFlag0 = false; + } + + if (true == lpitIsrFlag1) + { + PRINTF("\r\n\r\n Channel No.1 Chained with Channel No.0 interrupt is occurred !\r\n"); + lpitIsrFlag1 = false; + } + +#if (defined(FSL_FEATURE_LPIT_TIMER_COUNT) && (FSL_FEATURE_LPIT_TIMER_COUNT >= 3U)) + if (true == lpitIsrFlag2) + { + PRINTF("\r\n\r\n Channel No.2 Chained with Channel No.1 interrupt is occurred !\r\n"); + lpitIsrFlag2 = false; + } +#endif +#if (defined(FSL_FEATURE_LPIT_TIMER_COUNT) && (FSL_FEATURE_LPIT_TIMER_COUNT >= 4U)) + if (true == lpitIsrFlag3) + { + PRINTF("\r\n\r\n Channel No.3 Chained with Channel No.2 interrupt is occurred !\r\n"); + lpitIsrFlag3 = false; + } +#endif + } +} diff --git a/boards/som_mx93/driver_examples/lpit/chained_channel/pin_mux.c b/boards/som_mx93/driver_examples/lpit/chained_channel/pin_mux.c new file mode 100644 index 000000000..4c8d6a119 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/chained_channel/pin_mux.c @@ -0,0 +1,65 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/lpit/chained_channel/pin_mux.h b/boards/som_mx93/driver_examples/lpit/chained_channel/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/chained_channel/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/lpit/chained_channel/readme.txt b/boards/som_mx93/driver_examples/lpit/chained_channel/readme.txt new file mode 100644 index 000000000..ca9a1f191 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/chained_channel/readme.txt @@ -0,0 +1,88 @@ +Overview +======== +The LPIT chained_channel project is a simple example of the SDK LPIT driver. It sets up the LPIT +hardware block to trigger a periodic interrupt after every 1 second in the channel No.0, the channel +No.1 chained with channel No.0, if LPIT contain more than two channels, the channel No.2 chained with +channel No.1....the channel No.N chained with Channel No.N-1. +Chaining the timer channel causes them to work in a 'nested loop' manner thereby leading to an effective +timeout value up to TVALn × ((TVALn-1) + 1) at channel No.N. The timer counts down for 5 (TVALn + 1) timer +cycles until the timer reaches 0, then the timer generates an interrupt and loads the Timer Value register +(TVALn) value again. The example sets the timer period of the channel to 5 by using the API LPIT_SetTimerPeriod(). +When the LPIT interrupt is triggered a message a printed on the serial terminal. + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Micro USB cable +- USB to UART Adapter +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Proper power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + +Prepare the Demo +================ +1. Connect the power supply to the board and switch on the board. +2. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +3. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +When the example runs successfully, you will see the similar information from the terminal shown as below. +Detail prints for each channel depends on by the total numbs of chained channels and the order of +interrupt flag handler process for each channel. + +~~~~~~~~~~~~~~~~~~~~~ +Starting channel No.0 ... +Starting channel No.1 ... +Starting channel No.2 ... +Starting channel No.3 ... + + Channel No.0 interrupt is occurred ! + Channel No.0 interrupt is occurred ! + Channel No.0 interrupt is occurred ! + Channel No.0 interrupt is occurred ! + Channel No.0 interrupt is occurred ! + + Channel No.1 Chained with Channel No.0 interrupt is occurred ! +...................................... + Channel No.1 Chained with Channel No.0 interrupt is occurred ! +...................................... + Channel No.1 Chained with Channel No.0 interrupt is occurred ! +...................................... + Channel No.1 Chained with Channel No.0 interrupt is occurred ! +...................................... + Channel No.1 Chained with Channel No.0 interrupt is occurred ! + + Channel No.2 Chained with Channel No.1 interrupt is occurred ! +...................................... +...................................... + Channel No.2 Chained with Channel No.1 interrupt is occurred ! +...................................... +...................................... + Channel No.2 Chained with Channel No.1 interrupt is occurred ! +...................................... +...................................... + Channel No.2 Chained with Channel No.1 interrupt is occurred ! +...................................... +...................................... + Channel No.3 Chained with Channel No.2 interrupt is occurred ! + ..................................... + ..................................... + ..................................... + +~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/CMakeLists.txt b/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/CMakeLists.txt new file mode 100644 index 000000000..7fdb6d733 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/CMakeLists.txt @@ -0,0 +1,109 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(lpit_single_channel) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME lpit_single_channel.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../lpit_single_channel.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/devices/MIMX9352/utilities/debug_console_lite + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(utility_debug_console_lite_MIMX9352) + +include(utility_assert_lite_MIMX9352) + +include(driver_lpit_MIMX9352) + +include(driver_clock_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_lists_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/build_all.bat b/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/build_all.bat new file mode 100644 index 000000000..1205ab083 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/build_all.bat @@ -0,0 +1,15 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/build_all.sh b/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/build_all.sh new file mode 100755 index 000000000..8cc56b74f --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/build_debug.bat b/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/build_debug.sh b/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/build_release.bat b/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/build_release.sh b/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/clean.bat b/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/clean.sh b/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/config.cmake b/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/config.cmake new file mode 100755 index 000000000..920520e3d --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/flags.cmake b/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/flags.cmake new file mode 100755 index 000000000..bf4fa0ef5 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/single_channel/armgcc/flags.cmake @@ -0,0 +1,185 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/driver_examples/lpit/single_channel/board.c b/boards/som_mx93/driver_examples/lpit/single_channel/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/single_channel/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/driver_examples/lpit/single_channel/board.h b/boards/som_mx93/driver_examples/lpit/single_channel/board.h new file mode 100644 index 000000000..5108807ef --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/single_channel/board.h @@ -0,0 +1,89 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + +/* ADP5585 */ +#define BOARD_ADP5585_I2C LPI2C2 +#define BOARD_ADP5585_I2C_ADDR (0x34U) +#define BOARD_ADP5585_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_ADP5585_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_ADP5585_I2C_CLOCK_ROOT) + +#define BOARD_ADP5585_PDM_MQS_SEL (2U) +#define BOARD_ADP5585_EXP_SEL (4U) +#define BOARD_ADP5585_CAN_STBY (8U) + +/* PCAL6524 */ +#define BOARD_PCAL6524_I2C LPI2C2 +#define BOARD_PCAL6524_I2C_ADDR (0x22U) +#define BOARD_PCAL6524_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_PCAL6524_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_PCAL6524_I2C_CLOCK_ROOT) + +#define BOARD_PCAL6524_ENET1_NRST (8U + 7U) +#define BOARD_PCAL6524_ENET2_NRST (16U + 0U) +#define BOARD_PCAL6524_MIC_CAN_SEL (16U + 1U) +#define BOARD_PCAL6524_EXP_SEL (16U + 6U) +#define BOARD_PCAL6524_CAN_STBY (16U + 7U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/driver_examples/lpit/single_channel/clock_config.c b/boards/som_mx93/driver_examples/lpit/single_channel/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/single_channel/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/driver_examples/lpit/single_channel/clock_config.h b/boards/som_mx93/driver_examples/lpit/single_channel/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/single_channel/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/driver_examples/lpit/single_channel/lpit_single_channel.c b/boards/som_mx93/driver_examples/lpit/single_channel/lpit_single_channel.c new file mode 100644 index 000000000..b4ae58772 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/single_channel/lpit_single_channel.c @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" + +#include "fsl_lpit.h" + +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define DEMO_LPIT_BASE LPIT1 +#define DEMO_LPIT_IRQn LPIT1_IRQn +#define DEMO_LPIT_IRQHandler LPIT1_IRQHandler +/* Get source clock for LPIT driver */ +#define LPIT_MASTER_CLOCK_ROOT kCLOCK_Root_Lpit1 +#define LPIT_SOURCECLOCK CLOCK_GetIpFreq(LPIT_MASTER_CLOCK_ROOT) +#define LED_INIT() +#define LED_TOGGLE() + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +volatile bool lpitIsrFlag = false; + +/******************************************************************************* + * Code + ******************************************************************************/ +void DEMO_LPIT_IRQHandler(void) +{ + /* Clear interrupt flag.*/ + LPIT_ClearStatusFlags(DEMO_LPIT_BASE, kLPIT_Channel0TimerFlag); + lpitIsrFlag = true; + SDK_ISR_EXIT_BARRIER; +} + +/*! + * @brief Main function + */ +int main(void) +{ + /* Structure of initialize LPIT */ + lpit_config_t lpitConfig; + lpit_chnl_params_t lpitChannelConfig; + + /* Board pin, clock, debug console init */ + /* clang-format off */ + + const clock_root_config_t lpitClkCfg = { + .clockOff = false, + .mux = 1, + .div = 4 + }; + /* clang-format on */ + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + + CLOCK_SetRootClock(LPIT_MASTER_CLOCK_ROOT, &lpitClkCfg); + + /* Initialize and enable LED */ + LED_INIT(); + + /* + * lpitConfig.enableRunInDebug = false; + * lpitConfig.enableRunInDoze = false; + */ + LPIT_GetDefaultConfig(&lpitConfig); + + /* Init lpit module */ + LPIT_Init(DEMO_LPIT_BASE, &lpitConfig); + + lpitChannelConfig.chainChannel = false; + lpitChannelConfig.enableReloadOnTrigger = false; + lpitChannelConfig.enableStartOnTrigger = false; + lpitChannelConfig.enableStopOnTimeout = false; + lpitChannelConfig.timerMode = kLPIT_PeriodicCounter; + /* Set default values for the trigger source */ + lpitChannelConfig.triggerSelect = kLPIT_Trigger_TimerChn0; + lpitChannelConfig.triggerSource = kLPIT_TriggerSource_External; + + /* Init lpit channel 0 */ + LPIT_SetupChannel(DEMO_LPIT_BASE, kLPIT_Chnl_0, &lpitChannelConfig); + + /* Set timer period for channel 0 */ + LPIT_SetTimerPeriod(DEMO_LPIT_BASE, kLPIT_Chnl_0, USEC_TO_COUNT(1000000U, LPIT_SOURCECLOCK)); + + /* Enable timer interrupts for channel 0 */ + LPIT_EnableInterrupts(DEMO_LPIT_BASE, kLPIT_Channel0TimerInterruptEnable); + + /* Enable at the NVIC */ + EnableIRQ(DEMO_LPIT_IRQn); + + /* Start channel 0 */ + PRINTF("\r\nStarting channel No.0 ..."); + LPIT_StartTimer(DEMO_LPIT_BASE, kLPIT_Chnl_0); + + while (true) + { + /* Check whether occur interupt and toggle LED */ + if (true == lpitIsrFlag) + { + PRINTF("\r\n Channel No.0 interrupt is occurred !"); + LED_TOGGLE(); + lpitIsrFlag = false; + } + } +} diff --git a/boards/som_mx93/driver_examples/lpit/single_channel/pin_mux.c b/boards/som_mx93/driver_examples/lpit/single_channel/pin_mux.c new file mode 100644 index 000000000..4c8d6a119 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/single_channel/pin_mux.c @@ -0,0 +1,65 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/lpit/single_channel/pin_mux.h b/boards/som_mx93/driver_examples/lpit/single_channel/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/single_channel/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/lpit/single_channel/readme.txt b/boards/som_mx93/driver_examples/lpit/single_channel/readme.txt new file mode 100644 index 000000000..2f6e77916 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpit/single_channel/readme.txt @@ -0,0 +1,50 @@ +Overview +======== +The LPIT single channel project is a simple example of the SDK LPIT driver. It sets up the LPIT +hardware block to trigger a periodic interrupt after every 1 second. When the LPIT interrupt is triggered +a message a printed on the serial terminal and an LED is toggled on the board. + + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Micro USB cable +- USB to UART Adapter +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Proper power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + +Prepare the Demo +================ +1. Connect the power supply to the board and switch on the board. +2. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +3. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +When the example runs successfully, you can see similar information from the terminal as below: + +~~~~~~~~~~~~~~~~~~~~~ +Starting channel No.0 ... + Channel No.0 interrupt is occurred ! + Channel No.0 interrupt is occurred ! + Channel No.0 interrupt is occurred ! + Channel No.0 interrupt is occurred ! + Channel No.0 interrupt is occurred ! + ........................ +~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/som_mx93/driver_examples/lptmr/armgcc/CMakeLists.txt b/boards/som_mx93/driver_examples/lptmr/armgcc/CMakeLists.txt new file mode 100644 index 000000000..9f706f8b1 --- /dev/null +++ b/boards/som_mx93/driver_examples/lptmr/armgcc/CMakeLists.txt @@ -0,0 +1,109 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(lptmr) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME lptmr.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../lptmr.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/devices/MIMX9352/utilities/debug_console_lite + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(utility_debug_console_lite_MIMX9352) + +include(utility_assert_lite_MIMX9352) + +include(driver_lptmr_MIMX9352) + +include(driver_clock_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_lists_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/driver_examples/lptmr/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/driver_examples/lptmr/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/driver_examples/lptmr/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/driver_examples/lptmr/armgcc/build_all.bat b/boards/som_mx93/driver_examples/lptmr/armgcc/build_all.bat new file mode 100644 index 000000000..a16d8ae13 --- /dev/null +++ b/boards/som_mx93/driver_examples/lptmr/armgcc/build_all.bat @@ -0,0 +1,15 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/som_mx93/driver_examples/lptmr/armgcc/build_all.sh b/boards/som_mx93/driver_examples/lptmr/armgcc/build_all.sh new file mode 100755 index 000000000..253693061 --- /dev/null +++ b/boards/som_mx93/driver_examples/lptmr/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/driver_examples/lptmr/armgcc/build_debug.bat b/boards/som_mx93/driver_examples/lptmr/armgcc/build_debug.bat new file mode 100644 index 000000000..15123387e --- /dev/null +++ b/boards/som_mx93/driver_examples/lptmr/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/lptmr/armgcc/build_debug.sh b/boards/som_mx93/driver_examples/lptmr/armgcc/build_debug.sh new file mode 100755 index 000000000..42803761b --- /dev/null +++ b/boards/som_mx93/driver_examples/lptmr/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/lptmr/armgcc/build_release.bat b/boards/som_mx93/driver_examples/lptmr/armgcc/build_release.bat new file mode 100644 index 000000000..a88e3d668 --- /dev/null +++ b/boards/som_mx93/driver_examples/lptmr/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/lptmr/armgcc/build_release.sh b/boards/som_mx93/driver_examples/lptmr/armgcc/build_release.sh new file mode 100755 index 000000000..47cfb057c --- /dev/null +++ b/boards/som_mx93/driver_examples/lptmr/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/lptmr/armgcc/clean.bat b/boards/som_mx93/driver_examples/lptmr/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/driver_examples/lptmr/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/driver_examples/lptmr/armgcc/clean.sh b/boards/som_mx93/driver_examples/lptmr/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/driver_examples/lptmr/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/driver_examples/lptmr/armgcc/config.cmake b/boards/som_mx93/driver_examples/lptmr/armgcc/config.cmake new file mode 100755 index 000000000..920520e3d --- /dev/null +++ b/boards/som_mx93/driver_examples/lptmr/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/driver_examples/lptmr/armgcc/flags.cmake b/boards/som_mx93/driver_examples/lptmr/armgcc/flags.cmake new file mode 100755 index 000000000..bf4fa0ef5 --- /dev/null +++ b/boards/som_mx93/driver_examples/lptmr/armgcc/flags.cmake @@ -0,0 +1,185 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/driver_examples/lptmr/board.c b/boards/som_mx93/driver_examples/lptmr/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/lptmr/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/driver_examples/lptmr/board.h b/boards/som_mx93/driver_examples/lptmr/board.h new file mode 100644 index 000000000..5108807ef --- /dev/null +++ b/boards/som_mx93/driver_examples/lptmr/board.h @@ -0,0 +1,89 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + +/* ADP5585 */ +#define BOARD_ADP5585_I2C LPI2C2 +#define BOARD_ADP5585_I2C_ADDR (0x34U) +#define BOARD_ADP5585_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_ADP5585_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_ADP5585_I2C_CLOCK_ROOT) + +#define BOARD_ADP5585_PDM_MQS_SEL (2U) +#define BOARD_ADP5585_EXP_SEL (4U) +#define BOARD_ADP5585_CAN_STBY (8U) + +/* PCAL6524 */ +#define BOARD_PCAL6524_I2C LPI2C2 +#define BOARD_PCAL6524_I2C_ADDR (0x22U) +#define BOARD_PCAL6524_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_PCAL6524_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_PCAL6524_I2C_CLOCK_ROOT) + +#define BOARD_PCAL6524_ENET1_NRST (8U + 7U) +#define BOARD_PCAL6524_ENET2_NRST (16U + 0U) +#define BOARD_PCAL6524_MIC_CAN_SEL (16U + 1U) +#define BOARD_PCAL6524_EXP_SEL (16U + 6U) +#define BOARD_PCAL6524_CAN_STBY (16U + 7U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/driver_examples/lptmr/clock_config.c b/boards/som_mx93/driver_examples/lptmr/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/driver_examples/lptmr/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/driver_examples/lptmr/clock_config.h b/boards/som_mx93/driver_examples/lptmr/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/driver_examples/lptmr/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/driver_examples/lptmr/lptmr.c b/boards/som_mx93/driver_examples/lptmr/lptmr.c new file mode 100644 index 000000000..dceb5b0c0 --- /dev/null +++ b/boards/som_mx93/driver_examples/lptmr/lptmr.c @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" + +#include "fsl_lptmr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define DEMO_LPTMR_BASE LPTMR1 +#define DEMO_LPTMR_IRQn LPTMR1_IRQn +#define LPTMR_LED_HANDLER LPTMR1_IRQHandler +/* Get source clock for LPTMR driver */ +#define LPTMR_SOURCE_CLOCK 32000U +/* Define LPTMR microseconds counts value */ +#define LPTMR_USEC_COUNT 1000000U + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +volatile uint32_t lptmrCounter = 0U; + +/******************************************************************************* + * Code + ******************************************************************************/ +void LPTMR_LED_HANDLER(void) +{ + LPTMR_ClearStatusFlags(DEMO_LPTMR_BASE, kLPTMR_TimerCompareFlag); + lptmrCounter++; + LED_TOGGLE(); + /* + * Workaround for TWR-KV58: because write buffer is enabled, adding + * memory barrier instructions to make sure clearing interrupt flag completed + * before go out ISR + */ + __DSB(); + __ISB(); +} + +/*! + * @brief Main function + */ +int main(void) +{ + uint32_t currentCounter = 0U; + lptmr_config_t lptmrConfig; + + /* Board pin, clock, debug console init */ + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + + LED_INIT(); + + /* Configure LPTMR */ + /* + * lptmrConfig.timerMode = kLPTMR_TimerModeTimeCounter; + * lptmrConfig.pinSelect = kLPTMR_PinSelectInput_0; + * lptmrConfig.pinPolarity = kLPTMR_PinPolarityActiveHigh; + * lptmrConfig.enableFreeRunning = false; + * lptmrConfig.bypassPrescaler = true; + * lptmrConfig.prescalerClockSource = kLPTMR_PrescalerClock_1; + * lptmrConfig.value = kLPTMR_Prescale_Glitch_0; + */ + LPTMR_GetDefaultConfig(&lptmrConfig); + + /* Initialize the LPTMR */ + LPTMR_Init(DEMO_LPTMR_BASE, &lptmrConfig); + + /* + * Set timer period. + * Note : the parameter "ticks" of LPTMR_SetTimerPeriod should be equal or greater than 1. + */ + LPTMR_SetTimerPeriod(DEMO_LPTMR_BASE, USEC_TO_COUNT(LPTMR_USEC_COUNT, LPTMR_SOURCE_CLOCK)); + + /* Enable timer interrupt */ + LPTMR_EnableInterrupts(DEMO_LPTMR_BASE, kLPTMR_TimerInterruptEnable); + + /* Enable at the NVIC */ + EnableIRQ(DEMO_LPTMR_IRQn); + + PRINTF("Low Power Timer Example\r\n"); + + /* Start counting */ + LPTMR_StartTimer(DEMO_LPTMR_BASE); + while (1) + { + if (currentCounter != lptmrCounter) + { + currentCounter = lptmrCounter; + PRINTF("LPTMR interrupt No.%d \r\n", currentCounter); + } + } +} diff --git a/boards/som_mx93/driver_examples/lptmr/pin_mux.c b/boards/som_mx93/driver_examples/lptmr/pin_mux.c new file mode 100644 index 000000000..4c8d6a119 --- /dev/null +++ b/boards/som_mx93/driver_examples/lptmr/pin_mux.c @@ -0,0 +1,65 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/lptmr/pin_mux.h b/boards/som_mx93/driver_examples/lptmr/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/driver_examples/lptmr/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/lptmr/readme.txt b/boards/som_mx93/driver_examples/lptmr/readme.txt new file mode 100644 index 000000000..b611d053f --- /dev/null +++ b/boards/som_mx93/driver_examples/lptmr/readme.txt @@ -0,0 +1,47 @@ +Overview +======== +The LPTMR project is a simple demonstration program of the SDK LPTMR driver. It sets up the LPTMR +hardware block to trigger a periodic interrupt after every 1 second. When the LPTMR interrupt is triggered +a message a printed on the UART terminal. + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Micro USB cable +- USB to UART Adapter +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Proper power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + +Prepare the Demo +================ +1. Connect the power supply to the board and switch on the board. +2. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +3. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +These instructions are displayed/shown on the terminal window: +~~~~~~~~~~~~~~~~~~~~~~~~ +Low Power Timer Example +LPTMR interrupt No.1 +LPTMR interrupt No.2 +LPTMR interrupt No.3 +.................... +.................... +~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/CMakeLists.txt b/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/CMakeLists.txt new file mode 100644 index 000000000..e80f38bc8 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/CMakeLists.txt @@ -0,0 +1,107 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(lpuart_interrupt) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME lpuart_interrupt.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../lpuart_interrupt.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/devices/MIMX9352/utilities/debug_console_lite + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(utility_debug_console_lite_MIMX9352) + +include(utility_assert_lite_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(driver_clock_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_lists_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/build_all.bat b/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/build_all.bat new file mode 100644 index 000000000..1205ab083 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/build_all.bat @@ -0,0 +1,15 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/build_all.sh b/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/build_all.sh new file mode 100755 index 000000000..8cc56b74f --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/build_debug.bat b/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/build_debug.sh b/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/build_release.bat b/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/build_release.sh b/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/clean.bat b/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/clean.sh b/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/config.cmake b/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/config.cmake new file mode 100755 index 000000000..920520e3d --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/flags.cmake b/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/flags.cmake new file mode 100755 index 000000000..bf4fa0ef5 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt/armgcc/flags.cmake @@ -0,0 +1,185 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt/board.c b/boards/som_mx93/driver_examples/lpuart/interrupt/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt/board.h b/boards/som_mx93/driver_examples/lpuart/interrupt/board.h new file mode 100644 index 000000000..5108807ef --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt/board.h @@ -0,0 +1,89 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + +/* ADP5585 */ +#define BOARD_ADP5585_I2C LPI2C2 +#define BOARD_ADP5585_I2C_ADDR (0x34U) +#define BOARD_ADP5585_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_ADP5585_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_ADP5585_I2C_CLOCK_ROOT) + +#define BOARD_ADP5585_PDM_MQS_SEL (2U) +#define BOARD_ADP5585_EXP_SEL (4U) +#define BOARD_ADP5585_CAN_STBY (8U) + +/* PCAL6524 */ +#define BOARD_PCAL6524_I2C LPI2C2 +#define BOARD_PCAL6524_I2C_ADDR (0x22U) +#define BOARD_PCAL6524_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_PCAL6524_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_PCAL6524_I2C_CLOCK_ROOT) + +#define BOARD_PCAL6524_ENET1_NRST (8U + 7U) +#define BOARD_PCAL6524_ENET2_NRST (16U + 0U) +#define BOARD_PCAL6524_MIC_CAN_SEL (16U + 1U) +#define BOARD_PCAL6524_EXP_SEL (16U + 6U) +#define BOARD_PCAL6524_CAN_STBY (16U + 7U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt/clock_config.c b/boards/som_mx93/driver_examples/lpuart/interrupt/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt/clock_config.h b/boards/som_mx93/driver_examples/lpuart/interrupt/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt/lpuart_interrupt.c b/boards/som_mx93/driver_examples/lpuart/interrupt/lpuart_interrupt.c new file mode 100644 index 000000000..7e0764433 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt/lpuart_interrupt.c @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_lpuart.h" + +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Get source clock for LPIT driver */ +#define DEMO_LPUART LPUART7 +#define LPUART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define DEMO_LPUART_CLK_FREQ CLOCK_GetIpFreq(LPUART_CLOCK_ROOT) +#define DEMO_LPUART_IRQn LPUART7_IRQn +#define DEMO_LPUART_IRQHandler LPUART7_IRQHandler + +/*! @brief Ring buffer size (Unit: Byte). */ +#define DEMO_RING_BUFFER_SIZE 16 + +/*! @brief Ring buffer to save received data. */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +uint8_t g_tipString[] = + "Lpuart functional API interrupt example\r\nBoard receives characters then sends them out\r\nNow please input:\r\n"; + +/* + Ring buffer for data input and output, in this example, input data are saved + to ring buffer in IRQ handler. The main function polls the ring buffer status, + if there are new data, then send them out. + Ring buffer full: (((rxIndex + 1) % DEMO_RING_BUFFER_SIZE) == txIndex) + Ring buffer empty: (rxIndex == txIndex) +*/ +uint8_t demoRingBuffer[DEMO_RING_BUFFER_SIZE]; +volatile uint16_t txIndex; /* Index of the data to send out. */ +volatile uint16_t rxIndex; /* Index of the memory to save new arrived data. */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +void DEMO_LPUART_IRQHandler(void) +{ + uint8_t data; + uint16_t tmprxIndex = rxIndex; + uint16_t tmptxIndex = txIndex; + + /* If new data arrived. */ +#if defined(LP_FLEXCOMM_PSELID_UARTPRESENT_MASK) + if ((kLPUART_RxDataRegFullInterruptFlag)&LPUART_GetStatusFlags(DEMO_LPUART)) +#else + if ((kLPUART_RxDataRegFullFlag)&LPUART_GetStatusFlags(DEMO_LPUART)) +#endif + { + data = LPUART_ReadByte(DEMO_LPUART); + + /* If ring buffer is not full, add data to ring buffer. */ + if (((tmprxIndex + 1) % DEMO_RING_BUFFER_SIZE) != tmptxIndex) + { + demoRingBuffer[rxIndex] = data; + rxIndex++; + rxIndex %= DEMO_RING_BUFFER_SIZE; + } + } + SDK_ISR_EXIT_BARRIER; +} + +/*! + * @brief Main function + */ +int main(void) +{ + lpuart_config_t config; + uint16_t tmprxIndex = rxIndex; + uint16_t tmptxIndex = txIndex; + + /* clang-format off */ + + const clock_root_config_t lpuartClkCfg = { + .clockOff = false, + .mux = 0, + .div = 1 + }; + /* clang-format on */ + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + + CLOCK_SetRootClock(LPUART_CLOCK_ROOT, &lpuartClkCfg); + + /* + * config.baudRate_Bps = 115200U; + * config.parityMode = kLPUART_ParityDisabled; + * config.stopBitCount = kLPUART_OneStopBit; + * config.txFifoWatermark = 0; + * config.rxFifoWatermark = 0; + * config.enableTx = false; + * config.enableRx = false; + */ + LPUART_GetDefaultConfig(&config); + config.baudRate_Bps = BOARD_DEBUG_UART_BAUDRATE; + config.enableTx = true; + config.enableRx = true; + + LPUART_Init(DEMO_LPUART, &config, DEMO_LPUART_CLK_FREQ); + + /* Send g_tipString out. */ + LPUART_WriteBlocking(DEMO_LPUART, g_tipString, sizeof(g_tipString) / sizeof(g_tipString[0])); + + /* Enable RX interrupt. */ + LPUART_EnableInterrupts(DEMO_LPUART, kLPUART_RxDataRegFullInterruptEnable); + EnableIRQ(DEMO_LPUART_IRQn); + + while (1) + { + /* Send data only when LPUART TX register is empty and ring buffer has data to send out. */ +#if defined(LP_FLEXCOMM_PSELID_UARTPRESENT_MASK) + while (kLPUART_TxDataRegEmptyInterruptFlag & LPUART_GetStatusFlags(DEMO_LPUART)) +#else + while (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(DEMO_LPUART)) +#endif + { + tmprxIndex = rxIndex; + tmptxIndex = txIndex; + if (tmprxIndex != tmptxIndex) + { + LPUART_WriteByte(DEMO_LPUART, demoRingBuffer[txIndex]); + txIndex++; + txIndex %= DEMO_RING_BUFFER_SIZE; + } + } + } +} diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt/pin_mux.c b/boards/som_mx93/driver_examples/lpuart/interrupt/pin_mux.c new file mode 100644 index 000000000..4c8d6a119 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt/pin_mux.c @@ -0,0 +1,65 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt/pin_mux.h b/boards/som_mx93/driver_examples/lpuart/interrupt/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt/readme.txt b/boards/som_mx93/driver_examples/lpuart/interrupt/readme.txt new file mode 100644 index 000000000..38266a4a8 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt/readme.txt @@ -0,0 +1,49 @@ +Overview +======== +The lpuart_functioncal_interrupt example shows how to use lpuart driver functional +API to receive data with interrupt method: + +In this example, one lpuart instance connect to PC, the board will +send back all characters that PC send to the board. + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Micro USB cable +- USB to UART Adapter +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Proper power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + +Prepare the Demo +================ +1. Connect the power supply to the board and switch on the board. +2. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +3. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +When the example runs successfully, you can see the similar information from the terminal as below. + +~~~~~~~~~~~~~~~~~~~~~ +Lpuart functional API interrupt example + +Board receives characters then sends them out + +Now please input: +~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/CMakeLists.txt b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/CMakeLists.txt new file mode 100644 index 000000000..e04409963 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/CMakeLists.txt @@ -0,0 +1,107 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(lpuart_interrupt_rb_transfer) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME lpuart_interrupt_rb_transfer.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../lpuart_interrupt_rb_transfer.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/devices/MIMX9352/utilities/debug_console_lite + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(utility_debug_console_lite_MIMX9352) + +include(utility_assert_lite_MIMX9352) + +include(driver_clock_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_lists_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/build_all.bat b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/build_all.bat new file mode 100644 index 000000000..1205ab083 --- /dev/null +++ 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-j + diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/build_debug.bat b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/build_debug.sh b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/build_release.bat b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/build_release.sh b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/clean.bat b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/clean.sh b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/config.cmake b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/config.cmake new file mode 100755 index 000000000..920520e3d --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/flags.cmake b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/flags.cmake new file mode 100755 index 000000000..bf4fa0ef5 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/armgcc/flags.cmake @@ -0,0 +1,185 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/board.c b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/board.h b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/board.h new file mode 100644 index 000000000..5108807ef --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/board.h @@ -0,0 +1,89 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + +/* ADP5585 */ +#define BOARD_ADP5585_I2C LPI2C2 +#define BOARD_ADP5585_I2C_ADDR (0x34U) +#define BOARD_ADP5585_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_ADP5585_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_ADP5585_I2C_CLOCK_ROOT) + +#define BOARD_ADP5585_PDM_MQS_SEL (2U) +#define BOARD_ADP5585_EXP_SEL (4U) +#define BOARD_ADP5585_CAN_STBY (8U) + +/* PCAL6524 */ +#define BOARD_PCAL6524_I2C LPI2C2 +#define BOARD_PCAL6524_I2C_ADDR (0x22U) +#define BOARD_PCAL6524_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_PCAL6524_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_PCAL6524_I2C_CLOCK_ROOT) + +#define BOARD_PCAL6524_ENET1_NRST (8U + 7U) +#define BOARD_PCAL6524_ENET2_NRST (16U + 0U) +#define BOARD_PCAL6524_MIC_CAN_SEL (16U + 1U) +#define BOARD_PCAL6524_EXP_SEL (16U + 6U) +#define BOARD_PCAL6524_CAN_STBY (16U + 7U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/clock_config.c b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/clock_config.h b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/lpuart_interrupt_rb_transfer.c b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/lpuart_interrupt_rb_transfer.c new file mode 100644 index 000000000..0ac47cc52 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/lpuart_interrupt_rb_transfer.c @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_lpuart.h" + +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Get source clock for LPIT driver */ +#define DEMO_LPUART LPUART7 +#define LPUART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define DEMO_LPUART_CLK_FREQ CLOCK_GetIpFreq(LPUART_CLOCK_ROOT) + +#define RX_RING_BUFFER_SIZE 20U +#define ECHO_BUFFER_SIZE 8U +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/* LPUART user callback */ +void LPUART_UserCallback(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData); + +/******************************************************************************* + * Variables + ******************************************************************************/ +lpuart_handle_t g_lpuartHandle; +uint8_t g_tipString[] = "LPUART RX ring buffer example\r\nSend back received data\r\nEcho every 8 types\r\n"; +uint8_t g_rxRingBuffer[RX_RING_BUFFER_SIZE] = {0}; /* RX ring buffer. */ + +uint8_t g_rxBuffer[ECHO_BUFFER_SIZE] = {0}; /* Buffer for receive data to echo. */ +uint8_t g_txBuffer[ECHO_BUFFER_SIZE] = {0}; /* Buffer for send data to echo. */ +volatile bool rxBufferEmpty = true; +volatile bool txBufferFull = false; +volatile bool txOnGoing = false; +volatile bool rxOnGoing = false; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* LPUART user callback */ +void LPUART_UserCallback(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData) +{ + if (kStatus_LPUART_TxIdle == status) + { + txBufferFull = false; + txOnGoing = false; + } + + if (kStatus_LPUART_RxIdle == status) + { + rxBufferEmpty = false; + rxOnGoing = false; + } +} + +/*! + * @brief Main function + */ +int main(void) +{ + lpuart_config_t config; + lpuart_transfer_t xfer; + lpuart_transfer_t sendXfer; + lpuart_transfer_t receiveXfer; + size_t receivedBytes = 0U; + uint32_t i; + + /* clang-format off */ + + const clock_root_config_t lpuartClkCfg = { + .clockOff = false, + .mux = 0, + .div = 1 + }; + /* clang-format on */ + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + + CLOCK_SetRootClock(LPUART_CLOCK_ROOT, &lpuartClkCfg); + + /* + * config.baudRate_Bps = 115200U; + * config.parityMode = kLPUART_ParityDisabled; + * config.stopBitCount = kLPUART_OneStopBit; + * config.txFifoWatermark = 0; + * config.rxFifoWatermark = 0; + * config.enableTx = false; + * config.enableRx = false; + */ + LPUART_GetDefaultConfig(&config); + config.baudRate_Bps = BOARD_DEBUG_UART_BAUDRATE; + config.enableTx = true; + config.enableRx = true; + + LPUART_Init(DEMO_LPUART, &config, DEMO_LPUART_CLK_FREQ); + LPUART_TransferCreateHandle(DEMO_LPUART, &g_lpuartHandle, LPUART_UserCallback, NULL); + LPUART_TransferStartRingBuffer(DEMO_LPUART, &g_lpuartHandle, g_rxRingBuffer, RX_RING_BUFFER_SIZE); + + /* Send g_tipString out. */ + xfer.data = g_tipString; + xfer.dataSize = sizeof(g_tipString) - 1; + txOnGoing = true; + LPUART_TransferSendNonBlocking(DEMO_LPUART, &g_lpuartHandle, &xfer); + + /* Wait send finished */ + while (txOnGoing) + { + } + + /* Start to echo. */ + sendXfer.data = g_txBuffer; + sendXfer.dataSize = ECHO_BUFFER_SIZE; + receiveXfer.data = g_rxBuffer; + receiveXfer.dataSize = ECHO_BUFFER_SIZE; + + while (1) + { + /* If g_txBuffer is empty and g_rxBuffer is full, copy g_rxBuffer to g_txBuffer. */ + if ((!rxBufferEmpty) && (!txBufferFull)) + { + memcpy(g_txBuffer, g_rxBuffer, ECHO_BUFFER_SIZE); + rxBufferEmpty = true; + txBufferFull = true; + } + + /* If RX is idle and g_rxBuffer is empty, start to read data to g_rxBuffer. */ + if ((!rxOnGoing) && rxBufferEmpty) + { + rxOnGoing = true; + LPUART_TransferReceiveNonBlocking(DEMO_LPUART, &g_lpuartHandle, &receiveXfer, &receivedBytes); + if (ECHO_BUFFER_SIZE == receivedBytes) + { + rxBufferEmpty = false; + rxOnGoing = false; + } + } + + /* If TX is idle and g_txBuffer is full, start to send data. */ + if ((!txOnGoing) && txBufferFull) + { + txOnGoing = true; + LPUART_TransferSendNonBlocking(DEMO_LPUART, &g_lpuartHandle, &sendXfer); + } + + /* Delay some time, simulate the app is processing other things, input data save to ring buffer. */ + i = 0x10U; + while (i--) + { + __NOP(); + } + } +} diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/pin_mux.c b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/pin_mux.c new file mode 100644 index 000000000..4c8d6a119 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/pin_mux.c @@ -0,0 +1,65 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/pin_mux.h b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/readme.txt b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/readme.txt new file mode 100644 index 000000000..237c90256 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_rb_transfer/readme.txt @@ -0,0 +1,45 @@ +Overview +======== +The lpuart_interrupt_ring_buffer Example project is to demonstrate usage of the KSDK lpuart driver. +In the example, you can send characters to the console back and they will be printed out onto console + in a group of 8 characters. + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Micro USB cable +- USB to UART Adapter +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Proper power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + +Prepare the Demo +================ +1. Connect the power supply to the board and switch on the board. +2. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +3. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +When the example runs successfully, you can see the similar information from the terminal as below. + +~~~~~~~~~~~~~~~~~~~~~ +LPUART RX ring buffer example +Send back received data +Echo every 8 bytes +~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/CMakeLists.txt b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/CMakeLists.txt new file mode 100644 index 000000000..c028d80da --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/CMakeLists.txt @@ -0,0 +1,107 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(lpuart_interrupt_transfer) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME lpuart_interrupt_transfer.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../lpuart_interrupt_transfer.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/devices/MIMX9352/utilities/debug_console_lite + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(utility_debug_console_lite_MIMX9352) + +include(utility_assert_lite_MIMX9352) + +include(driver_clock_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_lists_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/build_all.bat b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/build_all.bat new file mode 100644 index 000000000..1205ab083 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/build_all.bat @@ -0,0 +1,15 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/build_all.sh b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/build_all.sh new file mode 100755 index 000000000..8cc56b74f --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/build_debug.bat b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/build_debug.sh b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/build_release.bat b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/build_release.sh b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/clean.bat b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/clean.sh b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/config.cmake b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/config.cmake new file mode 100755 index 000000000..920520e3d --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/flags.cmake b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/flags.cmake new file mode 100755 index 000000000..bf4fa0ef5 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/armgcc/flags.cmake @@ -0,0 +1,185 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/board.c b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/board.h b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/board.h new file mode 100644 index 000000000..5108807ef --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/board.h @@ -0,0 +1,89 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + +/* ADP5585 */ +#define BOARD_ADP5585_I2C LPI2C2 +#define BOARD_ADP5585_I2C_ADDR (0x34U) +#define BOARD_ADP5585_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_ADP5585_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_ADP5585_I2C_CLOCK_ROOT) + +#define BOARD_ADP5585_PDM_MQS_SEL (2U) +#define BOARD_ADP5585_EXP_SEL (4U) +#define BOARD_ADP5585_CAN_STBY (8U) + +/* PCAL6524 */ +#define BOARD_PCAL6524_I2C LPI2C2 +#define BOARD_PCAL6524_I2C_ADDR (0x22U) +#define BOARD_PCAL6524_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_PCAL6524_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_PCAL6524_I2C_CLOCK_ROOT) + +#define BOARD_PCAL6524_ENET1_NRST (8U + 7U) +#define BOARD_PCAL6524_ENET2_NRST (16U + 0U) +#define BOARD_PCAL6524_MIC_CAN_SEL (16U + 1U) +#define BOARD_PCAL6524_EXP_SEL (16U + 6U) +#define BOARD_PCAL6524_CAN_STBY (16U + 7U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/clock_config.c b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/clock_config.h b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/lpuart_interrupt_transfer.c b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/lpuart_interrupt_transfer.c new file mode 100644 index 000000000..864c00765 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/lpuart_interrupt_transfer.c @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_lpuart.h" + +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Get source clock for LPIT driver */ +#define DEMO_LPUART LPUART7 +#define LPUART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define DEMO_LPUART_CLK_FREQ CLOCK_GetIpFreq(LPUART_CLOCK_ROOT) +#define ECHO_BUFFER_LENGTH 8 + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/* LPUART user callback */ +void LPUART_UserCallback(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData); + +/******************************************************************************* + * Variables + ******************************************************************************/ +lpuart_handle_t g_lpuartHandle; + +uint8_t g_tipString[] = + "Lpuart interrupt example\r\nBoard receives 8 characters then sends them out\r\nNow please input:\r\n"; + +uint8_t g_txBuffer[ECHO_BUFFER_LENGTH] = {0}; +uint8_t g_rxBuffer[ECHO_BUFFER_LENGTH] = {0}; +volatile bool rxBufferEmpty = true; +volatile bool txBufferFull = false; +volatile bool txOnGoing = false; +volatile bool rxOnGoing = false; + +/******************************************************************************* + * Code + ******************************************************************************/ +/* LPUART user callback */ +void LPUART_UserCallback(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData) +{ + userData = userData; + + if (kStatus_LPUART_TxIdle == status) + { + txBufferFull = false; + txOnGoing = false; + } + + if (kStatus_LPUART_RxIdle == status) + { + rxBufferEmpty = false; + rxOnGoing = false; + } +} + +/*! + * @brief Main function + */ +int main(void) +{ + lpuart_config_t config; + lpuart_transfer_t xfer; + lpuart_transfer_t sendXfer; + lpuart_transfer_t receiveXfer; + + /* clang-format off */ + + const clock_root_config_t lpuartClkCfg = { + .clockOff = false, + .mux = 0, + .div = 1 + }; + /* clang-format on */ + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + + CLOCK_SetRootClock(LPUART_CLOCK_ROOT, &lpuartClkCfg); + + /* + * config.baudRate_Bps = 115200U; + * config.parityMode = kLPUART_ParityDisabled; + * config.stopBitCount = kLPUART_OneStopBit; + * config.txFifoWatermark = 0; + * config.rxFifoWatermark = 0; + * config.enableTx = false; + * config.enableRx = false; + */ + LPUART_GetDefaultConfig(&config); + config.baudRate_Bps = BOARD_DEBUG_UART_BAUDRATE; + config.enableTx = true; + config.enableRx = true; + + LPUART_Init(DEMO_LPUART, &config, DEMO_LPUART_CLK_FREQ); + LPUART_TransferCreateHandle(DEMO_LPUART, &g_lpuartHandle, LPUART_UserCallback, NULL); + + /* Send g_tipString out. */ + xfer.data = g_tipString; + xfer.dataSize = sizeof(g_tipString) - 1; + txOnGoing = true; + LPUART_TransferSendNonBlocking(DEMO_LPUART, &g_lpuartHandle, &xfer); + + /* Wait send finished */ + while (txOnGoing) + { + } + + /* Start to echo. */ + sendXfer.data = g_txBuffer; + sendXfer.dataSize = ECHO_BUFFER_LENGTH; + receiveXfer.data = g_rxBuffer; + receiveXfer.dataSize = ECHO_BUFFER_LENGTH; + + while (1) + { + /* If RX is idle and g_rxBuffer is empty, start to read data to g_rxBuffer. */ + if ((!rxOnGoing) && rxBufferEmpty) + { + rxOnGoing = true; + LPUART_TransferReceiveNonBlocking(DEMO_LPUART, &g_lpuartHandle, &receiveXfer, NULL); + } + + /* If TX is idle and g_txBuffer is full, start to send data. */ + if ((!txOnGoing) && txBufferFull) + { + txOnGoing = true; + LPUART_TransferSendNonBlocking(DEMO_LPUART, &g_lpuartHandle, &sendXfer); + } + + /* If g_txBuffer is empty and g_rxBuffer is full, copy g_rxBuffer to g_txBuffer. */ + if ((!rxBufferEmpty) && (!txBufferFull)) + { + memcpy(g_txBuffer, g_rxBuffer, ECHO_BUFFER_LENGTH); + rxBufferEmpty = true; + txBufferFull = true; + } + } +} diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/pin_mux.c b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/pin_mux.c new file mode 100644 index 000000000..4c8d6a119 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/pin_mux.c @@ -0,0 +1,65 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/pin_mux.h b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/readme.txt b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/readme.txt new file mode 100644 index 000000000..311acb3da --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/interrupt_transfer/readme.txt @@ -0,0 +1,45 @@ +Overview +======== +The lpuart_interrupt Example project is to demonstrate usage of the KSDK lpuart driver. +In the example, you can send characters to the console back and they will be printed out onto console + in a group of 8 characters. + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Micro USB cable +- USB to UART Adapter +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Proper power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + +Prepare the Demo +================ +1. Connect the power supply to the board and switch on the board. +2. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +3. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +When the example runs successfully, you can see the similar information from the terminal as below. + +~~~~~~~~~~~~~~~~~~~~~ +Lpuart interrupt example +Board receives 8 characters then sends them out +Now please input: +~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/som_mx93/driver_examples/lpuart/polling/armgcc/CMakeLists.txt b/boards/som_mx93/driver_examples/lpuart/polling/armgcc/CMakeLists.txt new file mode 100644 index 000000000..26db5c0c6 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/polling/armgcc/CMakeLists.txt @@ -0,0 +1,107 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(lpuart_polling) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME lpuart_polling.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../lpuart_polling.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/devices/MIMX9352/utilities/debug_console_lite + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(utility_debug_console_lite_MIMX9352) + +include(utility_assert_lite_MIMX9352) + +include(driver_clock_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_lists_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/driver_examples/lpuart/polling/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/driver_examples/lpuart/polling/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/polling/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/driver_examples/lpuart/polling/armgcc/build_all.bat b/boards/som_mx93/driver_examples/lpuart/polling/armgcc/build_all.bat new file mode 100644 index 000000000..1205ab083 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/polling/armgcc/build_all.bat @@ -0,0 +1,15 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/som_mx93/driver_examples/lpuart/polling/armgcc/build_all.sh b/boards/som_mx93/driver_examples/lpuart/polling/armgcc/build_all.sh new file mode 100755 index 000000000..8cc56b74f --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/polling/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/driver_examples/lpuart/polling/armgcc/build_debug.bat b/boards/som_mx93/driver_examples/lpuart/polling/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/polling/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/lpuart/polling/armgcc/build_debug.sh b/boards/som_mx93/driver_examples/lpuart/polling/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/polling/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/lpuart/polling/armgcc/build_release.bat b/boards/som_mx93/driver_examples/lpuart/polling/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/polling/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/lpuart/polling/armgcc/build_release.sh b/boards/som_mx93/driver_examples/lpuart/polling/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/polling/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/lpuart/polling/armgcc/clean.bat b/boards/som_mx93/driver_examples/lpuart/polling/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/polling/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/driver_examples/lpuart/polling/armgcc/clean.sh b/boards/som_mx93/driver_examples/lpuart/polling/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/polling/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/driver_examples/lpuart/polling/armgcc/config.cmake b/boards/som_mx93/driver_examples/lpuart/polling/armgcc/config.cmake new file mode 100755 index 000000000..920520e3d --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/polling/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/driver_examples/lpuart/polling/armgcc/flags.cmake b/boards/som_mx93/driver_examples/lpuart/polling/armgcc/flags.cmake new file mode 100755 index 000000000..bf4fa0ef5 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/polling/armgcc/flags.cmake @@ -0,0 +1,185 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/driver_examples/lpuart/polling/board.c b/boards/som_mx93/driver_examples/lpuart/polling/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/polling/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/driver_examples/lpuart/polling/board.h b/boards/som_mx93/driver_examples/lpuart/polling/board.h new file mode 100644 index 000000000..5108807ef --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/polling/board.h @@ -0,0 +1,89 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + +/* ADP5585 */ +#define BOARD_ADP5585_I2C LPI2C2 +#define BOARD_ADP5585_I2C_ADDR (0x34U) +#define BOARD_ADP5585_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_ADP5585_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_ADP5585_I2C_CLOCK_ROOT) + +#define BOARD_ADP5585_PDM_MQS_SEL (2U) +#define BOARD_ADP5585_EXP_SEL (4U) +#define BOARD_ADP5585_CAN_STBY (8U) + +/* PCAL6524 */ +#define BOARD_PCAL6524_I2C LPI2C2 +#define BOARD_PCAL6524_I2C_ADDR (0x22U) +#define BOARD_PCAL6524_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_PCAL6524_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_PCAL6524_I2C_CLOCK_ROOT) + +#define BOARD_PCAL6524_ENET1_NRST (8U + 7U) +#define BOARD_PCAL6524_ENET2_NRST (16U + 0U) +#define BOARD_PCAL6524_MIC_CAN_SEL (16U + 1U) +#define BOARD_PCAL6524_EXP_SEL (16U + 6U) +#define BOARD_PCAL6524_CAN_STBY (16U + 7U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/driver_examples/lpuart/polling/clock_config.c b/boards/som_mx93/driver_examples/lpuart/polling/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/polling/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/driver_examples/lpuart/polling/clock_config.h b/boards/som_mx93/driver_examples/lpuart/polling/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/polling/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/driver_examples/lpuart/polling/lpuart_polling.c b/boards/som_mx93/driver_examples/lpuart/polling/lpuart_polling.c new file mode 100644 index 000000000..54c9f09d0 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/polling/lpuart_polling.c @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_lpuart.h" + +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Get source clock for LPIT driver */ +#define DEMO_LPUART LPUART7 +#define LPUART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define DEMO_LPUART_CLK_FREQ CLOCK_GetIpFreq(LPUART_CLOCK_ROOT) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +uint8_t txbuff[] = "Lpuart polling example\r\nBoard will send back received characters\r\n"; +uint8_t rxbuff[20] = {0}; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * @brief Main function + */ +int main(void) +{ + uint8_t ch; + lpuart_config_t config; + + /* clang-format off */ + + const clock_root_config_t lpuartClkCfg = { + .clockOff = false, + .mux = 0, + .div = 1 + }; + /* clang-format on */ + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + + CLOCK_SetRootClock(LPUART_CLOCK_ROOT, &lpuartClkCfg); + + /* + * config.baudRate_Bps = 115200U; + * config.parityMode = kLPUART_ParityDisabled; + * config.stopBitCount = kLPUART_OneStopBit; + * config.txFifoWatermark = 0; + * config.rxFifoWatermark = 0; + * config.enableTx = false; + * config.enableRx = false; + */ + LPUART_GetDefaultConfig(&config); + config.baudRate_Bps = BOARD_DEBUG_UART_BAUDRATE; + config.enableTx = true; + config.enableRx = true; + + LPUART_Init(DEMO_LPUART, &config, DEMO_LPUART_CLK_FREQ); + + LPUART_WriteBlocking(DEMO_LPUART, txbuff, sizeof(txbuff) - 1); + + while (1) + { + LPUART_ReadBlocking(DEMO_LPUART, &ch, 1); + LPUART_WriteBlocking(DEMO_LPUART, &ch, 1); + } +} diff --git a/boards/som_mx93/driver_examples/lpuart/polling/pin_mux.c b/boards/som_mx93/driver_examples/lpuart/polling/pin_mux.c new file mode 100644 index 000000000..4c8d6a119 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/polling/pin_mux.c @@ -0,0 +1,65 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/lpuart/polling/pin_mux.h b/boards/som_mx93/driver_examples/lpuart/polling/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/polling/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/lpuart/polling/readme.txt b/boards/som_mx93/driver_examples/lpuart/polling/readme.txt new file mode 100644 index 000000000..127be3dd3 --- /dev/null +++ b/boards/som_mx93/driver_examples/lpuart/polling/readme.txt @@ -0,0 +1,46 @@ +Overview +======== +The lpuart_polling Example project is to demonstrate usage of the KSDK lpuart driver. +In the example, you can send characters to the console back and they will be printed out onto console + instantly. +Note: Please input one character at a time. If you input too many characters each time, the receiver may overflow +because the LPUART uses simple polling way for receiving. + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Micro USB cable +- USB to UART Adapter +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Proper power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + +Prepare the Demo +================ +1. Connect the power supply to the board and switch on the board. +2. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +3. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +When the example runs successfully, you can see the similar information from the terminal as below. + +~~~~~~~~~~~~~~~~~~~~~ +Lpuart polling example +Board will send back received characters +~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/CMakeLists.txt b/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/CMakeLists.txt new file mode 100644 index 000000000..3971cb37b --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/CMakeLists.txt @@ -0,0 +1,109 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(tpm_input_capture) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME tpm_input_capture.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../tpm_input_capture.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/devices/MIMX9352/utilities/debug_console_lite + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(utility_debug_console_lite_MIMX9352) + +include(utility_assert_lite_MIMX9352) + +include(driver_tpm_MIMX9352) + +include(driver_clock_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_lists_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/build_all.bat b/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/build_all.bat new file mode 100644 index 000000000..1205ab083 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/build_all.bat @@ -0,0 +1,15 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/build_all.sh b/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/build_all.sh new file mode 100755 index 000000000..8cc56b74f --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/build_debug.bat b/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/build_debug.sh b/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/build_release.bat b/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/build_release.sh b/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/clean.bat b/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/clean.sh b/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/config.cmake b/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/config.cmake new file mode 100755 index 000000000..920520e3d --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/flags.cmake b/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/flags.cmake new file mode 100755 index 000000000..bf4fa0ef5 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/input_capture/armgcc/flags.cmake @@ -0,0 +1,185 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/driver_examples/tpm/input_capture/board.c b/boards/som_mx93/driver_examples/tpm/input_capture/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/input_capture/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/driver_examples/tpm/input_capture/board.h b/boards/som_mx93/driver_examples/tpm/input_capture/board.h new file mode 100644 index 000000000..5108807ef --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/input_capture/board.h @@ -0,0 +1,89 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + +/* ADP5585 */ +#define BOARD_ADP5585_I2C LPI2C2 +#define BOARD_ADP5585_I2C_ADDR (0x34U) +#define BOARD_ADP5585_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_ADP5585_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_ADP5585_I2C_CLOCK_ROOT) + +#define BOARD_ADP5585_PDM_MQS_SEL (2U) +#define BOARD_ADP5585_EXP_SEL (4U) +#define BOARD_ADP5585_CAN_STBY (8U) + +/* PCAL6524 */ +#define BOARD_PCAL6524_I2C LPI2C2 +#define BOARD_PCAL6524_I2C_ADDR (0x22U) +#define BOARD_PCAL6524_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_PCAL6524_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_PCAL6524_I2C_CLOCK_ROOT) + +#define BOARD_PCAL6524_ENET1_NRST (8U + 7U) +#define BOARD_PCAL6524_ENET2_NRST (16U + 0U) +#define BOARD_PCAL6524_MIC_CAN_SEL (16U + 1U) +#define BOARD_PCAL6524_EXP_SEL (16U + 6U) +#define BOARD_PCAL6524_CAN_STBY (16U + 7U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/driver_examples/tpm/input_capture/clock_config.c b/boards/som_mx93/driver_examples/tpm/input_capture/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/input_capture/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/driver_examples/tpm/input_capture/clock_config.h b/boards/som_mx93/driver_examples/tpm/input_capture/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/input_capture/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/driver_examples/tpm/input_capture/pin_mux.c b/boards/som_mx93/driver_examples/tpm/input_capture/pin_mux.c new file mode 100644 index 000000000..2d0749a2e --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/input_capture/pin_mux.c @@ -0,0 +1,69 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, HYS: DISABLED, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, HYS: DISABLED, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + - {pin_num: W21, peripheral: TPM6, signal: 'tpm_ch, 0', pin_signal: GPIO_IO27, HYS: DISABLED, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO27__TPM6_CH3, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO27__TPM6_CH3, + IOMUXC_PAD_DSE(15U)); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/tpm/input_capture/pin_mux.h b/boards/som_mx93/driver_examples/tpm/input_capture/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/input_capture/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/tpm/input_capture/readme.txt b/boards/som_mx93/driver_examples/tpm/input_capture/readme.txt new file mode 100644 index 000000000..6dcb0a777 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/input_capture/readme.txt @@ -0,0 +1,44 @@ +Overview +======== +The TPM project is a demonstration program of the SDK TPM driver's input capture feature. +The example sets up a TPM channel for dual-edge capture. Once the input signal is received, +this example will print the capture value. + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Micro USB cable +- USB to UART Adapter +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Proper power supply +- Personal Computer + +Board settings +============== +- CM33: Connect input signal to J18-2 and J16-19(GND). + +Prepare the Demo +================ +1. Connect the power supply to the board and switch on the board. +2. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +3. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +When the example runs successfully, the following message is displayed in the terminal: + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +TPM input capture example +Once the input signal is received the input capture value is printed +Capture value C(n)V=1f61 +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/som_mx93/driver_examples/tpm/input_capture/tpm_input_capture.c b/boards/som_mx93/driver_examples/tpm/input_capture/tpm_input_capture.c new file mode 100644 index 000000000..d38bd3d6d --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/input_capture/tpm_input_capture.c @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_tpm.h" + +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* define instance */ +#define DEMO_TPM_BASEADDR TPM6 + +/* Interrupt to enable and flag to read; depends on the TPM channel used */ +#define BOARD_TPM_INPUT_CAPTURE_CHANNEL kTPM_Chnl_3 + +/* Interrupt to enable and flag to read; depends on the TPM channel used */ +#define TPM_CHANNEL_INTERRUPT_ENABLE kTPM_Chnl3InterruptEnable +#define TPM_CHANNEL_FLAG kTPM_Chnl3Flag + +/* Interrupt number and interrupt handler for the TPM instance used */ +#define TPM_INTERRUPT_NUMBER TPM6_IRQn +#define TPM_INPUT_CAPTURE_HANDLER TPM6_IRQHandler + +/* Get source clock for TPM driver */ +#define LPTPM_CLOCK_ROOT kCLOCK_Root_Tpm6 +#define TPM_SOURCE_CLOCK CLOCK_GetIpFreq(LPTPM_CLOCK_ROOT) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +volatile bool tpmIsrFlag = false; + +/******************************************************************************* + * Code + ******************************************************************************/ +void TPM_INPUT_CAPTURE_HANDLER(void) +{ + tpmIsrFlag = true; + + /* Clear interrupt flag.*/ + TPM_ClearStatusFlags(DEMO_TPM_BASEADDR, TPM_CHANNEL_FLAG); + __DSB(); +} + +/*! + * @brief Main function + */ +int main(void) +{ + tpm_config_t tpmInfo; + + /* Board pin, clock, debug console init */ + /* clang-format off */ + + const clock_root_config_t lptpmClkCfg = { + .clockOff = false, + .mux = 0, + .div = 1 + }; + /* clang-format on */ + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + + CLOCK_SetRootClock(LPTPM_CLOCK_ROOT, &lptpmClkCfg); + + /* Print a note to terminal */ + PRINTF("\r\nTPM input capture example\r\n"); + PRINTF("\r\nOnce the input signal is received the input capture value is printed\r\n"); + + TPM_GetDefaultConfig(&tpmInfo); + /* Initialize TPM module */ + TPM_Init(DEMO_TPM_BASEADDR, &tpmInfo); + + /* Setup input capture on a TPM channel */ + TPM_SetupInputCapture(DEMO_TPM_BASEADDR, BOARD_TPM_INPUT_CAPTURE_CHANNEL, kTPM_FallingEdge); + + /* Set the timer to be in free-running mode */ + TPM_SetTimerPeriod(DEMO_TPM_BASEADDR, TPM_MAX_COUNTER_VALUE(DEMO_TPM_BASEADDR)); + + /* Enable channel interrupt when the second edge is detected */ + TPM_EnableInterrupts(DEMO_TPM_BASEADDR, TPM_CHANNEL_INTERRUPT_ENABLE); + + /* Enable at the NVIC */ + EnableIRQ(TPM_INTERRUPT_NUMBER); + + TPM_StartTimer(DEMO_TPM_BASEADDR, kTPM_SystemClock); + + while (tpmIsrFlag != true) + { + } + + PRINTF("\r\nCapture value C(n)V=%x\r\n", TPM_GetChannelValue(DEMO_TPM_BASEADDR, BOARD_TPM_INPUT_CAPTURE_CHANNEL)); + while (1) + { + } +} diff --git a/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/CMakeLists.txt b/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/CMakeLists.txt new file mode 100644 index 000000000..5a3686434 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/CMakeLists.txt @@ -0,0 +1,109 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(tpm_output_compare) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME tpm_output_compare.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../tpm_output_compare.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/devices/MIMX9352/utilities/debug_console_lite + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(utility_debug_console_lite_MIMX9352) + +include(utility_assert_lite_MIMX9352) + +include(driver_tpm_MIMX9352) + +include(driver_clock_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_lists_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/build_all.bat b/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/build_all.bat new file mode 100644 index 000000000..1205ab083 --- /dev/null +++ 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b/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/build_all.sh new file mode 100755 index 000000000..8cc56b74f --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/build_debug.bat b/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/build_debug.sh b/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/build_release.bat b/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/build_release.sh b/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/clean.bat b/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/clean.sh b/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/config.cmake b/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/config.cmake new file mode 100755 index 000000000..920520e3d --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/flags.cmake b/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/flags.cmake new file mode 100755 index 000000000..bf4fa0ef5 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/output_compare/armgcc/flags.cmake @@ -0,0 +1,185 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/driver_examples/tpm/output_compare/board.c b/boards/som_mx93/driver_examples/tpm/output_compare/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/output_compare/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/driver_examples/tpm/output_compare/board.h b/boards/som_mx93/driver_examples/tpm/output_compare/board.h new file mode 100644 index 000000000..5108807ef --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/output_compare/board.h @@ -0,0 +1,89 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + +/* ADP5585 */ +#define BOARD_ADP5585_I2C LPI2C2 +#define BOARD_ADP5585_I2C_ADDR (0x34U) +#define BOARD_ADP5585_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_ADP5585_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_ADP5585_I2C_CLOCK_ROOT) + +#define BOARD_ADP5585_PDM_MQS_SEL (2U) +#define BOARD_ADP5585_EXP_SEL (4U) +#define BOARD_ADP5585_CAN_STBY (8U) + +/* PCAL6524 */ +#define BOARD_PCAL6524_I2C LPI2C2 +#define BOARD_PCAL6524_I2C_ADDR (0x22U) +#define BOARD_PCAL6524_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_PCAL6524_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_PCAL6524_I2C_CLOCK_ROOT) + +#define BOARD_PCAL6524_ENET1_NRST (8U + 7U) +#define BOARD_PCAL6524_ENET2_NRST (16U + 0U) +#define BOARD_PCAL6524_MIC_CAN_SEL (16U + 1U) +#define BOARD_PCAL6524_EXP_SEL (16U + 6U) +#define BOARD_PCAL6524_CAN_STBY (16U + 7U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/driver_examples/tpm/output_compare/clock_config.c b/boards/som_mx93/driver_examples/tpm/output_compare/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/output_compare/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/driver_examples/tpm/output_compare/clock_config.h b/boards/som_mx93/driver_examples/tpm/output_compare/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/output_compare/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/driver_examples/tpm/output_compare/pin_mux.c b/boards/som_mx93/driver_examples/tpm/output_compare/pin_mux.c new file mode 100644 index 000000000..2d0749a2e --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/output_compare/pin_mux.c @@ -0,0 +1,69 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, HYS: DISABLED, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, HYS: DISABLED, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + - {pin_num: W21, peripheral: TPM6, signal: 'tpm_ch, 0', pin_signal: GPIO_IO27, HYS: DISABLED, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO27__TPM6_CH3, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO27__TPM6_CH3, + IOMUXC_PAD_DSE(15U)); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/tpm/output_compare/pin_mux.h b/boards/som_mx93/driver_examples/tpm/output_compare/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/output_compare/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/tpm/output_compare/readme.txt b/boards/som_mx93/driver_examples/tpm/output_compare/readme.txt new file mode 100644 index 000000000..87f3bd236 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/output_compare/readme.txt @@ -0,0 +1,45 @@ +Overview +======== +The TPM project is a demonstration program of the SDK TPM driver's output compare feature. +It sets up one TPM channel to toggle the output when a match occurs with the channel value. The user +should probe the TPM output with a oscilloscope to see the signal toggling. + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Micro USB cable +- USB to UART Adapter +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Proper power supply +- Personal Computer +- Oscilloscope + +Board settings +============== +- CM33: connect J18-2 and J16-19(GND) to Oscilloscope + +Prepare the Demo +================ +1. Connect the power supply to the board and switch on the board. +2. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +3. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +When the example runs successfully, the following message is displayed in the terminal: + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +TPM example for output compare +You will see the output signal toggle +Probe the signal using an oscilloscope +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/som_mx93/driver_examples/tpm/output_compare/tpm_output_compare.c b/boards/som_mx93/driver_examples/tpm/output_compare/tpm_output_compare.c new file mode 100644 index 000000000..3e0461a58 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/output_compare/tpm_output_compare.c @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_tpm.h" + +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* define instance */ +#define DEMO_TPM_BASEADDR TPM6 +#define BOARD_TPM_OUT_CHANNEL kTPM_Chnl_3 + +/* Get source clock for TPM driver */ +#define LPTPM_CLOCK_ROOT kCLOCK_Root_Tpm6 +#define TPM_SOURCE_CLOCK CLOCK_GetIpFreq(LPTPM_CLOCK_ROOT) +#ifndef DEMO_TIMER_PERIOD_MS +/* To make led toggling visible, set default counter period to 40ms, which will make output frequency (two counter + * period) be 12.5Hz */ +#define DEMO_TIMER_PERIOD_MS (40U) +#endif +#ifndef TPM_PRESCALER_VALUE +/* Calculate the clock division based on the PWM frequency to be obtained */ +#define TPM_PRESCALER_VALUE \ + TPM_CalculateCounterClkDiv(DEMO_TPM_BASEADDR, 1000U / DEMO_TIMER_PERIOD_MS, TPM_SOURCE_CLOCK); +#endif +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * @brief Main function + */ +int main(void) +{ + tpm_config_t tpmInfo; + + /* Board pin, clock, debug console init */ + /* clang-format off */ + + const clock_root_config_t lptpmClkCfg = { + .clockOff = false, + .mux = 0, + .div = 1 + }; + /* clang-format on */ + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + + CLOCK_SetRootClock(LPTPM_CLOCK_ROOT, &lptpmClkCfg); + + /* Print a note to terminal */ + PRINTF("\r\nTPM example for output compare\r\n"); + PRINTF("\r\nYou will see the output signal toggle"); + PRINTF("\r\nProbe the signal using an oscilloscope"); + + TPM_GetDefaultConfig(&tpmInfo); + + tpmInfo.prescale = TPM_PRESCALER_VALUE; + + /* Initialize TPM module */ + TPM_Init(DEMO_TPM_BASEADDR, &tpmInfo); + + /* Setup the output compare mode to toggle output on a match, note the compare value must less than counter mod + * value */ + TPM_SetupOutputCompare(DEMO_TPM_BASEADDR, BOARD_TPM_OUT_CHANNEL, kTPM_ToggleOnMatch, + MSEC_TO_COUNT(DEMO_TIMER_PERIOD_MS, TPM_SOURCE_CLOCK / (1U << tpmInfo.prescale)) / 2U); + + /* Set the timer period */ + TPM_SetTimerPeriod(DEMO_TPM_BASEADDR, + MSEC_TO_COUNT(DEMO_TIMER_PERIOD_MS, TPM_SOURCE_CLOCK / (1U << tpmInfo.prescale))); + + TPM_StartTimer(DEMO_TPM_BASEADDR, kTPM_SystemClock); + while (1) + { + } +} diff --git a/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/CMakeLists.txt b/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/CMakeLists.txt new file mode 100644 index 000000000..ee89b03f5 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/CMakeLists.txt @@ -0,0 +1,109 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(tpm_simple_pwm) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME tpm_simple_pwm.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../tpm_simple_pwm.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/devices/MIMX9352/utilities/debug_console_lite + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(utility_debug_console_lite_MIMX9352) + +include(utility_assert_lite_MIMX9352) + +include(driver_tpm_MIMX9352) + +include(driver_clock_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_lists_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/build_all.bat b/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/build_all.bat new file mode 100644 index 000000000..1205ab083 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/build_all.bat @@ -0,0 +1,15 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/build_all.sh b/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/build_all.sh new file mode 100755 index 000000000..8cc56b74f --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/build_debug.bat b/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/build_debug.sh b/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/build_release.bat b/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/build_release.sh b/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/clean.bat b/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/clean.sh b/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/config.cmake b/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/config.cmake new file mode 100755 index 000000000..920520e3d --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/flags.cmake b/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/flags.cmake new file mode 100755 index 000000000..bf4fa0ef5 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/simple_pwm/armgcc/flags.cmake @@ -0,0 +1,185 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/driver_examples/tpm/simple_pwm/board.c b/boards/som_mx93/driver_examples/tpm/simple_pwm/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/simple_pwm/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/driver_examples/tpm/simple_pwm/board.h b/boards/som_mx93/driver_examples/tpm/simple_pwm/board.h new file mode 100644 index 000000000..5108807ef --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/simple_pwm/board.h @@ -0,0 +1,89 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + +/* ADP5585 */ +#define BOARD_ADP5585_I2C LPI2C2 +#define BOARD_ADP5585_I2C_ADDR (0x34U) +#define BOARD_ADP5585_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_ADP5585_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_ADP5585_I2C_CLOCK_ROOT) + +#define BOARD_ADP5585_PDM_MQS_SEL (2U) +#define BOARD_ADP5585_EXP_SEL (4U) +#define BOARD_ADP5585_CAN_STBY (8U) + +/* PCAL6524 */ +#define BOARD_PCAL6524_I2C LPI2C2 +#define BOARD_PCAL6524_I2C_ADDR (0x22U) +#define BOARD_PCAL6524_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_PCAL6524_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_PCAL6524_I2C_CLOCK_ROOT) + +#define BOARD_PCAL6524_ENET1_NRST (8U + 7U) +#define BOARD_PCAL6524_ENET2_NRST (16U + 0U) +#define BOARD_PCAL6524_MIC_CAN_SEL (16U + 1U) +#define BOARD_PCAL6524_EXP_SEL (16U + 6U) +#define BOARD_PCAL6524_CAN_STBY (16U + 7U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/driver_examples/tpm/simple_pwm/clock_config.c b/boards/som_mx93/driver_examples/tpm/simple_pwm/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/simple_pwm/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/driver_examples/tpm/simple_pwm/clock_config.h b/boards/som_mx93/driver_examples/tpm/simple_pwm/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/simple_pwm/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/driver_examples/tpm/simple_pwm/pin_mux.c b/boards/som_mx93/driver_examples/tpm/simple_pwm/pin_mux.c new file mode 100644 index 000000000..2d0749a2e --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/simple_pwm/pin_mux.c @@ -0,0 +1,69 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, HYS: DISABLED, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, HYS: DISABLED, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + - {pin_num: W21, peripheral: TPM6, signal: 'tpm_ch, 0', pin_signal: GPIO_IO27, HYS: DISABLED, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO27__TPM6_CH3, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO27__TPM6_CH3, + IOMUXC_PAD_DSE(15U)); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/tpm/simple_pwm/pin_mux.h b/boards/som_mx93/driver_examples/tpm/simple_pwm/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/simple_pwm/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/tpm/simple_pwm/readme.txt b/boards/som_mx93/driver_examples/tpm/simple_pwm/readme.txt new file mode 100644 index 000000000..1db374dbd --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/simple_pwm/readme.txt @@ -0,0 +1,57 @@ +Overview +======== +The TPM project is a simple demonstration program of the SDK TPM driver. It sets up the TPM +hardware block to output a center-aligned PWM signal(24kHZ). The PWM duty cycle is manually updated and is initially 10%. +On boards that have an LED connected to the TPM pins, the user will see a change in LED +brightness if user enter different values. + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Micro USB cable +- USB to UART Adapter +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Proper power supply +- Personal Computer +- Oscilloscope + +Board settings +============== +- CM33: Connect J18-2 and J16-19(GND) to Oscilloscope + +Prepare the Demo +================ +1. Connect the power supply to the board and switch on the board. +2. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +3. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +When the example runs successfully, the following message is displayed in the terminal: + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +TPM example to output center-aligned PWM signal + +If an LED is connected to the TPM pin, you will see a change in LED brightness if you enter different values +If no LED is connected to the TPM pin, then probe the signal using an oscilloscope +Please enter a value to update the Duty cycle: +Note: The range of value is 0 to 9. +For example: If enter '5', the duty cycle will be set to 50 percent. +Value:5 +The duty cycle was successfully updated! + +Please enter a value to update the Duty cycle: +Note: The range of value is 0 to 9. +For example: If enter '5', the duty cycle will be set to 50 percent. +Value: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/som_mx93/driver_examples/tpm/simple_pwm/tpm_simple_pwm.c b/boards/som_mx93/driver_examples/tpm/simple_pwm/tpm_simple_pwm.c new file mode 100644 index 000000000..5b6b497d3 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/simple_pwm/tpm_simple_pwm.c @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_tpm.h" + +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* define instance */ +#define BOARD_TPM_BASEADDR TPM6 +#define BOARD_TPM_CHANNEL kTPM_Chnl_3 + +/* Interrupt to enable and flag to read; depends on the TPM channel used */ +#define TPM_CHANNEL_INTERRUPT_ENABLE kTPM_Chnl3InterruptEnable +#define TPM_CHANNEL_FLAG kTPM_Chnl3Flag + +/* Interrupt number and interrupt handler for the TPM instance used */ +#define TPM_INTERRUPT_NUMBER TPM6_IRQn +#define TPM_LED_HANDLER TPM6_IRQHandler + +/* Get source clock for TPM driver */ +#define LPTPM_CLOCK_ROOT kCLOCK_Root_Tpm6 +#define TPM_SOURCE_CLOCK CLOCK_GetIpFreq(LPTPM_CLOCK_ROOT) +#ifndef TPM_LED_ON_LEVEL +#define TPM_LED_ON_LEVEL kTPM_HighTrue +#endif +#ifndef DEMO_PWM_FREQUENCY +#define DEMO_PWM_FREQUENCY (24000U) +#endif +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief delay a while. + */ +void delay(void); + +/******************************************************************************* + * Variables + ******************************************************************************/ +volatile bool brightnessUp = true; /* Indicate LED is brighter or dimmer */ +volatile uint8_t updatedDutycycle = 10U; +volatile uint8_t getCharValue = 0U; + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief Main function + */ +int main(void) +{ + tpm_config_t tpmInfo; + tpm_chnl_pwm_signal_param_t tpmParam; + uint8_t control; + + /* Board pin, clock, debug console init */ + /* clang-format off */ + + const clock_root_config_t lptpmClkCfg = { + .clockOff = false, + .mux = 0, + .div = 1 + }; + /* clang-format on */ + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + + CLOCK_SetRootClock(LPTPM_CLOCK_ROOT, &lptpmClkCfg); + + /* Print a note to terminal */ + PRINTF("\r\nTPM example to output center-aligned PWM signal\r\n"); + PRINTF( + "\r\nIf an LED is connected to the TPM pin, you will see a change in LED brightness if you enter different " + "values"); + PRINTF("\r\nIf no LED is connected to the TPM pin, then probe the signal using an oscilloscope"); + + /* Fill in the TPM config struct with the default settings */ + TPM_GetDefaultConfig(&tpmInfo); + /* Calculate the clock division based on the PWM frequency to be obtained */ + tpmInfo.prescale = TPM_CalculateCounterClkDiv(BOARD_TPM_BASEADDR, DEMO_PWM_FREQUENCY, TPM_SOURCE_CLOCK); + /* Initialize TPM module */ + TPM_Init(BOARD_TPM_BASEADDR, &tpmInfo); + + /* Configure tpm params with frequency 24kHZ */ + tpmParam.chnlNumber = (tpm_chnl_t)BOARD_TPM_CHANNEL; +#if (defined(FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT) && FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT) + tpmParam.pauseLevel = kTPM_ClearOnPause; +#endif + tpmParam.level = TPM_LED_ON_LEVEL; + tpmParam.dutyCyclePercent = updatedDutycycle; + if (kStatus_Success != + TPM_SetupPwm(BOARD_TPM_BASEADDR, &tpmParam, 1U, kTPM_CenterAlignedPwm, DEMO_PWM_FREQUENCY, TPM_SOURCE_CLOCK)) + { + PRINTF("\r\nSetup PWM fail!\r\n"); + return -1; + } + + TPM_StartTimer(BOARD_TPM_BASEADDR, kTPM_SystemClock); + + /* Record channel PWM mode configure */ + control = TPM_GetChannelContorlBits(BOARD_TPM_BASEADDR, (tpm_chnl_t)BOARD_TPM_CHANNEL); + while (1) + { + do + { + PRINTF("\r\nPlease enter a value to update the Duty cycle:\r\n"); + PRINTF("Note: The range of value is 0 to 9.\r\n"); + PRINTF("For example: If enter '5', the duty cycle will be set to 50 percent.\r\n"); + PRINTF("Value:"); + getCharValue = GETCHAR() - 0x30U; + PRINTF("%d", getCharValue); + PRINTF("\r\n"); + } while (getCharValue > 9U); + + updatedDutycycle = getCharValue * 10U; + + /* Disable channel output before updating the dutycycle */ + TPM_DisableChannel(BOARD_TPM_BASEADDR, (tpm_chnl_t)BOARD_TPM_CHANNEL); + + /* Update PWM duty cycle */ + if (kStatus_Success == TPM_UpdatePwmDutycycle(BOARD_TPM_BASEADDR, (tpm_chnl_t)BOARD_TPM_CHANNEL, + kTPM_CenterAlignedPwm, updatedDutycycle)) + { + PRINTF("The duty cycle was successfully updated!\r\n"); + } + + /* Start channel output with updated dutycycle */ + TPM_EnableChannel(BOARD_TPM_BASEADDR, (tpm_chnl_t)BOARD_TPM_CHANNEL, control); + } +} diff --git a/boards/som_mx93/driver_examples/tpm/timer/armgcc/CMakeLists.txt b/boards/som_mx93/driver_examples/tpm/timer/armgcc/CMakeLists.txt new file mode 100644 index 000000000..4f95e64d9 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/timer/armgcc/CMakeLists.txt @@ -0,0 +1,109 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(tpm_timer) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME tpm_timer.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../tpm_timer.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/devices/MIMX9352/utilities/debug_console_lite + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(utility_debug_console_lite_MIMX9352) + +include(utility_assert_lite_MIMX9352) + +include(driver_tpm_MIMX9352) + +include(driver_clock_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_lists_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/driver_examples/tpm/timer/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/driver_examples/tpm/timer/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/timer/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/driver_examples/tpm/timer/armgcc/build_all.bat b/boards/som_mx93/driver_examples/tpm/timer/armgcc/build_all.bat new file mode 100644 index 000000000..1205ab083 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/timer/armgcc/build_all.bat @@ -0,0 +1,15 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/som_mx93/driver_examples/tpm/timer/armgcc/build_all.sh b/boards/som_mx93/driver_examples/tpm/timer/armgcc/build_all.sh new file mode 100755 index 000000000..8cc56b74f --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/timer/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/driver_examples/tpm/timer/armgcc/build_debug.bat b/boards/som_mx93/driver_examples/tpm/timer/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/timer/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/tpm/timer/armgcc/build_debug.sh b/boards/som_mx93/driver_examples/tpm/timer/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/timer/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/tpm/timer/armgcc/build_release.bat b/boards/som_mx93/driver_examples/tpm/timer/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/timer/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/tpm/timer/armgcc/build_release.sh b/boards/som_mx93/driver_examples/tpm/timer/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/timer/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/tpm/timer/armgcc/clean.bat b/boards/som_mx93/driver_examples/tpm/timer/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/timer/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/driver_examples/tpm/timer/armgcc/clean.sh b/boards/som_mx93/driver_examples/tpm/timer/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/timer/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/driver_examples/tpm/timer/armgcc/config.cmake b/boards/som_mx93/driver_examples/tpm/timer/armgcc/config.cmake new file mode 100755 index 000000000..920520e3d --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/timer/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/driver_examples/tpm/timer/armgcc/flags.cmake b/boards/som_mx93/driver_examples/tpm/timer/armgcc/flags.cmake new file mode 100755 index 000000000..bf4fa0ef5 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/timer/armgcc/flags.cmake @@ -0,0 +1,185 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/driver_examples/tpm/timer/board.c b/boards/som_mx93/driver_examples/tpm/timer/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/timer/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/driver_examples/tpm/timer/board.h b/boards/som_mx93/driver_examples/tpm/timer/board.h new file mode 100644 index 000000000..5108807ef --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/timer/board.h @@ -0,0 +1,89 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + +/* ADP5585 */ +#define BOARD_ADP5585_I2C LPI2C2 +#define BOARD_ADP5585_I2C_ADDR (0x34U) +#define BOARD_ADP5585_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_ADP5585_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_ADP5585_I2C_CLOCK_ROOT) + +#define BOARD_ADP5585_PDM_MQS_SEL (2U) +#define BOARD_ADP5585_EXP_SEL (4U) +#define BOARD_ADP5585_CAN_STBY (8U) + +/* PCAL6524 */ +#define BOARD_PCAL6524_I2C LPI2C2 +#define BOARD_PCAL6524_I2C_ADDR (0x22U) +#define BOARD_PCAL6524_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_PCAL6524_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_PCAL6524_I2C_CLOCK_ROOT) + +#define BOARD_PCAL6524_ENET1_NRST (8U + 7U) +#define BOARD_PCAL6524_ENET2_NRST (16U + 0U) +#define BOARD_PCAL6524_MIC_CAN_SEL (16U + 1U) +#define BOARD_PCAL6524_EXP_SEL (16U + 6U) +#define BOARD_PCAL6524_CAN_STBY (16U + 7U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/driver_examples/tpm/timer/clock_config.c b/boards/som_mx93/driver_examples/tpm/timer/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/timer/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/driver_examples/tpm/timer/clock_config.h b/boards/som_mx93/driver_examples/tpm/timer/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/timer/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/driver_examples/tpm/timer/pin_mux.c b/boards/som_mx93/driver_examples/tpm/timer/pin_mux.c new file mode 100644 index 000000000..2d0749a2e --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/timer/pin_mux.c @@ -0,0 +1,69 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, HYS: DISABLED, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, HYS: DISABLED, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + - {pin_num: W21, peripheral: TPM6, signal: 'tpm_ch, 0', pin_signal: GPIO_IO27, HYS: DISABLED, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO27__TPM6_CH3, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO27__TPM6_CH3, + IOMUXC_PAD_DSE(15U)); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/tpm/timer/pin_mux.h b/boards/som_mx93/driver_examples/tpm/timer/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/timer/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/tpm/timer/readme.txt b/boards/som_mx93/driver_examples/tpm/timer/readme.txt new file mode 100644 index 000000000..d806f42bc --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/timer/readme.txt @@ -0,0 +1,45 @@ +Overview +======== +The TPM project is a simple demonstration program of the SDK TPM driver to use TPM as a timer. +It sets up the TPM hardware block to trigger an interrupt every 1 millisecond. +When the TPM interrupt is triggered 1000 times, a message is printed on the UART terminal. + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Micro USB cable +- USB to UART Adapter +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Proper power supply +- Personal Computer + +Board settings +============== +No special settings are required. + +Prepare the Demo +================ +1. Connect the power supply to the board and switch on the board. +2. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +3. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +When the example runs successfully, the following message is displayed in the terminal: + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +TPM example to simulate a timer + +You will see a "-" or "|" in terminal every 1 second: +-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|- +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/som_mx93/driver_examples/tpm/timer/tpm_timer.c b/boards/som_mx93/driver_examples/tpm/timer/tpm_timer.c new file mode 100644 index 000000000..0196503af --- /dev/null +++ b/boards/som_mx93/driver_examples/tpm/timer/tpm_timer.c @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_tpm.h" + +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* define instance */ +#define BOARD_TPM TPM6 + +/* Interrupt number and interrupt handler for the TPM instance used */ +#define BOARD_TPM_IRQ_NUM TPM6_IRQn +#define BOARD_TPM_HANDLER TPM6_IRQHandler + +/* Get source clock for TPM driver */ +#define LPTPM_CLOCK_ROOT kCLOCK_Root_Tpm6 +#define TPM_SOURCE_CLOCK CLOCK_GetIpFreq(LPTPM_CLOCK_ROOT) +#ifndef DEMO_TIMER_PERIOD_US +/* Set counter period to 1ms */ +#define DEMO_TIMER_PERIOD_US (1000U) +#endif +#ifndef TPM_PRESCALER +/* Calculate the clock division based on the PWM frequency to be obtained */ +#define TPM_PRESCALER TPM_CalculateCounterClkDiv(BOARD_TPM, 1000000U / DEMO_TIMER_PERIOD_US, TPM_SOURCE_CLOCK); +#endif +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +volatile bool tpmIsrFlag = false; +volatile uint32_t milisecondCounts = 0U; + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief Main function + */ +int main(void) +{ + uint32_t cnt; + uint32_t loop = 2; + uint32_t secondLoop = 1000U; + const char *signals = "-|"; + tpm_config_t tpmInfo; + + /* Board pin, clock, debug console init */ + /* clang-format off */ + + const clock_root_config_t lptpmClkCfg = { + .clockOff = false, + .mux = 0, + .div = 1 + }; + /* clang-format on */ + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + + CLOCK_SetRootClock(LPTPM_CLOCK_ROOT, &lptpmClkCfg); + + /* Print a note to terminal */ + PRINTF("\r\nTPM example to simulate a timer\r\n"); + + TPM_GetDefaultConfig(&tpmInfo); + + /* TPM clock divide by TPM_PRESCALER */ + tpmInfo.prescale = TPM_PRESCALER; + + /* Initialize TPM module */ + TPM_Init(BOARD_TPM, &tpmInfo); + + /* Set timer period */ + TPM_SetTimerPeriod(BOARD_TPM, USEC_TO_COUNT(DEMO_TIMER_PERIOD_US, TPM_SOURCE_CLOCK / (1U << tpmInfo.prescale))); + + TPM_EnableInterrupts(BOARD_TPM, kTPM_TimeOverflowInterruptEnable); + + EnableIRQ(BOARD_TPM_IRQ_NUM); + + PRINTF("Press any key to start timer!\r\n"); + GETCHAR(); + + PRINTF("\r\nYou will see a \"-\" or \"|\" in terminal every 1 second:\r\n"); + TPM_StartTimer(BOARD_TPM, kTPM_SystemClock); + + cnt = 0; + while (true) + { + if (tpmIsrFlag) + { + milisecondCounts++; + tpmIsrFlag = false; + if (milisecondCounts >= secondLoop) + { + PRINTF("%c", signals[cnt & 1]); + cnt++; + if (cnt >= loop) + { + cnt = 0; + } + milisecondCounts = 0U; + } + } + __WFI(); + } +} + +void BOARD_TPM_HANDLER(void) +{ + /* Clear interrupt flag.*/ + TPM_ClearStatusFlags(BOARD_TPM, kTPM_TimeOverflowFlag); + tpmIsrFlag = true; + __DSB(); +} diff --git a/boards/som_mx93/driver_examples/tstmr/armgcc/CMakeLists.txt b/boards/som_mx93/driver_examples/tstmr/armgcc/CMakeLists.txt new file mode 100644 index 000000000..8812c9e75 --- /dev/null +++ b/boards/som_mx93/driver_examples/tstmr/armgcc/CMakeLists.txt @@ -0,0 +1,109 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(tstmr) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME tstmr.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../tstmr.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/devices/MIMX9352/utilities/debug_console_lite + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(utility_debug_console_lite_MIMX9352) + +include(utility_assert_lite_MIMX9352) + +include(driver_tstmr_MIMX9352) + +include(driver_clock_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_lists_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/driver_examples/tstmr/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/driver_examples/tstmr/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/driver_examples/tstmr/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/driver_examples/tstmr/armgcc/build_all.bat b/boards/som_mx93/driver_examples/tstmr/armgcc/build_all.bat new file mode 100644 index 000000000..a16d8ae13 --- /dev/null +++ b/boards/som_mx93/driver_examples/tstmr/armgcc/build_all.bat @@ -0,0 +1,15 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/som_mx93/driver_examples/tstmr/armgcc/build_all.sh b/boards/som_mx93/driver_examples/tstmr/armgcc/build_all.sh new file mode 100755 index 000000000..253693061 --- /dev/null +++ b/boards/som_mx93/driver_examples/tstmr/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/driver_examples/tstmr/armgcc/build_debug.bat b/boards/som_mx93/driver_examples/tstmr/armgcc/build_debug.bat new file mode 100644 index 000000000..15123387e --- /dev/null +++ b/boards/som_mx93/driver_examples/tstmr/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/tstmr/armgcc/build_debug.sh b/boards/som_mx93/driver_examples/tstmr/armgcc/build_debug.sh new file mode 100755 index 000000000..42803761b --- /dev/null +++ b/boards/som_mx93/driver_examples/tstmr/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/tstmr/armgcc/build_release.bat b/boards/som_mx93/driver_examples/tstmr/armgcc/build_release.bat new file mode 100644 index 000000000..a88e3d668 --- /dev/null +++ b/boards/som_mx93/driver_examples/tstmr/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/driver_examples/tstmr/armgcc/build_release.sh b/boards/som_mx93/driver_examples/tstmr/armgcc/build_release.sh new file mode 100755 index 000000000..47cfb057c --- /dev/null +++ b/boards/som_mx93/driver_examples/tstmr/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/driver_examples/tstmr/armgcc/clean.bat b/boards/som_mx93/driver_examples/tstmr/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/driver_examples/tstmr/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/driver_examples/tstmr/armgcc/clean.sh b/boards/som_mx93/driver_examples/tstmr/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/driver_examples/tstmr/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/driver_examples/tstmr/armgcc/config.cmake b/boards/som_mx93/driver_examples/tstmr/armgcc/config.cmake new file mode 100755 index 000000000..920520e3d --- /dev/null +++ b/boards/som_mx93/driver_examples/tstmr/armgcc/config.cmake @@ -0,0 +1,2 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/driver_examples/tstmr/armgcc/flags.cmake b/boards/som_mx93/driver_examples/tstmr/armgcc/flags.cmake new file mode 100755 index 000000000..bf4fa0ef5 --- /dev/null +++ b/boards/som_mx93/driver_examples/tstmr/armgcc/flags.cmake @@ -0,0 +1,185 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/driver_examples/tstmr/board.c b/boards/som_mx93/driver_examples/tstmr/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/driver_examples/tstmr/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/driver_examples/tstmr/board.h b/boards/som_mx93/driver_examples/tstmr/board.h new file mode 100644 index 000000000..5108807ef --- /dev/null +++ b/boards/som_mx93/driver_examples/tstmr/board.h @@ -0,0 +1,89 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + +/* ADP5585 */ +#define BOARD_ADP5585_I2C LPI2C2 +#define BOARD_ADP5585_I2C_ADDR (0x34U) +#define BOARD_ADP5585_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_ADP5585_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_ADP5585_I2C_CLOCK_ROOT) + +#define BOARD_ADP5585_PDM_MQS_SEL (2U) +#define BOARD_ADP5585_EXP_SEL (4U) +#define BOARD_ADP5585_CAN_STBY (8U) + +/* PCAL6524 */ +#define BOARD_PCAL6524_I2C LPI2C2 +#define BOARD_PCAL6524_I2C_ADDR (0x22U) +#define BOARD_PCAL6524_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_PCAL6524_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_PCAL6524_I2C_CLOCK_ROOT) + +#define BOARD_PCAL6524_ENET1_NRST (8U + 7U) +#define BOARD_PCAL6524_ENET2_NRST (16U + 0U) +#define BOARD_PCAL6524_MIC_CAN_SEL (16U + 1U) +#define BOARD_PCAL6524_EXP_SEL (16U + 6U) +#define BOARD_PCAL6524_CAN_STBY (16U + 7U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/driver_examples/tstmr/clock_config.c b/boards/som_mx93/driver_examples/tstmr/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/driver_examples/tstmr/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/driver_examples/tstmr/clock_config.h b/boards/som_mx93/driver_examples/tstmr/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/driver_examples/tstmr/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/driver_examples/tstmr/pin_mux.c b/boards/som_mx93/driver_examples/tstmr/pin_mux.c new file mode 100644 index 000000000..4c8d6a119 --- /dev/null +++ b/boards/som_mx93/driver_examples/tstmr/pin_mux.c @@ -0,0 +1,65 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/tstmr/pin_mux.h b/boards/som_mx93/driver_examples/tstmr/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/driver_examples/tstmr/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/driver_examples/tstmr/readme.txt b/boards/som_mx93/driver_examples/tstmr/readme.txt new file mode 100644 index 000000000..9463ebaf7 --- /dev/null +++ b/boards/som_mx93/driver_examples/tstmr/readme.txt @@ -0,0 +1,51 @@ +Overview +======== + +The tstmr example shows the usage of TSTMR driver in application. The TSTMR module is a free running incrementing counter that starts running after system reset de-assertion and can be read at any time by the software for determining the software ticks.The TSTMR runs off the 1 MHz clock and resets on every system reset. + +In this example, it would output a time stamp information when the application is ready. And then, delay for 1 second with TSTMR_DelayUs() function. Before and after the delay, it would output the two time stamps information again. + + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Micro USB cable +- USB to UART Adapter +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Proper power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + +Prepare the Demo +================ +1. Connect the power supply to the board and switch on the board. +2. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +3. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +When the demo runs successfully, will get the similar messages on the terminal. + +~~~~~~~~~~~~~~~~~~~~~~ + Timestamp1 = 01c98d6 + + Test the delay function, delay for 1 second + + Start time = 01cb123 + + End time = 02bfbd3 +~~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/som_mx93/driver_examples/tstmr/tstmr.c b/boards/som_mx93/driver_examples/tstmr/tstmr.c new file mode 100644 index 000000000..665d73ad6 --- /dev/null +++ b/boards/som_mx93/driver_examples/tstmr/tstmr.c @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_tstmr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define EXAMPLE_TSTMR TSTMR1__TSTMRA + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief Main function + */ +int main(void) +{ + uint64_t ts; + + /* Board pin, clock, debug console init */ + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + + ts = TSTMR_ReadTimeStamp(EXAMPLE_TSTMR); + PRINTF("\r\n Timestamp1 = %x%x\r\n", (uint32_t)(ts >> 32), (uint32_t)ts); + + PRINTF("\r\n Test the delay function, delay for 1 second\r\n"); + + ts = TSTMR_ReadTimeStamp(EXAMPLE_TSTMR); + PRINTF("\r\n Start time = %x%x\r\n", (uint32_t)(ts >> 32), (uint32_t)ts); + + TSTMR_DelayUs(EXAMPLE_TSTMR, 1000000); + + ts = TSTMR_ReadTimeStamp(EXAMPLE_TSTMR); + PRINTF("\r\n End time = %x%x\r\n", (uint32_t)(ts >> 32), (uint32_t)ts); + while (1) + { + } +} diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/FreeRTOSConfig.h b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/FreeRTOSConfig.h new file mode 100644 index 000000000..a5f69d7e7 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/FreeRTOSConfig.h @@ -0,0 +1,183 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)1000) +#define configMAX_PRIORITIES 5 +#define configMINIMAL_STACK_SIZE ((unsigned short)90) +#define configMAX_TASK_NAME_LEN 10 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 + +/* Used memory allocation (heap_x.c) */ +#define configFRTOS_MEMORY_SCHEME 4 +/* Tasks.c additions (e.g. Thread Aware Debug capability) */ +#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Task aware debugging. */ +#define configRECORD_STACK_HIGH_ADDRESS 1 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY 2 +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +#define configASSERT_BOOL(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} +#define configASSERT(x) configASSERT_BOOL((x)!=0) + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_xResumeFromISR 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 1 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + + + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) + /* Clock manager provides in this variable system core clock frequency */ + #include + extern uint32_t SystemCoreClock; +#endif + + +#ifndef configENABLE_FPU + #define configENABLE_FPU 1 +#endif +#ifndef configENABLE_MPU + #define configENABLE_MPU 0 +#endif +#ifndef configENABLE_TRUSTZONE + #define configENABLE_TRUSTZONE 0 +#endif +#ifndef configRUN_FREERTOS_SECURE_ONLY + #define configRUN_FREERTOS_SECURE_ONLY 1 +#endif + +/* Redefine: Mutex is needed for SRTM communication */ +#undef configUSE_MUTEXES +#define configUSE_MUTEXES 1 + +#ifndef configTOTAL_HEAP_SIZE +#define configTOTAL_HEAP_SIZE ((size_t)(40 * 1024)) +#endif + +/* Interrupt nesting behaviour configuration. Cortex-M specific. */ +#ifdef __NVIC_PRIO_BITS +/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ +#define configPRIO_BITS __NVIC_PRIO_BITS +#else +#define configPRIO_BITS 3 /* 7 priority levels */ +#endif + +#define configSTACK_DEPTH_TYPE uint32_t + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define vPortPendSVHandler PendSV_Handler +#define vPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/CMakeLists.txt b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/CMakeLists.txt new file mode 100644 index 000000000..567840c34 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/CMakeLists.txt @@ -0,0 +1,134 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(rpmsg_lite_pingpong_rtos_linux_remote) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME rpmsg_lite_pingpong_rtos_linux_remote.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../main_remote.c" +"${ProjDirPath}/../FreeRTOSConfig.h" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../rpmsg_config.h" +"${ProjDirPath}/../rsc_table.c" +"${ProjDirPath}/../rsc_table.h" +"${ProjDirPath}/../remoteproc.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/middleware/multicore + ${SdkRootDirPath}/rtos/freertos/freertos-kernel + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/serial_manager + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(middleware_multicore_rpmsg_lite_imx93_m33_freertos_MIMX9352) + +include(middleware_multicore_rpmsg_lite_MIMX9352) + +include(middleware_multicore_rpmsg_lite_freertos_MIMX9352) + +include(middleware_freertos-kernel_heap_4_MIMX9352) + +include(middleware_freertos-kernel_cm33_nonsecure_port_MIMX9352) + +include(driver_mu1_MIMX9352) + +include(driver_clock_MIMX9352) + +include(middleware_freertos-kernel_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(utility_debug_console_MIMX9352) + +include(utility_assert_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_serial_manager_MIMX9352) + +include(component_lists_MIMX9352) + +include(component_serial_manager_uart_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(middleware_freertos-kernel_extension_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/rpmsg_lite_pingpong_rtos_linux_remote.bin) + diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..869d37655 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_all.bat b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_all.bat new file mode 100644 index 000000000..1205ab083 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_all.bat @@ -0,0 +1,15 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_all.sh b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_all.sh new file mode 100755 index 000000000..8cc56b74f --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_debug.bat b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_debug.bat new file mode 100644 index 000000000..98e3af7b8 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_debug.sh b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_debug.sh new file mode 100755 index 000000000..bc7d6e8e0 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_release.bat b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_release.bat new file mode 100644 index 000000000..1f9b96808 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_release.sh b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_release.sh new file mode 100755 index 000000000..d89c1a360 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/clean.bat b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/clean.sh b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/config.cmake b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/config.cmake new file mode 100755 index 000000000..186f296b0 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/config.cmake @@ -0,0 +1,5 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_middleware_multicore_rpmsg_lite_freertos_MIMX9352 true) +set(CONFIG_USE_component_serial_manager_uart_MIMX9352 true) +set(CONFIG_USE_driver_lpuart_MIMX9352 true) +set(CONFIG_USE_middleware_freertos-kernel_MIMX9352 true) diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/flags.cmake b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/flags.cmake new file mode 100755 index 000000000..9f42cc4ac --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/armgcc/flags.cmake @@ -0,0 +1,199 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DSDK_OS_FREE_RTOS \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DSDK_OS_FREE_RTOS \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + -Xlinker \ + --defsym=__stack_size__=0x400 \ + -Xlinker \ + --defsym=__heap_size__=0x400 \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + -Xlinker \ + --defsym=__stack_size__=0x400 \ + -Xlinker \ + --defsym=__heap_size__=0x400 \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/board.c b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/board.h b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/board.h new file mode 100644 index 000000000..5108807ef --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/board.h @@ -0,0 +1,89 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + +/* ADP5585 */ +#define BOARD_ADP5585_I2C LPI2C2 +#define BOARD_ADP5585_I2C_ADDR (0x34U) +#define BOARD_ADP5585_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_ADP5585_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_ADP5585_I2C_CLOCK_ROOT) + +#define BOARD_ADP5585_PDM_MQS_SEL (2U) +#define BOARD_ADP5585_EXP_SEL (4U) +#define BOARD_ADP5585_CAN_STBY (8U) + +/* PCAL6524 */ +#define BOARD_PCAL6524_I2C LPI2C2 +#define BOARD_PCAL6524_I2C_ADDR (0x22U) +#define BOARD_PCAL6524_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_PCAL6524_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_PCAL6524_I2C_CLOCK_ROOT) + +#define BOARD_PCAL6524_ENET1_NRST (8U + 7U) +#define BOARD_PCAL6524_ENET2_NRST (16U + 0U) +#define BOARD_PCAL6524_MIC_CAN_SEL (16U + 1U) +#define BOARD_PCAL6524_EXP_SEL (16U + 6U) +#define BOARD_PCAL6524_CAN_STBY (16U + 7U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/clock_config.c b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/clock_config.h b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/main_remote.c b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/main_remote.c new file mode 100644 index 000000000..ba8f59065 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/main_remote.c @@ -0,0 +1,216 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include "rpmsg_lite.h" +#include "rpmsg_queue.h" +#include "rpmsg_ns.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_debug_console.h" +#include "FreeRTOS.h" +#include "task.h" + +#include "rsc_table.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define RPMSG_LITE_LINK_ID (RL_PLATFORM_IMX93_M33_A55_USER_LINK_ID) +#define RPMSG_LITE_SHMEM_BASE (VDEV1_VRING_BASE) +#define RPMSG_LITE_NS_ANNOUNCE_STRING "rpmsg-openamp-demo-channel" +#define RPMSG_LITE_MASTER_IS_LINUX + +#define APP_DEBUG_UART_BAUDRATE (115200U) /* Debug console baud rate. */ +#define APP_TASK_STACK_SIZE (256U) +#ifndef LOCAL_EPT_ADDR +#define LOCAL_EPT_ADDR (30U) +#endif +#define APP_RPMSG_READY_EVENT_DATA (1U) + +typedef struct the_message +{ + uint32_t DATA; +} THE_MESSAGE, *THE_MESSAGE_PTR; + +static volatile THE_MESSAGE msg = {0}; +#ifdef RPMSG_LITE_MASTER_IS_LINUX +static char helloMsg[13]; +#endif /* RPMSG_LITE_MASTER_IS_LINUX */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +static TaskHandle_t app_task_handle = NULL; + +static struct rpmsg_lite_instance *volatile my_rpmsg = NULL; + +static struct rpmsg_lite_endpoint *volatile my_ept = NULL; +static volatile rpmsg_queue_handle my_queue = NULL; + +void app_destroy_task(void) +{ + if (app_task_handle) + { + vTaskDelete(app_task_handle); + app_task_handle = NULL; + } + + if (my_ept) + { + rpmsg_lite_destroy_ept(my_rpmsg, my_ept); + my_ept = NULL; + } + + if (my_queue) + { + rpmsg_queue_destroy(my_rpmsg, my_queue); + my_queue = NULL; + } + + if (my_rpmsg) + { + rpmsg_lite_deinit(my_rpmsg); + my_rpmsg = NULL; + } +} + +static void app_nameservice_isr_cb(uint32_t new_ept, const char *new_ept_name, uint32_t flags, void *user_data) +{ +} + +#ifdef MCMGR_USED +/*! + * @brief Application-specific implementation of the SystemInitHook() weak function. + */ +void SystemInitHook(void) +{ + /* Initialize MCMGR - low level multicore management library. Call this + function as close to the reset entry as possible to allow CoreUp event + triggering. The SystemInitHook() weak function overloading is used in this + application. */ + (void)MCMGR_EarlyInit(); +} +#endif /* MCMGR_USED */ + +static void app_task(void *param) +{ + volatile uint32_t remote_addr; + volatile rpmsg_ns_handle ns_handle; + + /* Print the initial banner */ + (void)PRINTF("\r\nRPMSG Ping-Pong FreeRTOS RTOS API Demo...\r\n"); + +#ifdef MCMGR_USED + uint32_t startupData; + mcmgr_status_t status; + + /* Get the startup data */ + do + { + status = MCMGR_GetStartupData(&startupData); + } while (status != kStatus_MCMGR_Success); + + my_rpmsg = rpmsg_lite_remote_init((void *)(char *)startupData, RPMSG_LITE_LINK_ID, RL_NO_FLAGS); + + /* Signal the other core we are ready by triggering the event and passing the APP_RPMSG_READY_EVENT_DATA */ + (void)MCMGR_TriggerEvent(kMCMGR_RemoteApplicationEvent, APP_RPMSG_READY_EVENT_DATA); +#else + (void)PRINTF("RPMSG Share Base Addr is 0x%x\r\n", RPMSG_LITE_SHMEM_BASE); + my_rpmsg = rpmsg_lite_remote_init((void *)RPMSG_LITE_SHMEM_BASE, RPMSG_LITE_LINK_ID, RL_NO_FLAGS); +#endif /* MCMGR_USED */ + rpmsg_lite_wait_for_link_up(my_rpmsg, RL_BLOCK); + (void)PRINTF("Link is up!\r\n"); + + my_queue = rpmsg_queue_create(my_rpmsg); + my_ept = rpmsg_lite_create_ept(my_rpmsg, LOCAL_EPT_ADDR, rpmsg_queue_rx_cb, my_queue); + ns_handle = rpmsg_ns_bind(my_rpmsg, app_nameservice_isr_cb, ((void *)0)); + /* Introduce some delay to avoid NS announce message not being captured by the master side. + This could happen when the remote side execution is too fast and the NS announce message is triggered + before the nameservice_isr_cb is registered on the master side. */ + SDK_DelayAtLeastUs(1000000U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + (void)rpmsg_ns_announce(my_rpmsg, my_ept, RPMSG_LITE_NS_ANNOUNCE_STRING, (uint32_t)RL_NS_CREATE); + (void)PRINTF("Nameservice announce sent.\r\n"); + +#ifdef RPMSG_LITE_MASTER_IS_LINUX + /* Wait Hello handshake message from Remote Core. */ + (void)rpmsg_queue_recv(my_rpmsg, my_queue, (uint32_t *)&remote_addr, helloMsg, sizeof(helloMsg), ((void *)0), + RL_BLOCK); +#endif /* RPMSG_LITE_MASTER_IS_LINUX */ + + while (msg.DATA <= 100U) + { + (void)PRINTF("Waiting for ping...\r\n"); + (void)rpmsg_queue_recv(my_rpmsg, my_queue, (uint32_t *)&remote_addr, (char *)&msg, sizeof(THE_MESSAGE), + ((void *)0), RL_BLOCK); + msg.DATA++; + (void)PRINTF("Sending pong...\r\n"); + (void)rpmsg_lite_send(my_rpmsg, my_ept, remote_addr, (char *)&msg, sizeof(THE_MESSAGE), RL_BLOCK); + } + + (void)PRINTF("Ping pong done, deinitializing...\r\n"); + + (void)rpmsg_lite_destroy_ept(my_rpmsg, my_ept); + my_ept = ((void *)0); + (void)rpmsg_queue_destroy(my_rpmsg, my_queue); + my_queue = ((void *)0); + (void)rpmsg_ns_unbind(my_rpmsg, ns_handle); + (void)rpmsg_lite_deinit(my_rpmsg); + my_rpmsg = ((void *)0); + msg.DATA = 0U; + + (void)PRINTF("Looping forever...\r\n"); + + /* End of the example */ + for (;;) + { + } +} + +void app_create_task(void) +{ + if (app_task_handle == NULL && + xTaskCreate(app_task, "APP_TASK", APP_TASK_STACK_SIZE, NULL, tskIDLE_PRIORITY + 1, &app_task_handle) != pdPASS) + { + PRINTF("\r\nFailed to create application task\r\n"); + for (;;) + ; + } +} + +/*! + * @brief Main function + */ +int main(void) +{ + /* Initialize standard SDK demo application pins */ + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + + /* copy resource table to destination address(TCM) */ + copyResourceTable(); + +#ifdef MCMGR_USED + /* Initialize MCMGR before calling its API */ + (void)MCMGR_Init(); +#endif /* MCMGR_USED */ + + app_create_task(); + vTaskStartScheduler(); + + (void)PRINTF("Failed to start FreeRTOS on core0.\r\n"); + for (;;) + { + } +} diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/pin_mux.c b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/pin_mux.c new file mode 100644 index 000000000..4c8d6a119 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/pin_mux.c @@ -0,0 +1,65 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/pin_mux.h b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/readme.txt b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/readme.txt new file mode 100644 index 000000000..76247af55 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/readme.txt @@ -0,0 +1,83 @@ +Overview +======== +The Multicore RPMsg-Lite pingpong RTOS project is a simple demonstration program that uses the +MCUXpresso SDK software and the RPMsg-Lite library and shows how to implement the inter-core +communicaton between cores of the multicore system. The primary core releases the secondary core +from the reset and then the inter-core communication is established. Once the RPMsg is initialized +and endpoints are created the message exchange starts, incrementing a virtual counter that is part +of the message payload. The message pingpong finishes when the counter reaches the value of 100. +Then the RPMsg-Lite is deinitialized and the procedure of the data exchange is repeated again. + +Shared memory usage +This multicore example uses the shared memory for data exchange. The shared memory region is +defined and the size can be adjustable in the linker file. The shared memory region start address +and the size have to be defined in linker file for each core equally. The shared memory start +address is then exported from the linker to the application. + +Toolchain supported +=================== +- GCC ARM Embedded 10.3.1 +- IAR embedded Workbench 9.30.1 + +Hardware requirements +===================== +- Micro USB cable +- USB to UART Adapter +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Proper power supply +- Personal Computer + +Board settings +============== +No special is needed. + +Prepare the Demo +================ +1. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). + Open two serial terminals for A Core and M Core with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control + (e.g. /dev/ttyUSB0~3, /dev/ttyUSB2 for A Core, /dev/ttyUSB3 for M Core) +2. Connect the power supply to the board and switch on the board. switch SW301 to power on the board +3. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. +4. Append "clk_ignore_unused" in u-boot "mmcargs" env, before booting linux. +5. Boot to linux. Run "echo '7 4 1 7' > /proc/sys/kernel/printk" to change the message level. +6. After login, make sure imx_rpmsg_pingpong kernel module is inserted (lsmod) or insert it (modprobe imx_rpmsg_pingpong). + +Running the demo +================ +After the boot process succeeds, the ARM Cortex-M33 terminal displays the following information: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +RPMSG Ping-Pong FreeRTOS RTOS API Demo... +RPMSG Share Base Addr is 0x87ef0000 +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +During boot the Kernel,the ARM Cortex-M33 terminal displays the following information: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Link is up! +Nameservice announce sent. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +After the Linux RPMsg pingpong module was installed, the ARM Cortex-M33 terminal displays the following information: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Waiting for ping... +Sending pong... +Waiting for ping... +Sending pong... +Waiting for ping... +Sending pong... +...... +Waiting for ping... +Sending pong... +Ping pong done, deinitializing... +Looping forever... +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +The Cortex-A terminal displays the following information: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +get 1 (src: 0x1e) +get 3 (src: 0x1e) +...... +get 99 (src: 0x1e) +get 101 (src: 0x1e) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/remoteproc.h b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/remoteproc.h new file mode 100644 index 000000000..7dad9c9eb --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/remoteproc.h @@ -0,0 +1,372 @@ +/* + * Remoteproc Framework + * + * Copyright 2020 NXP. + * Copyright(c) 2018 Xilinx Ltd. + * Copyright(c) 2011 Texas Instruments, Inc. + * Copyright(c) 2011 Google, Inc. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef REMOTEPROC_H +#define REMOTEPROC_H + +#include + +#if defined __cplusplus +extern "C" { +#endif + +#define RSC_NOTIFY_ID_ANY 0xFFFFFFFFUL + +#define RPROC_MAX_NAME_LEN 32 + +/* IAR ARM build tools */ +#if defined(__ICCARM__) + +#ifndef METAL_PACKED_BEGIN +#define METAL_PACKED_BEGIN __packed +#endif + +#ifndef METAL_PACKED_END +#define METAL_PACKED_END +#endif + +/* GNUC */ +#elif defined(__GNUC__) + +#ifndef METAL_PACKED_BEGIN +#define METAL_PACKED_BEGIN +#endif + +#ifndef METAL_PACKED_END +#define METAL_PACKED_END __attribute__((__packed__)) +#endif + +/* ARMCC */ +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) + +#ifndef METAL_PACKED_BEGIN +#define METAL_PACKED_BEGIN _Pragma("pack(1U)") +#endif + +#ifndef METAL_PACKED_END +#define METAL_PACKED_END _Pragma("pack()") +#endif + +#else +/* There is no default definition here to avoid wrong structures packing in case of not supported compiler */ +#error Please implement the structure packing macros for your compiler here! +#endif + +/** + * struct resource_table - firmware resource table header + * @ver: version number + * @num: number of resource entries + * @reserved: reserved (must be zero) + * @offset: array of offsets pointing at the various resource entries + * + * A resource table is essentially a list of system resources required + * by the remote remoteproc. It may also include configuration entries. + * If needed, the remote remoteproc firmware should contain this table + * as a dedicated ".resource_table" ELF section. + * + * Some resources entries are mere announcements, where the host is informed + * of specific remoteproc configuration. Other entries require the host to + * do something (e.g. allocate a system resource). Sometimes a negotiation + * is expected, where the firmware requests a resource, and once allocated, + * the host should provide back its details (e.g. address of an allocated + * memory region). + * + * The header of the resource table, as expressed by this structure, + * contains a version number (should we need to change this format in the + * future), the number of available resource entries, and their offsets + * in the table. + * + * Immediately following this header are the resource entries themselves, + * each of which begins with a resource entry header (as described below). + */ +METAL_PACKED_BEGIN +struct resource_table +{ + uint32_t ver; + uint32_t num; + uint32_t reserved[2]; + uint32_t offset[0]; +} METAL_PACKED_END; + +/** + * struct fw_rsc_hdr - firmware resource entry header + * @type: resource type + * @data: resource data + * + * Every resource entry begins with a 'struct fw_rsc_hdr' header providing + * its @type. The content of the entry itself will immediately follow + * this header, and it should be parsed according to the resource type. + */ +METAL_PACKED_BEGIN +struct fw_rsc_hdr +{ + uint32_t type; + uint8_t data[0]; +} METAL_PACKED_END; + +/** + * enum fw_resource_type - types of resource entries + * + * @RSC_CARVEOUT: request for allocation of a physically contiguous + * memory region. + * @RSC_DEVMEM: request to iommu_map a memory-based peripheral. + * @RSC_TRACE: announces the availability of a trace buffer into which + * the remote remoteproc will be writing logs. + * @RSC_VDEV: declare support for a virtio device, and serve as its + * virtio header. + * @RSC_VENDOR_START: start of the vendor specific resource types range + * @RSC_VENDOR_END : end of the vendor specific resource types range + * @RSC_LAST: just keep this one at the end + * + * For more details regarding a specific resource type, please see its + * dedicated structure below. + * + * Please note that these values are used as indices to the rproc_handle_rsc + * lookup table, so please keep them sane. Moreover, @RSC_LAST is used to + * check the validity of an index before the lookup table is accessed, so + * please update it as needed. + */ +enum fw_resource_type +{ + RSC_CARVEOUT = 0, + RSC_DEVMEM = 1, + RSC_TRACE = 2, + RSC_VDEV = 3, + RSC_LAST = 4, + RSC_VENDOR_START = 128, + RSC_VENDOR_END = 512, +}; + +#define FW_RSC_U64_ADDR_ANY 0xFFFFFFFFFFFFFFFFUL +#define FW_RSC_U32_ADDR_ANY 0xFFFFFFFFUL + +/** + * struct fw_rsc_carveout - physically contiguous memory request + * @da: device address + * @pa: physical address + * @len: length (in bytes) + * @flags: iommu protection flags + * @reserved: reserved (must be zero) + * @name: human-readable name of the requested memory region + * + * This resource entry requests the host to allocate a physically contiguous + * memory region. + * + * These request entries should precede other firmware resource entries, + * as other entries might request placing other data objects inside + * these memory regions (e.g. data/code segments, trace resource entries, ...). + * + * Allocating memory this way helps utilizing the reserved physical memory + * (e.g. CMA) more efficiently, and also minimizes the number of TLB entries + * needed to map it (in case @rproc is using an IOMMU). Reducing the TLB + * pressure is important; it may have a substantial impact on performance. + * + * If the firmware is compiled with static addresses, then @da should specify + * the expected device address of this memory region. If @da is set to + * FW_RSC_ADDR_ANY, then the host will dynamically allocate it, and then + * overwrite @da with the dynamically allocated address. + * + * We will always use @da to negotiate the device addresses, even if it + * isn't using an iommu. In that case, though, it will obviously contain + * physical addresses. + * + * Some remote remoteprocs needs to know the allocated physical address + * even if they do use an iommu. This is needed, e.g., if they control + * hardware accelerators which access the physical memory directly (this + * is the case with OMAP4 for instance). In that case, the host will + * overwrite @pa with the dynamically allocated physical address. + * Generally we don't want to expose physical addresses if we don't have to + * (remote remoteprocs are generally _not_ trusted), so we might want to + * change this to happen _only_ when explicitly required by the hardware. + * + * @flags is used to provide IOMMU protection flags, and @name should + * (optionally) contain a human readable name of this carveout region + * (mainly for debugging purposes). + */ +METAL_PACKED_BEGIN +struct fw_rsc_carveout +{ + uint32_t type; + uint32_t da; + uint32_t pa; + uint32_t len; + uint32_t flags; + uint32_t reserved; + uint8_t name[RPROC_MAX_NAME_LEN]; +} METAL_PACKED_END; + +/** + * struct fw_rsc_devmem - iommu mapping request + * @da: device address + * @pa: physical address + * @len: length (in bytes) + * @flags: iommu protection flags + * @reserved: reserved (must be zero) + * @name: human-readable name of the requested region to be mapped + * + * This resource entry requests the host to iommu map a physically contiguous + * memory region. This is needed in case the remote remoteproc requires + * access to certain memory-based peripherals; _never_ use it to access + * regular memory. + * + * This is obviously only needed if the remote remoteproc is accessing memory + * via an iommu. + * + * @da should specify the required device address, @pa should specify + * the physical address we want to map, @len should specify the size of + * the mapping and @flags is the IOMMU protection flags. As always, @name may + * (optionally) contain a human readable name of this mapping (mainly for + * debugging purposes). + * + * Note: at this point we just "trust" those devmem entries to contain valid + * physical addresses, but this isn't safe and will be changed: eventually we + * want remoteproc implementations to provide us ranges of physical addresses + * the firmware is allowed to request, and not allow firmwares to request + * access to physical addresses that are outside those ranges. + */ +METAL_PACKED_BEGIN +struct fw_rsc_devmem +{ + uint32_t type; + uint32_t da; + uint32_t pa; + uint32_t len; + uint32_t flags; + uint32_t reserved; + uint8_t name[RPROC_MAX_NAME_LEN]; +} METAL_PACKED_END; + +/** + * struct fw_rsc_trace - trace buffer declaration + * @da: device address + * @len: length (in bytes) + * @reserved: reserved (must be zero) + * @name: human-readable name of the trace buffer + * + * This resource entry provides the host information about a trace buffer + * into which the remote remoteproc will write log messages. + * + * @da specifies the device address of the buffer, @len specifies + * its size, and @name may contain a human readable name of the trace buffer. + * + * After booting the remote remoteproc, the trace buffers are exposed to the + * user via debugfs entries (called trace0, trace1, etc..). + */ +METAL_PACKED_BEGIN +struct fw_rsc_trace +{ + uint32_t type; + uint32_t da; + uint32_t len; + uint32_t reserved; + uint8_t name[RPROC_MAX_NAME_LEN]; +} METAL_PACKED_END; + +/** + * struct fw_rsc_vdev_vring - vring descriptor entry + * @da: device address + * @align: the alignment between the consumer and producer parts of the vring + * @num: num of buffers supported by this vring (must be power of two) + * @notifyid is a unique rproc-wide notify index for this vring. This notify + * index is used when kicking a remote remoteproc, to let it know that this + * vring is triggered. + * @reserved: reserved (must be zero) + * + * This descriptor is not a resource entry by itself; it is part of the + * vdev resource type (see below). + * + * Note that @da should either contain the device address where + * the remote remoteproc is expecting the vring, or indicate that + * dynamically allocation of the vring's device address is supported. + */ +METAL_PACKED_BEGIN +struct fw_rsc_vdev_vring +{ + uint32_t da; + uint32_t align; + uint32_t num; + uint32_t notifyid; + uint32_t reserved; +} METAL_PACKED_END; + +/** + * struct fw_rsc_vdev - virtio device header + * @id: virtio device id (as in virtio_ids.h) + * @notifyid is a unique rproc-wide notify index for this vdev. This notify + * index is used when kicking a remote remoteproc, to let it know that the + * status/features of this vdev have changes. + * @dfeatures specifies the virtio device features supported by the firmware + * @gfeatures is a place holder used by the host to write back the + * negotiated features that are supported by both sides. + * @config_len is the size of the virtio config space of this vdev. The config + * space lies in the resource table immediate after this vdev header. + * @status is a place holder where the host will indicate its virtio progress. + * @num_of_vrings indicates how many vrings are described in this vdev header + * @reserved: reserved (must be zero) + * @vring is an array of @num_of_vrings entries of 'struct fw_rsc_vdev_vring'. + * + * This resource is a virtio device header: it provides information about + * the vdev, and is then used by the host and its peer remote remoteprocs + * to negotiate and share certain virtio properties. + * + * By providing this resource entry, the firmware essentially asks remoteproc + * to statically allocate a vdev upon registration of the rproc (dynamic vdev + * allocation is not yet supported). + * + * Note: unlike virtualization systems, the term 'host' here means + * the Linux side which is running remoteproc to control the remote + * remoteprocs. We use the name 'gfeatures' to comply with virtio's terms, + * though there isn't really any virtualized guest OS here: it's the host + * which is responsible for negotiating the final features. + * Yeah, it's a bit confusing. + * + * Note: immediately following this structure is the virtio config space for + * this vdev (which is specific to the vdev; for more info, read the virtio + * spec). the size of the config space is specified by @config_len. + */ +METAL_PACKED_BEGIN +struct fw_rsc_vdev +{ + uint32_t type; + uint32_t id; + uint32_t notifyid; + uint32_t dfeatures; + uint32_t gfeatures; + uint32_t config_len; + uint8_t status; + uint8_t num_of_vrings; + uint8_t reserved[2]; + struct fw_rsc_vdev_vring vring[0]; +} METAL_PACKED_END; + +/** + * struct fw_rsc_vendor - remote processor vendor specific resource + * @len: length of the resource + * + * This resource entry tells the host the vendor specific resource + * required by the remote. + * + * These request entries should precede other shared resource entries + * such as vdevs, vrings. + */ +METAL_PACKED_BEGIN +struct fw_rsc_vendor +{ + uint32_t type; + uint32_t len; +} METAL_PACKED_END; + +#if defined __cplusplus +} +#endif + +#endif /* REMOTEPROC_H_ */ diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rpmsg_config.h b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rpmsg_config.h new file mode 100644 index 000000000..d7f0be129 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rpmsg_config.h @@ -0,0 +1,84 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RPMSG_CONFIG_H_ +#define RPMSG_CONFIG_H_ + +/*! + * @addtogroup config + * @{ + * @file + */ + +//! @name Configuration options +//@{ + +//! @def RL_MS_PER_INTERVAL +//! +//! Delay in milliseconds used in non-blocking API functions for polling. +//! The default value is 1. +#define RL_MS_PER_INTERVAL (1) + +//! @def RL_BUFFER_PAYLOAD_SIZE +//! +//! Size of the buffer payload, it must be equal to (240, 496, 1008, ...) +//! [2^n - 16]. +//! The default value is 496U. +#define RL_BUFFER_PAYLOAD_SIZE (496U) + +//! @def RL_BUFFER_COUNT +//! +//! Number of the buffers, it must be power of two (2, 4, ...). +//! The default value is 2U. +#define RL_BUFFER_COUNT (256U) + +//! @def RL_API_HAS_ZEROCOPY +//! +//! Zero-copy API functions enabled/disabled. +//! The default value is 1 (enabled). +#define RL_API_HAS_ZEROCOPY (1) + +//! @def RL_USE_STATIC_API +//! +//! Static API functions (no dynamic allocation) enabled/disabled. +//! The default value is 0 (static API disabled). +#define RL_USE_STATIC_API (0) + +//! @def RL_CLEAR_USED_BUFFERS +//! +//! Clearing used buffers before returning back to the pool of free buffers +//! enabled/disabled. +//! The default value is 0 (disabled). +#define RL_CLEAR_USED_BUFFERS (0) + +//! @def RL_USE_MCMGR_IPC_ISR_HANDLER +//! +//! When enabled IPC interrupts are managed by the Multicore Manager (IPC +//! interrupts router), when disabled RPMsg-Lite manages IPC interrupts +//! by itself. +//! The default value is 0 (no MCMGR IPC ISR handler used). +#define RL_USE_MCMGR_IPC_ISR_HANDLER (0) + +//! @def RL_USE_ENVIRONMENT_CONTEXT +//! +//! When enabled the environment layer uses its own context. +//! Added for QNX port mainly, but can be used if required. +//! The default value is 0 (no context, saves some RAM). +#define RL_USE_ENVIRONMENT_CONTEXT (0) + +//! @def RL_DEBUG_CHECK_BUFFERS +//! +//! Do not use in RPMsg-Lite to Linux configuration +#define RL_DEBUG_CHECK_BUFFERS (0) +//@} + +//! @def MU0_A_IRQHandler +//! +//! MU0_A_IRQHandler handled by application, rename the handler name in RPMsg. +#define MU0_A_IRQHandler RPMsg_MU0_A_IRQHandler + +#endif /* RPMSG_CONFIG_H_ */ diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rsc_table.c b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rsc_table.c new file mode 100644 index 000000000..18b7f56d6 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rsc_table.c @@ -0,0 +1,91 @@ +/* + * Copyright 2022 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* This file populates resource table for BM remote + * for use by the Linux Master */ + +#include +#include "board.h" +#include "rsc_table.h" +#include "rpmsg_lite.h" + +#define NUM_VRINGS 0x02 + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif +const struct remote_resource_table resources = { + /* Version */ + 1, + + /* NUmber of table entries */ + NO_RESOURCE_ENTRIES, + + /* reserved fields */ + { + 0, + 0, + }, + + /* Offsets of rsc entries */ + { + offsetof(struct remote_resource_table, srtm_vdev), + offsetof(struct remote_resource_table, user_vdev), + }, + + /* SRTM virtio device entry */ + { + RSC_VDEV, + 7, + 0, + RSC_VDEV_FEATURE_NS, + 0, + 0, + 0, + NUM_VRINGS, + {0, 0}, + }, + + /* Vring rsc entry - part of vdev rsc entry */ + {VDEV0_VRING_BASE, VRING_ALIGN, RL_BUFFER_COUNT, 0, 0}, + {VDEV0_VRING_BASE + VRING_SIZE, VRING_ALIGN, RL_BUFFER_COUNT, 1, 0}, + + /* SRTM virtio device entry */ + { + RSC_VDEV, + 7, + 1, + RSC_VDEV_FEATURE_NS, + 0, + 0, + 0, + NUM_VRINGS, + {0, 0}, + }, + + /* Vring rsc entry - part of vdev rsc entry */ + {VDEV1_VRING_BASE, VRING_ALIGN, RL_BUFFER_COUNT, 2, 0}, + {VDEV1_VRING_BASE + VRING_SIZE, VRING_ALIGN, RL_BUFFER_COUNT, 3, 0}, +}; + +void copyResourceTable(void) +{ + /* + * On startup, DDR not be enabled when M Core does resource table copy. + * Here store the resource table to a destination address + * (such as: 0x2001f000(NS)/0x3001F000(S) in TCM). + */ + memset((void *)0x2001F000U, 0, + 0x1000); /* ECC is enabled defaultly , cortex-A55 failed to read 4KB from the region when the region is not + initialized.(cortex-A55 report an ECC read error) */ + memcpy((void *)0x2001F000U, &resources, sizeof(resources)); +} diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rsc_table.h b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rsc_table.h new file mode 100644 index 000000000..efd8caefc --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_pingpong_rtos/linux_remote/rsc_table.h @@ -0,0 +1,53 @@ +/* + * Copyright 2022 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* This file populates resource table for BM remote + * for use by the Linux Master */ + +#ifndef RSC_TABLE_H_ +#define RSC_TABLE_H_ + +#include +#include + +#if defined __cplusplus +extern "C" { +#endif + +#define NO_RESOURCE_ENTRIES (2) +#define RSC_VDEV_FEATURE_NS (1) /* Support name service announcement */ + +/* Resource table for the given remote */ +METAL_PACKED_BEGIN +struct remote_resource_table +{ + uint32_t version; + uint32_t num; + uint32_t reserved[2]; + uint32_t offset[NO_RESOURCE_ENTRIES]; + + /* rpmsg vdev entry for srtm communication */ + struct fw_rsc_vdev srtm_vdev; + struct fw_rsc_vdev_vring srtm_vring0; + struct fw_rsc_vdev_vring srtm_vring1; + /* rpmsg vdev entry for user app communication */ + struct fw_rsc_vdev user_vdev; + struct fw_rsc_vdev_vring user_vring0; + struct fw_rsc_vdev_vring user_vring1; +} METAL_PACKED_END; + +/* + * Copy resource table to shared memory base for early M Core boot case. + * In M Core early boot case, Linux kernel need to get resource table before file system gets loaded. + */ +void copyResourceTable(void); + +#if defined __cplusplus +} +#endif + +#endif /* RSC_TABLE_H_ */ diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/FreeRTOSConfig.h b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/FreeRTOSConfig.h new file mode 100644 index 000000000..860d91193 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/FreeRTOSConfig.h @@ -0,0 +1,181 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)1000) +#define configMAX_PRIORITIES 5 +#define configMINIMAL_STACK_SIZE ((unsigned short)90) +#define configMAX_TASK_NAME_LEN 10 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 + +/* Used memory allocation (heap_x.c) */ +#define configFRTOS_MEMORY_SCHEME 4 +/* Tasks.c additions (e.g. Thread Aware Debug capability) */ +#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Task aware debugging. */ +#define configRECORD_STACK_HIGH_ADDRESS 1 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY 2 +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +#define configASSERT_BOOL(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} +#define configASSERT(x) configASSERT_BOOL((x)!=0) + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + + + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) + /* Clock manager provides in this variable system core clock frequency */ + #include + extern uint32_t SystemCoreClock; +#endif + + +#ifndef configENABLE_FPU + #define configENABLE_FPU 1 +#endif +#ifndef configENABLE_MPU + #define configENABLE_MPU 0 +#endif +#ifndef configENABLE_TRUSTZONE + #define configENABLE_TRUSTZONE 0 +#endif +#ifndef configRUN_FREERTOS_SECURE_ONLY + #define configRUN_FREERTOS_SECURE_ONLY 1 +#endif + +/* Redefine: Mutex is needed for SRTM communication */ +#undef configUSE_MUTEXES +#define configUSE_MUTEXES 1 + +#ifndef configTOTAL_HEAP_SIZE +#define configTOTAL_HEAP_SIZE ((size_t)(40 * 1024)) +#endif + +/* Interrupt nesting behaviour configuration. Cortex-M specific. */ +#ifdef __NVIC_PRIO_BITS +/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ +#define configPRIO_BITS __NVIC_PRIO_BITS +#else +#define configPRIO_BITS 3 /* 7 priority levels */ +#endif + +#define configSTACK_DEPTH_TYPE uint32_t + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define vPortPendSVHandler PendSV_Handler +#define vPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/CMakeLists.txt b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/CMakeLists.txt new file mode 100644 index 000000000..b140dc6b2 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/CMakeLists.txt @@ -0,0 +1,134 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(rpmsg_lite_str_echo_rtos_imxcm33) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME rpmsg_lite_str_echo_rtos_imxcm33.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../main_remote.c" +"${ProjDirPath}/../FreeRTOSConfig.h" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../rpmsg_config.h" +"${ProjDirPath}/../rsc_table.c" +"${ProjDirPath}/../rsc_table.h" +"${ProjDirPath}/../remoteproc.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/middleware/multicore + ${SdkRootDirPath}/rtos/freertos/freertos-kernel + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/serial_manager + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(middleware_multicore_rpmsg_lite_imx93_m33_freertos_MIMX9352) + +include(middleware_multicore_rpmsg_lite_MIMX9352) + +include(middleware_multicore_rpmsg_lite_freertos_MIMX9352) + +include(middleware_freertos-kernel_heap_4_MIMX9352) + +include(middleware_freertos-kernel_cm33_nonsecure_port_MIMX9352) + +include(driver_mu1_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_clock_MIMX9352) + +include(middleware_freertos-kernel_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(utility_debug_console_MIMX9352) + +include(utility_assert_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_serial_manager_MIMX9352) + +include(component_lists_MIMX9352) + +include(component_serial_manager_uart_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(middleware_freertos-kernel_extension_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/rpmsg_lite_str_echo_rtos.bin) + diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..869d37655 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_all.bat b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_all.bat new file mode 100644 index 000000000..a16d8ae13 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_all.bat @@ -0,0 +1,15 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_all.sh b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_all.sh new file mode 100755 index 000000000..253693061 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_debug.bat b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_debug.bat new file mode 100644 index 000000000..15123387e --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_debug.sh b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_debug.sh new file mode 100755 index 000000000..42803761b --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_release.bat b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_release.bat new file mode 100644 index 000000000..a88e3d668 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_release.sh b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_release.sh new file mode 100755 index 000000000..47cfb057c --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/clean.bat b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/clean.sh b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/config.cmake b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/config.cmake new file mode 100755 index 000000000..186f296b0 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/config.cmake @@ -0,0 +1,5 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_middleware_multicore_rpmsg_lite_freertos_MIMX9352 true) +set(CONFIG_USE_component_serial_manager_uart_MIMX9352 true) +set(CONFIG_USE_driver_lpuart_MIMX9352 true) +set(CONFIG_USE_middleware_freertos-kernel_MIMX9352 true) diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/flags.cmake b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/flags.cmake new file mode 100755 index 000000000..9f42cc4ac --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/armgcc/flags.cmake @@ -0,0 +1,199 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DSDK_OS_FREE_RTOS \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DSDK_OS_FREE_RTOS \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + -Xlinker \ + --defsym=__stack_size__=0x400 \ + -Xlinker \ + --defsym=__heap_size__=0x400 \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + -Xlinker \ + --defsym=__stack_size__=0x400 \ + -Xlinker \ + --defsym=__heap_size__=0x400 \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/board.c b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/board.h b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/board.h new file mode 100644 index 000000000..5108807ef --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/board.h @@ -0,0 +1,89 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + +/* ADP5585 */ +#define BOARD_ADP5585_I2C LPI2C2 +#define BOARD_ADP5585_I2C_ADDR (0x34U) +#define BOARD_ADP5585_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_ADP5585_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_ADP5585_I2C_CLOCK_ROOT) + +#define BOARD_ADP5585_PDM_MQS_SEL (2U) +#define BOARD_ADP5585_EXP_SEL (4U) +#define BOARD_ADP5585_CAN_STBY (8U) + +/* PCAL6524 */ +#define BOARD_PCAL6524_I2C LPI2C2 +#define BOARD_PCAL6524_I2C_ADDR (0x22U) +#define BOARD_PCAL6524_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_PCAL6524_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_PCAL6524_I2C_CLOCK_ROOT) + +#define BOARD_PCAL6524_ENET1_NRST (8U + 7U) +#define BOARD_PCAL6524_ENET2_NRST (16U + 0U) +#define BOARD_PCAL6524_MIC_CAN_SEL (16U + 1U) +#define BOARD_PCAL6524_EXP_SEL (16U + 6U) +#define BOARD_PCAL6524_CAN_STBY (16U + 7U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/clock_config.c b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/clock_config.h b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/main_remote.c b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/main_remote.c new file mode 100644 index 000000000..c556a1068 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/main_remote.c @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include "rpmsg_lite.h" +#include "rpmsg_queue.h" +#include "rpmsg_ns.h" +#include "pin_mux.h" +#include "board.h" +#include "fsl_debug_console.h" +#include "FreeRTOS.h" +#include "task.h" + +#include "rsc_table.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define RPMSG_LITE_LINK_ID (RL_PLATFORM_IMX93_M33_A55_USER_LINK_ID) +#define RPMSG_LITE_SHMEM_BASE (VDEV1_VRING_BASE) +#define RPMSG_LITE_NS_ANNOUNCE_STRING "rpmsg-virtual-tty-channel" +#define RPMSG_LITE_MASTER_IS_LINUX + +#define APP_DEBUG_UART_BAUDRATE (115200U) /* Debug console baud rate. */ +#define APP_TASK_STACK_SIZE (256) +#ifndef LOCAL_EPT_ADDR +#define LOCAL_EPT_ADDR (30) +#endif + +/* Globals */ +static char app_buf[512]; /* Each RPMSG buffer can carry less than 512 payload */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +static TaskHandle_t app_task_handle = NULL; + +static struct rpmsg_lite_instance *volatile my_rpmsg = NULL; + +static struct rpmsg_lite_endpoint *volatile my_ept = NULL; +static volatile rpmsg_queue_handle my_queue = NULL; +void app_destroy_task(void) +{ + if (app_task_handle) + { + vTaskDelete(app_task_handle); + app_task_handle = NULL; + } + + if (my_ept) + { + rpmsg_lite_destroy_ept(my_rpmsg, my_ept); + my_ept = NULL; + } + + if (my_queue) + { + rpmsg_queue_destroy(my_rpmsg, my_queue); + my_queue = NULL; + } + + if (my_rpmsg) + { + rpmsg_lite_deinit(my_rpmsg); + my_rpmsg = NULL; + } +} + +void app_task(void *param) +{ + volatile uint32_t remote_addr; + void *rx_buf; + uint32_t len; + int32_t result; + void *tx_buf; + uint32_t size; + + /* Print the initial banner */ + PRINTF("\r\nRPMSG String Echo FreeRTOS RTOS API Demo...\r\n"); + +#ifdef MCMGR_USED + uint32_t startupData; + + /* Get the startup data */ + (void)MCMGR_GetStartupData(kMCMGR_Core1, &startupData); + + my_rpmsg = rpmsg_lite_remote_init((void *)startupData, RPMSG_LITE_LINK_ID, RL_NO_FLAGS); + + /* Signal the other core we are ready */ + (void)MCMGR_SignalReady(kMCMGR_Core1); +#else + my_rpmsg = rpmsg_lite_remote_init((void *)RPMSG_LITE_SHMEM_BASE, RPMSG_LITE_LINK_ID, RL_NO_FLAGS); +#endif /* MCMGR_USED */ + + rpmsg_lite_wait_for_link_up(my_rpmsg, RL_BLOCK); + + my_queue = rpmsg_queue_create(my_rpmsg); + my_ept = rpmsg_lite_create_ept(my_rpmsg, LOCAL_EPT_ADDR, rpmsg_queue_rx_cb, my_queue); + (void)rpmsg_ns_announce(my_rpmsg, my_ept, RPMSG_LITE_NS_ANNOUNCE_STRING, RL_NS_CREATE); + + PRINTF("\r\nNameservice sent, ready for incoming messages...\r\n"); + + for (;;) + { + /* Get RPMsg rx buffer with message */ + result = + rpmsg_queue_recv_nocopy(my_rpmsg, my_queue, (uint32_t *)&remote_addr, (char **)&rx_buf, &len, RL_BLOCK); + if (result != 0) + { + assert(false); + } + + /* Copy string from RPMsg rx buffer */ + assert(len < sizeof(app_buf)); + memcpy(app_buf, rx_buf, len); + app_buf[len] = 0; /* End string by '\0' */ + + if ((len == 2) && (app_buf[0] == 0xd) && (app_buf[1] == 0xa)) + PRINTF("Get New Line From Master Side\r\n"); + else + PRINTF("Get Message From Master Side : \"%s\" [len : %d]\r\n", app_buf, len); + + /* Get tx buffer from RPMsg */ + tx_buf = rpmsg_lite_alloc_tx_buffer(my_rpmsg, &size, RL_BLOCK); + assert(tx_buf); + /* Copy string to RPMsg tx buffer */ + memcpy(tx_buf, app_buf, len); + /* Echo back received message with nocopy send */ + result = rpmsg_lite_send_nocopy(my_rpmsg, my_ept, remote_addr, tx_buf, len); + if (result != 0) + { + assert(false); + } + /* Release held RPMsg rx buffer */ + result = rpmsg_queue_nocopy_free(my_rpmsg, rx_buf); + if (result != 0) + { + assert(false); + } + } +} + +void app_create_task(void) +{ + if (app_task_handle == NULL && + xTaskCreate(app_task, "APP_TASK", APP_TASK_STACK_SIZE, NULL, tskIDLE_PRIORITY + 1, &app_task_handle) != pdPASS) + { + PRINTF("\r\nFailed to create application task\r\n"); + for (;;) + ; + } +} + +/*! + * @brief Main function + */ +int main(void) +{ + /* Initialize standard SDK demo application pins */ + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + + /* copy resource table to destination address(TCM) */ + copyResourceTable(); + +#ifdef MCMGR_USED + /* Initialize MCMGR before calling its API */ + (void)MCMGR_Init(); +#endif /* MCMGR_USED */ + + app_create_task(); + vTaskStartScheduler(); + + PRINTF("Failed to start FreeRTOS on core0.\n"); + for (;;) + ; +} diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/pin_mux.c b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/pin_mux.c new file mode 100644 index 000000000..4c8d6a119 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/pin_mux.c @@ -0,0 +1,65 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/pin_mux.h b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/readme.txt b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/readme.txt new file mode 100644 index 000000000..571f9f11f --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/readme.txt @@ -0,0 +1,81 @@ +Overview +======== +The Multicore RPMsg-Lite string echo project is a simple demonstration program that uses the +MCUXpresso SDK software and the RPMsg-Lite library and shows how to implement the inter-core +communicaton between cores of the multicore system. + +It works with Linux RPMsg master peer to transfer string content back and forth. The name service +handshake is performed first to create the communication channels. Next, Linux OS waits for user +input to the RPMsg virtual tty. Anything which is received is sent to M4. M4 displays what is +received, and echoes back the same message as an acknowledgement. The tty reader on the Linux side +can get the message, and start another transaction. The demo demonstrates RPMsg’s ability to send +arbitrary content back and forth. Note: The maximum message length supported by RPMsg is now 496 +bytes. String longer than 496 will be divided by virtual tty into several messages. + +Shared memory usage +This multicore example uses the shared memory for data exchange. The shared memory region is +defined and the size can be adjustable in the linker file. The shared memory region start address +and the size have to be defined in linker file for each core equally. The shared memory start +address is then exported from the linker to the application. + +Toolchain supported +=================== +- GCC ARM Embedded 10.3.1 +- IAR embedded Workbench 9.30.1 + +Hardware requirements +===================== +- Micro USB cable +- USB to UART Adapter +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Proper power supply +- Personal Computer + +Board settings +============== +The Multicore RPMsg-Lite string echo project does not call for any special hardware configurations. +Although not required, the recommendation is to leave the development board jumper settings and +configurations in default state when running this demo. + + +Prepare the Demo +================ +1. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). + Open two serial terminals for A Core and M Core with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control + (e.g. /dev/ttyUSB0~3, /dev/ttyUSB2 for A Core, /dev/ttyUSB3 for M Core) +2. Connect the power supply to the board and switch on the board. switch SW301 to power on the board +3. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. +4. Append "clk_ignore_unused" in u-boot "mmcargs" env, before booting linux. +5. Boot to linux. +6. After login, make sure imx_rpmsg_tty kernel module is inserted (lsmod) or insert it (modprobe imx_rpmsg_tty). + +Running the demo +================ +After the boot process succeeds, the ARM Cortex-M33 terminal displays the following information: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +RPMSG String Echo FreeRTOS RTOS API Demo... + +Nameservice sent, ready for incoming messages... +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +After the Linux RPMsg tty module was installed, the ARM Cortex-M33 terminal displays the following +information: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Get Messgae From Master Side : "hello world!" [len : 12] +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +The user can then input an arbitrary string to the virtual RPMsg tty using the following echo command on +Cortex-A terminal: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +echo test > /dev/ttyRPMSG + here is the allocated ttyRPMsg channel number. Please find out the number in the file system by "ls" command. +Log below shows the output of the RPMsg-Lite str echo demo in the terminal window: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +On the M33 terminal, the received string content and its length is output, as shown in the log. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Get Message From Master Side : "test" [len : 4] +Get New Line From Master Side +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/remoteproc.h b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/remoteproc.h new file mode 100644 index 000000000..7dad9c9eb --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/remoteproc.h @@ -0,0 +1,372 @@ +/* + * Remoteproc Framework + * + * Copyright 2020 NXP. + * Copyright(c) 2018 Xilinx Ltd. + * Copyright(c) 2011 Texas Instruments, Inc. + * Copyright(c) 2011 Google, Inc. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef REMOTEPROC_H +#define REMOTEPROC_H + +#include + +#if defined __cplusplus +extern "C" { +#endif + +#define RSC_NOTIFY_ID_ANY 0xFFFFFFFFUL + +#define RPROC_MAX_NAME_LEN 32 + +/* IAR ARM build tools */ +#if defined(__ICCARM__) + +#ifndef METAL_PACKED_BEGIN +#define METAL_PACKED_BEGIN __packed +#endif + +#ifndef METAL_PACKED_END +#define METAL_PACKED_END +#endif + +/* GNUC */ +#elif defined(__GNUC__) + +#ifndef METAL_PACKED_BEGIN +#define METAL_PACKED_BEGIN +#endif + +#ifndef METAL_PACKED_END +#define METAL_PACKED_END __attribute__((__packed__)) +#endif + +/* ARMCC */ +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) + +#ifndef METAL_PACKED_BEGIN +#define METAL_PACKED_BEGIN _Pragma("pack(1U)") +#endif + +#ifndef METAL_PACKED_END +#define METAL_PACKED_END _Pragma("pack()") +#endif + +#else +/* There is no default definition here to avoid wrong structures packing in case of not supported compiler */ +#error Please implement the structure packing macros for your compiler here! +#endif + +/** + * struct resource_table - firmware resource table header + * @ver: version number + * @num: number of resource entries + * @reserved: reserved (must be zero) + * @offset: array of offsets pointing at the various resource entries + * + * A resource table is essentially a list of system resources required + * by the remote remoteproc. It may also include configuration entries. + * If needed, the remote remoteproc firmware should contain this table + * as a dedicated ".resource_table" ELF section. + * + * Some resources entries are mere announcements, where the host is informed + * of specific remoteproc configuration. Other entries require the host to + * do something (e.g. allocate a system resource). Sometimes a negotiation + * is expected, where the firmware requests a resource, and once allocated, + * the host should provide back its details (e.g. address of an allocated + * memory region). + * + * The header of the resource table, as expressed by this structure, + * contains a version number (should we need to change this format in the + * future), the number of available resource entries, and their offsets + * in the table. + * + * Immediately following this header are the resource entries themselves, + * each of which begins with a resource entry header (as described below). + */ +METAL_PACKED_BEGIN +struct resource_table +{ + uint32_t ver; + uint32_t num; + uint32_t reserved[2]; + uint32_t offset[0]; +} METAL_PACKED_END; + +/** + * struct fw_rsc_hdr - firmware resource entry header + * @type: resource type + * @data: resource data + * + * Every resource entry begins with a 'struct fw_rsc_hdr' header providing + * its @type. The content of the entry itself will immediately follow + * this header, and it should be parsed according to the resource type. + */ +METAL_PACKED_BEGIN +struct fw_rsc_hdr +{ + uint32_t type; + uint8_t data[0]; +} METAL_PACKED_END; + +/** + * enum fw_resource_type - types of resource entries + * + * @RSC_CARVEOUT: request for allocation of a physically contiguous + * memory region. + * @RSC_DEVMEM: request to iommu_map a memory-based peripheral. + * @RSC_TRACE: announces the availability of a trace buffer into which + * the remote remoteproc will be writing logs. + * @RSC_VDEV: declare support for a virtio device, and serve as its + * virtio header. + * @RSC_VENDOR_START: start of the vendor specific resource types range + * @RSC_VENDOR_END : end of the vendor specific resource types range + * @RSC_LAST: just keep this one at the end + * + * For more details regarding a specific resource type, please see its + * dedicated structure below. + * + * Please note that these values are used as indices to the rproc_handle_rsc + * lookup table, so please keep them sane. Moreover, @RSC_LAST is used to + * check the validity of an index before the lookup table is accessed, so + * please update it as needed. + */ +enum fw_resource_type +{ + RSC_CARVEOUT = 0, + RSC_DEVMEM = 1, + RSC_TRACE = 2, + RSC_VDEV = 3, + RSC_LAST = 4, + RSC_VENDOR_START = 128, + RSC_VENDOR_END = 512, +}; + +#define FW_RSC_U64_ADDR_ANY 0xFFFFFFFFFFFFFFFFUL +#define FW_RSC_U32_ADDR_ANY 0xFFFFFFFFUL + +/** + * struct fw_rsc_carveout - physically contiguous memory request + * @da: device address + * @pa: physical address + * @len: length (in bytes) + * @flags: iommu protection flags + * @reserved: reserved (must be zero) + * @name: human-readable name of the requested memory region + * + * This resource entry requests the host to allocate a physically contiguous + * memory region. + * + * These request entries should precede other firmware resource entries, + * as other entries might request placing other data objects inside + * these memory regions (e.g. data/code segments, trace resource entries, ...). + * + * Allocating memory this way helps utilizing the reserved physical memory + * (e.g. CMA) more efficiently, and also minimizes the number of TLB entries + * needed to map it (in case @rproc is using an IOMMU). Reducing the TLB + * pressure is important; it may have a substantial impact on performance. + * + * If the firmware is compiled with static addresses, then @da should specify + * the expected device address of this memory region. If @da is set to + * FW_RSC_ADDR_ANY, then the host will dynamically allocate it, and then + * overwrite @da with the dynamically allocated address. + * + * We will always use @da to negotiate the device addresses, even if it + * isn't using an iommu. In that case, though, it will obviously contain + * physical addresses. + * + * Some remote remoteprocs needs to know the allocated physical address + * even if they do use an iommu. This is needed, e.g., if they control + * hardware accelerators which access the physical memory directly (this + * is the case with OMAP4 for instance). In that case, the host will + * overwrite @pa with the dynamically allocated physical address. + * Generally we don't want to expose physical addresses if we don't have to + * (remote remoteprocs are generally _not_ trusted), so we might want to + * change this to happen _only_ when explicitly required by the hardware. + * + * @flags is used to provide IOMMU protection flags, and @name should + * (optionally) contain a human readable name of this carveout region + * (mainly for debugging purposes). + */ +METAL_PACKED_BEGIN +struct fw_rsc_carveout +{ + uint32_t type; + uint32_t da; + uint32_t pa; + uint32_t len; + uint32_t flags; + uint32_t reserved; + uint8_t name[RPROC_MAX_NAME_LEN]; +} METAL_PACKED_END; + +/** + * struct fw_rsc_devmem - iommu mapping request + * @da: device address + * @pa: physical address + * @len: length (in bytes) + * @flags: iommu protection flags + * @reserved: reserved (must be zero) + * @name: human-readable name of the requested region to be mapped + * + * This resource entry requests the host to iommu map a physically contiguous + * memory region. This is needed in case the remote remoteproc requires + * access to certain memory-based peripherals; _never_ use it to access + * regular memory. + * + * This is obviously only needed if the remote remoteproc is accessing memory + * via an iommu. + * + * @da should specify the required device address, @pa should specify + * the physical address we want to map, @len should specify the size of + * the mapping and @flags is the IOMMU protection flags. As always, @name may + * (optionally) contain a human readable name of this mapping (mainly for + * debugging purposes). + * + * Note: at this point we just "trust" those devmem entries to contain valid + * physical addresses, but this isn't safe and will be changed: eventually we + * want remoteproc implementations to provide us ranges of physical addresses + * the firmware is allowed to request, and not allow firmwares to request + * access to physical addresses that are outside those ranges. + */ +METAL_PACKED_BEGIN +struct fw_rsc_devmem +{ + uint32_t type; + uint32_t da; + uint32_t pa; + uint32_t len; + uint32_t flags; + uint32_t reserved; + uint8_t name[RPROC_MAX_NAME_LEN]; +} METAL_PACKED_END; + +/** + * struct fw_rsc_trace - trace buffer declaration + * @da: device address + * @len: length (in bytes) + * @reserved: reserved (must be zero) + * @name: human-readable name of the trace buffer + * + * This resource entry provides the host information about a trace buffer + * into which the remote remoteproc will write log messages. + * + * @da specifies the device address of the buffer, @len specifies + * its size, and @name may contain a human readable name of the trace buffer. + * + * After booting the remote remoteproc, the trace buffers are exposed to the + * user via debugfs entries (called trace0, trace1, etc..). + */ +METAL_PACKED_BEGIN +struct fw_rsc_trace +{ + uint32_t type; + uint32_t da; + uint32_t len; + uint32_t reserved; + uint8_t name[RPROC_MAX_NAME_LEN]; +} METAL_PACKED_END; + +/** + * struct fw_rsc_vdev_vring - vring descriptor entry + * @da: device address + * @align: the alignment between the consumer and producer parts of the vring + * @num: num of buffers supported by this vring (must be power of two) + * @notifyid is a unique rproc-wide notify index for this vring. This notify + * index is used when kicking a remote remoteproc, to let it know that this + * vring is triggered. + * @reserved: reserved (must be zero) + * + * This descriptor is not a resource entry by itself; it is part of the + * vdev resource type (see below). + * + * Note that @da should either contain the device address where + * the remote remoteproc is expecting the vring, or indicate that + * dynamically allocation of the vring's device address is supported. + */ +METAL_PACKED_BEGIN +struct fw_rsc_vdev_vring +{ + uint32_t da; + uint32_t align; + uint32_t num; + uint32_t notifyid; + uint32_t reserved; +} METAL_PACKED_END; + +/** + * struct fw_rsc_vdev - virtio device header + * @id: virtio device id (as in virtio_ids.h) + * @notifyid is a unique rproc-wide notify index for this vdev. This notify + * index is used when kicking a remote remoteproc, to let it know that the + * status/features of this vdev have changes. + * @dfeatures specifies the virtio device features supported by the firmware + * @gfeatures is a place holder used by the host to write back the + * negotiated features that are supported by both sides. + * @config_len is the size of the virtio config space of this vdev. The config + * space lies in the resource table immediate after this vdev header. + * @status is a place holder where the host will indicate its virtio progress. + * @num_of_vrings indicates how many vrings are described in this vdev header + * @reserved: reserved (must be zero) + * @vring is an array of @num_of_vrings entries of 'struct fw_rsc_vdev_vring'. + * + * This resource is a virtio device header: it provides information about + * the vdev, and is then used by the host and its peer remote remoteprocs + * to negotiate and share certain virtio properties. + * + * By providing this resource entry, the firmware essentially asks remoteproc + * to statically allocate a vdev upon registration of the rproc (dynamic vdev + * allocation is not yet supported). + * + * Note: unlike virtualization systems, the term 'host' here means + * the Linux side which is running remoteproc to control the remote + * remoteprocs. We use the name 'gfeatures' to comply with virtio's terms, + * though there isn't really any virtualized guest OS here: it's the host + * which is responsible for negotiating the final features. + * Yeah, it's a bit confusing. + * + * Note: immediately following this structure is the virtio config space for + * this vdev (which is specific to the vdev; for more info, read the virtio + * spec). the size of the config space is specified by @config_len. + */ +METAL_PACKED_BEGIN +struct fw_rsc_vdev +{ + uint32_t type; + uint32_t id; + uint32_t notifyid; + uint32_t dfeatures; + uint32_t gfeatures; + uint32_t config_len; + uint8_t status; + uint8_t num_of_vrings; + uint8_t reserved[2]; + struct fw_rsc_vdev_vring vring[0]; +} METAL_PACKED_END; + +/** + * struct fw_rsc_vendor - remote processor vendor specific resource + * @len: length of the resource + * + * This resource entry tells the host the vendor specific resource + * required by the remote. + * + * These request entries should precede other shared resource entries + * such as vdevs, vrings. + */ +METAL_PACKED_BEGIN +struct fw_rsc_vendor +{ + uint32_t type; + uint32_t len; +} METAL_PACKED_END; + +#if defined __cplusplus +} +#endif + +#endif /* REMOTEPROC_H_ */ diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/rpmsg_config.h b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/rpmsg_config.h new file mode 100644 index 000000000..0222e60ff --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/rpmsg_config.h @@ -0,0 +1,79 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _RPMSG_CONFIG_H +#define _RPMSG_CONFIG_H + +/*! + * @addtogroup config + * @{ + * @file + */ + +//! @name Configuration options +//@{ + +//! @def RL_MS_PER_INTERVAL +//! +//! Delay in milliseconds used in non-blocking API functions for polling. +//! The default value is 1. +#define RL_MS_PER_INTERVAL (1) + +//! @def RL_BUFFER_PAYLOAD_SIZE +//! +//! Size of the buffer payload, it must be equal to (240, 496, 1008, ...) +//! [2^n - 16]. +//! The default value is 496U. +#define RL_BUFFER_PAYLOAD_SIZE (496U) + +//! @def RL_BUFFER_COUNT +//! +//! Number of the buffers, it must be power of two (2, 4, ...). +//! The default value is 2U. +#define RL_BUFFER_COUNT (256U) + +//! @def RL_API_HAS_ZEROCOPY +//! +//! Zero-copy API functions enabled/disabled. +//! The default value is 1 (enabled). +#define RL_API_HAS_ZEROCOPY (1) + +//! @def RL_USE_STATIC_API +//! +//! Static API functions (no dynamic allocation) enabled/disabled. +//! The default value is 0 (static API disabled). +#define RL_USE_STATIC_API (0) + +//! @def RL_CLEAR_USED_BUFFERS +//! +//! Clearing used buffers before returning back to the pool of free buffers +//! enabled/disabled. +//! The default value is 0 (disabled). +#define RL_CLEAR_USED_BUFFERS (0) + +//! @def RL_USE_MCMGR_IPC_ISR_HANDLER +//! +//! When enabled IPC interrupts are managed by the Multicore Manager (IPC +//! interrupts router), when disabled RPMsg-Lite manages IPC interrupts +//! by itself. +//! The default value is 0 (no MCMGR IPC ISR handler used). +#define RL_USE_MCMGR_IPC_ISR_HANDLER (0) + +//! @def RL_USE_ENVIRONMENT_CONTEXT +//! +//! When enabled the environment layer uses its own context. +//! Added for QNX port mainly, but can be used if required. +//! The default value is 0 (no context, saves some RAM). +#define RL_USE_ENVIRONMENT_CONTEXT (0) + +//! @def RL_DEBUG_CHECK_BUFFERS +//! +//! Do not use in RPMsg-Lite to Linux configuration +#define RL_DEBUG_CHECK_BUFFERS (0) +//@} +// +#endif /* _RPMSG_CONFIG_H */ diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/rsc_table.c b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/rsc_table.c new file mode 100644 index 000000000..18b7f56d6 --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/rsc_table.c @@ -0,0 +1,91 @@ +/* + * Copyright 2022 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* This file populates resource table for BM remote + * for use by the Linux Master */ + +#include +#include "board.h" +#include "rsc_table.h" +#include "rpmsg_lite.h" + +#define NUM_VRINGS 0x02 + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif +const struct remote_resource_table resources = { + /* Version */ + 1, + + /* NUmber of table entries */ + NO_RESOURCE_ENTRIES, + + /* reserved fields */ + { + 0, + 0, + }, + + /* Offsets of rsc entries */ + { + offsetof(struct remote_resource_table, srtm_vdev), + offsetof(struct remote_resource_table, user_vdev), + }, + + /* SRTM virtio device entry */ + { + RSC_VDEV, + 7, + 0, + RSC_VDEV_FEATURE_NS, + 0, + 0, + 0, + NUM_VRINGS, + {0, 0}, + }, + + /* Vring rsc entry - part of vdev rsc entry */ + {VDEV0_VRING_BASE, VRING_ALIGN, RL_BUFFER_COUNT, 0, 0}, + {VDEV0_VRING_BASE + VRING_SIZE, VRING_ALIGN, RL_BUFFER_COUNT, 1, 0}, + + /* SRTM virtio device entry */ + { + RSC_VDEV, + 7, + 1, + RSC_VDEV_FEATURE_NS, + 0, + 0, + 0, + NUM_VRINGS, + {0, 0}, + }, + + /* Vring rsc entry - part of vdev rsc entry */ + {VDEV1_VRING_BASE, VRING_ALIGN, RL_BUFFER_COUNT, 2, 0}, + {VDEV1_VRING_BASE + VRING_SIZE, VRING_ALIGN, RL_BUFFER_COUNT, 3, 0}, +}; + +void copyResourceTable(void) +{ + /* + * On startup, DDR not be enabled when M Core does resource table copy. + * Here store the resource table to a destination address + * (such as: 0x2001f000(NS)/0x3001F000(S) in TCM). + */ + memset((void *)0x2001F000U, 0, + 0x1000); /* ECC is enabled defaultly , cortex-A55 failed to read 4KB from the region when the region is not + initialized.(cortex-A55 report an ECC read error) */ + memcpy((void *)0x2001F000U, &resources, sizeof(resources)); +} diff --git a/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/rsc_table.h b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/rsc_table.h new file mode 100644 index 000000000..efd8caefc --- /dev/null +++ b/boards/som_mx93/multicore_examples/rpmsg_lite_str_echo_rtos/rsc_table.h @@ -0,0 +1,53 @@ +/* + * Copyright 2022 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* This file populates resource table for BM remote + * for use by the Linux Master */ + +#ifndef RSC_TABLE_H_ +#define RSC_TABLE_H_ + +#include +#include + +#if defined __cplusplus +extern "C" { +#endif + +#define NO_RESOURCE_ENTRIES (2) +#define RSC_VDEV_FEATURE_NS (1) /* Support name service announcement */ + +/* Resource table for the given remote */ +METAL_PACKED_BEGIN +struct remote_resource_table +{ + uint32_t version; + uint32_t num; + uint32_t reserved[2]; + uint32_t offset[NO_RESOURCE_ENTRIES]; + + /* rpmsg vdev entry for srtm communication */ + struct fw_rsc_vdev srtm_vdev; + struct fw_rsc_vdev_vring srtm_vring0; + struct fw_rsc_vdev_vring srtm_vring1; + /* rpmsg vdev entry for user app communication */ + struct fw_rsc_vdev user_vdev; + struct fw_rsc_vdev_vring user_vring0; + struct fw_rsc_vdev_vring user_vring1; +} METAL_PACKED_END; + +/* + * Copy resource table to shared memory base for early M Core boot case. + * In M Core early boot case, Linux kernel need to get resource table before file system gets loaded. + */ +void copyResourceTable(void); + +#if defined __cplusplus +} +#endif + +#endif /* RSC_TABLE_H_ */ diff --git a/boards/som_mx93/project_template/board.c b/boards/som_mx93/project_template/board.c new file mode 100644 index 000000000..384d8f531 --- /dev/null +++ b/boards/som_mx93/project_template/board.c @@ -0,0 +1,37 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + diff --git a/boards/som_mx93/project_template/board.h b/boards/som_mx93/project_template/board.h new file mode 100644 index 000000000..efcf21814 --- /dev/null +++ b/boards/som_mx93/project_template/board.h @@ -0,0 +1,41 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/project_template/clock_config.c b/boards/som_mx93/project_template/clock_config.c new file mode 100644 index 000000000..53a5abb4c --- /dev/null +++ b/boards/som_mx93/project_template/clock_config.c @@ -0,0 +1,162 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" +#include "board.h" +#include "fsl_upower.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* + * SYSOSC clock setting. + * SYSOSC clock : 24MHz + */ +const cgc_sosc_config_t g_cgcSysOscConfig = {.freq = BOARD_XTAL0_CLK_HZ, + .enableMode = 0, /* Disabled in Deep Sleep/Power down */ + .monitorMode = kCGC_SysOscMonitorDisable, + .workMode = kCGC_SysOscModeOscLowPower}; + +/* + * FRO clock setting. + * FRO clock : 192MHz + */ +const cgc_fro_config_t g_cgcFroConfig = {.enableMode = kCGC_FroEnableInDeepSleep}; + +/* + * PLL0 clock setting. + * PLL0 clock VCO : 24 * 20 = 480MHz + * PLL0 VCODIV output : 0MHz + * PLL0 PFD1DIV output : 0MHz + * PLL0 PFD2DIV output : 0MHz + */ +const cgc_pll0_config_t g_cgcPll0Config = {.enableMode = kCGC_PllEnable, + .div1 = 0U, + .pfd1Div = 0U, + .pfd2Div = 0U, + .src = kCGC_PllSrcSysOsc, + .mult = kCGC_Pll0Mult20 + }; /* x20 */ + +/* + * PLL1 clock setting. + * PLL1 clock VCO : 24 * 22.528 = 540.672MHz + * PLL1 VCODIV output : 0MHz + * PLL1 PFD1DIV output : 0MHz + * PLL1 PFD2DIV output : 540.672 / 44 = 12.288MHz + */ +const cgc_pll1_config_t g_cgcPll1Config = {.enableMode = kCGC_PllEnable, + .div1 = 0U, + .pfd1Div = 0U, + .pfd2Div = 44U, + .src = kCGC_PllSrcSysOsc, + .mult = kCGC_Pll1Mult22, + .num = 528000U, + .denom = 1000000U}; + +/* + * Select FRO as system clock source, before configuring other clock sources. + * Clock source : FRO + * Core clock : 192MHz + * Bus clock : 96MHz + * Slow clock : 24MHz + */ +const cgc_rtd_sys_clk_config_t g_sysClkConfigFroSource = { + .divCore = 0, /* Core clock divider. */ + .divBus = 1, /* Bus clock divider. */ + .divSlow = 3, /* Slow clock divider. */ + .src = kCGC_RtdSysClkSrcFro, /* System clock source. */ + .locked = 0, /* Register not locked. */ +}; + +/* + * System clock source and divider in Normal RUN mode. + * + * Clock source : PLL0 main clock 480MHz. + * Core clock : 160MHz + * Bus clock : 80MHz + * Slow clock : 20MHz + */ +const cgc_rtd_sys_clk_config_t g_sysClkConfigRun = { + .divCore = 2, /* Core clock divider. */ + .divBus = 1, /* Bus clock divider. */ + .divSlow = 7, /* Slow clock divider. */ + .src = kCGC_RtdSysClkSrcPll0, /* PLL0 main clock source. */ + .locked = 0, /* Register not locked. */ +}; + +/******************************************************************************* + * Code + ******************************************************************************/ +static void BOARD_InitClock(void) +{ + CLOCK_InitFro(&g_cgcFroConfig); + + if (!CLOCK_IsSysOscValid()) + { + CLOCK_InitSysOsc(&g_cgcSysOscConfig); + } + + CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ); + + /* Then set SOSC, FRO DIV needed by application */ + CLOCK_SetRtdSysOscAsyncClkDiv(kCGC_AsyncDiv1Clk, 1); + CLOCK_SetRtdSysOscAsyncClkDiv(kCGC_AsyncDiv2Clk, 1); + CLOCK_SetRtdSysOscAsyncClkDiv(kCGC_AsyncDiv3Clk, 0); + + CLOCK_SetRtdFroAsyncClkDiv(kCGC_AsyncDiv1Clk, 1); + CLOCK_SetRtdFroAsyncClkDiv(kCGC_AsyncDiv2Clk, 1); + CLOCK_SetRtdFroAsyncClkDiv(kCGC_AsyncDiv3Clk, 0); + + /* RTC OSC clock is enabled by default, initalize g_xtal32Freq */ + CLOCK_SetXtal32Freq(CLK_RTC_32K_CLK); +} + +/* + * Clock in RUN mode: + * SYSOSC : Enable + * FRO : Enable + * FIRC : Enable + * PLL0 : Enable + * AUXPLL : Enable + */ +void BOARD_BootClockRUN(void) +{ + UPOWER_Init(NULL); + BOARD_InitClock(); + + /* Call function BOARD_FlexspiClockSafeConfig() to move FlexSPI clock to a stable clock source to avoid + instruction/data fetch issue when updating PLL and Main clock if XIP(execute code on FLEXSPI memory). */ + BOARD_FlexspiClockSafeConfig(); + + CLOCK_SetCm33SysClkConfig(&g_sysClkConfigFroSource); + + /* Set voltage for RTD sysclk from FRO(192MHz) to PLL(240MHz) */ + UPOWER_SetVoltageForFreq(RTD_DOMAIN, CLOCK_GetFroFreq() / 1000U, 240000U); + + /* Initialize PLL0 480MHz */ + CLOCK_InitPll0(&g_cgcPll0Config); + + /* Enable Pll0 Pfd1 576MHz */ + CLOCK_EnablePll0PfdClkout(kCGC_PllPfd1Clk, 15U); + /* Enable Pll0 Pfd2 480MHz */ + CLOCK_EnablePll0PfdClkout(kCGC_PllPfd2Clk, 18U); + /* Enable Pll0 Pfd3 392MHz */ + CLOCK_EnablePll0PfdClkout(kCGC_PllPfd3Clk, 22U); + + /* Initialize PLL1 */ + CLOCK_InitPll1(&g_cgcPll1Config); + /* Enable Pll1 Pfd2 540.672MHz */ + CLOCK_EnablePll1PfdClkout(kCGC_PllPfd2Clk, 18U); + + CLOCK_SetCm33SysClkConfig(&g_sysClkConfigRun); + + /* Call function BOARD_SetFlexspiClock() to set user configured clock source/divider for FlexSPI. */ + BOARD_SetFlexspiClock(FLEXSPI0, 5U, 1U, 0U); /* CM33_PLATCLK / 2 = 120MHz */ + + SystemCoreClockUpdate(); +} diff --git a/boards/som_mx93/project_template/clock_config.h b/boards/som_mx93/project_template/clock_config.h new file mode 100644 index 000000000..5506a3e86 --- /dev/null +++ b/boards/som_mx93/project_template/clock_config.h @@ -0,0 +1,31 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U +#define BOARD_XTAL32K_CLK_HZ 32768U + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/project_template/peripherals.c b/boards/som_mx93/project_template/peripherals.c new file mode 100644 index 000000000..163d5872d --- /dev/null +++ b/boards/som_mx93/project_template/peripherals.c @@ -0,0 +1,23 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Peripherals v1.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Included files + ******************************************************************************/ +#include "peripherals.h" + +/******************************************************************************* + * BOARD_InitBootPeripherals function + ******************************************************************************/ +void BOARD_InitBootPeripherals(void) +{ +} diff --git a/boards/som_mx93/project_template/peripherals.h b/boards/som_mx93/project_template/peripherals.h new file mode 100644 index 000000000..436c516a9 --- /dev/null +++ b/boards/som_mx93/project_template/peripherals.h @@ -0,0 +1,23 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PERIPHERALS_H_ +#define _PERIPHERALS_H_ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus. */ +/******************************************************************************* + * BOARD_InitBootPeripherals function + ******************************************************************************/ +void BOARD_InitBootPeripherals(void); + +#if defined(__cplusplus) +} +#endif /*_cplusplus. */ + +#endif /* _PERIPHERALS_H_ */ diff --git a/boards/som_mx93/project_template/pin_mux.c b/boards/som_mx93/project_template/pin_mux.c new file mode 100644 index 000000000..4c8d6a119 --- /dev/null +++ b/boards/som_mx93/project_template/pin_mux.c @@ -0,0 +1,65 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/project_template/pin_mux.h b/boards/som_mx93/project_template/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/project_template/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/rtos_examples/freertos_event/FreeRTOSConfig.h b/boards/som_mx93/rtos_examples/freertos_event/FreeRTOSConfig.h new file mode 100644 index 000000000..6f6bcf9da --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_event/FreeRTOSConfig.h @@ -0,0 +1,182 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)200) +#define configMAX_PRIORITIES 5 +#define configMINIMAL_STACK_SIZE ((unsigned short)90) +#define configMAX_TASK_NAME_LEN 20 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 + +/* Used memory allocation (heap_x.c) */ +#define configFRTOS_MEMORY_SCHEME 4 +/* Tasks.c additions (e.g. Thread Aware Debug capability) */ +#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE ((size_t)(10 * 1024)) +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Task aware debugging. */ +#define configRECORD_STACK_HIGH_ADDRESS 1 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +/* Define to trap errors during development. */ +#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + + + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) + /* Clock manager provides in this variable system core clock frequency */ + #include + extern uint32_t SystemCoreClock; +#endif + + +#ifndef configENABLE_FPU + #define configENABLE_FPU 1 +#endif +#ifndef configENABLE_MPU + #define configENABLE_MPU 0 +#endif +#ifndef configENABLE_TRUSTZONE + #define configENABLE_TRUSTZONE 0 +#endif +#ifndef configRUN_FREERTOS_SECURE_ONLY + #define configRUN_FREERTOS_SECURE_ONLY 1 +#endif + +/* Redefine: Mutex is needed for SRTM communication */ +#undef configUSE_MUTEXES +#define configUSE_MUTEXES 1 + +#ifndef configTOTAL_HEAP_SIZE +#define configTOTAL_HEAP_SIZE ((size_t)(40 * 1024)) +#endif + +/* Interrupt nesting behaviour configuration. Cortex-M specific. */ +#ifdef __NVIC_PRIO_BITS +/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ +#define configPRIO_BITS __NVIC_PRIO_BITS +#else +#define configPRIO_BITS 3 /* 7 priority levels */ +#endif + +#define configSTACK_DEPTH_TYPE uint32_t + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define vPortPendSVHandler PendSV_Handler +#define vPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ diff --git a/boards/som_mx93/rtos_examples/freertos_event/armgcc/CMakeLists.txt b/boards/som_mx93/rtos_examples/freertos_event/armgcc/CMakeLists.txt new file mode 100644 index 000000000..0d26b2098 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_event/armgcc/CMakeLists.txt @@ -0,0 +1,121 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(freertos_event) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME freertos_event.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../freertos_event.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../FreeRTOSConfig.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/rtos/freertos/freertos-kernel + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/serial_manager + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(middleware_freertos-kernel_cm33_nonsecure_port_MIMX9352) + +include(driver_clock_MIMX9352) + +include(middleware_freertos-kernel_heap_4_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(utility_debug_console_MIMX9352) + +include(utility_assert_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_serial_manager_MIMX9352) + +include(component_lists_MIMX9352) + +include(component_serial_manager_uart_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(middleware_freertos-kernel_MIMX9352) + +include(middleware_freertos-kernel_extension_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/rtos_examples/freertos_event/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/rtos_examples/freertos_event/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_event/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/rtos_examples/freertos_event/armgcc/build_all.bat b/boards/som_mx93/rtos_examples/freertos_event/armgcc/build_all.bat new file mode 100644 index 000000000..a16d8ae13 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_event/armgcc/build_all.bat @@ -0,0 +1,15 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/som_mx93/rtos_examples/freertos_event/armgcc/build_all.sh b/boards/som_mx93/rtos_examples/freertos_event/armgcc/build_all.sh new file mode 100755 index 000000000..253693061 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_event/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/rtos_examples/freertos_event/armgcc/build_debug.bat b/boards/som_mx93/rtos_examples/freertos_event/armgcc/build_debug.bat new file mode 100644 index 000000000..15123387e --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_event/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/rtos_examples/freertos_event/armgcc/build_debug.sh b/boards/som_mx93/rtos_examples/freertos_event/armgcc/build_debug.sh new file mode 100755 index 000000000..42803761b --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_event/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/rtos_examples/freertos_event/armgcc/build_release.bat b/boards/som_mx93/rtos_examples/freertos_event/armgcc/build_release.bat new file mode 100644 index 000000000..a88e3d668 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_event/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/rtos_examples/freertos_event/armgcc/build_release.sh b/boards/som_mx93/rtos_examples/freertos_event/armgcc/build_release.sh new file mode 100755 index 000000000..47cfb057c --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_event/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/rtos_examples/freertos_event/armgcc/clean.bat b/boards/som_mx93/rtos_examples/freertos_event/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_event/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/rtos_examples/freertos_event/armgcc/clean.sh b/boards/som_mx93/rtos_examples/freertos_event/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_event/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/rtos_examples/freertos_event/armgcc/config.cmake b/boards/som_mx93/rtos_examples/freertos_event/armgcc/config.cmake new file mode 100755 index 000000000..b228f064e --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_event/armgcc/config.cmake @@ -0,0 +1,3 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_component_serial_manager_uart_MIMX9352 true) +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/rtos_examples/freertos_event/armgcc/flags.cmake b/boards/som_mx93/rtos_examples/freertos_event/armgcc/flags.cmake new file mode 100755 index 000000000..d76ba2bff --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_event/armgcc/flags.cmake @@ -0,0 +1,191 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/rtos_examples/freertos_event/board.c b/boards/som_mx93/rtos_examples/freertos_event/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_event/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/rtos_examples/freertos_event/board.h b/boards/som_mx93/rtos_examples/freertos_event/board.h new file mode 100644 index 000000000..5108807ef --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_event/board.h @@ -0,0 +1,89 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + +/* ADP5585 */ +#define BOARD_ADP5585_I2C LPI2C2 +#define BOARD_ADP5585_I2C_ADDR (0x34U) +#define BOARD_ADP5585_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_ADP5585_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_ADP5585_I2C_CLOCK_ROOT) + +#define BOARD_ADP5585_PDM_MQS_SEL (2U) +#define BOARD_ADP5585_EXP_SEL (4U) +#define BOARD_ADP5585_CAN_STBY (8U) + +/* PCAL6524 */ +#define BOARD_PCAL6524_I2C LPI2C2 +#define BOARD_PCAL6524_I2C_ADDR (0x22U) +#define BOARD_PCAL6524_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_PCAL6524_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_PCAL6524_I2C_CLOCK_ROOT) + +#define BOARD_PCAL6524_ENET1_NRST (8U + 7U) +#define BOARD_PCAL6524_ENET2_NRST (16U + 0U) +#define BOARD_PCAL6524_MIC_CAN_SEL (16U + 1U) +#define BOARD_PCAL6524_EXP_SEL (16U + 6U) +#define BOARD_PCAL6524_CAN_STBY (16U + 7U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/rtos_examples/freertos_event/clock_config.c b/boards/som_mx93/rtos_examples/freertos_event/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_event/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/rtos_examples/freertos_event/clock_config.h b/boards/som_mx93/rtos_examples/freertos_event/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_event/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/rtos_examples/freertos_event/freertos_event.c b/boards/som_mx93/rtos_examples/freertos_event/freertos_event.c new file mode 100644 index 000000000..c4d47c19e --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_event/freertos_event.c @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* FreeRTOS kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "event_groups.h" + +/* Freescale includes. */ +#include "fsl_device_registers.h" +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "board.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define B0 (1 << 0) +#define B1 (1 << 1) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static void write_task_1(void *pvParameters); +static void write_task_2(void *pvParameters); +static void read_task(void *pvParameters); +/******************************************************************************* + * Globals + ******************************************************************************/ +static EventGroupHandle_t event_group = NULL; + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief Main function + */ +int main(void) +{ + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + event_group = xEventGroupCreate(); + if (xTaskCreate(write_task_1, "WRITE_TASK_1", configMINIMAL_STACK_SIZE + 100, NULL, tskIDLE_PRIORITY + 1, NULL) != + pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + while (1) + ; + } + if (xTaskCreate(write_task_2, "WRITE_TASK_2", configMINIMAL_STACK_SIZE + 100, NULL, tskIDLE_PRIORITY + 1, NULL) != + pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + while (1) + ; + } + if (xTaskCreate(read_task, "READ_TASK", configMINIMAL_STACK_SIZE + 100, NULL, tskIDLE_PRIORITY + 2, NULL) != pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + while (1) + ; + } + /* Start scheduling. */ + vTaskStartScheduler(); + for (;;) + ; +} + +/*! + * @brief write_task_1 function + */ +static void write_task_1(void *pvParameters) +{ + while (1) + { + xEventGroupSetBits(event_group, B0); + } +} + +/*! + * @brief write_task_2 function + */ +static void write_task_2(void *pvParameters) +{ + while (1) + { + xEventGroupSetBits(event_group, B1); + } +} + +/*! + * @brief read_task function + */ +static void read_task(void *pvParameters) +{ + EventBits_t event_bits; + while (1) + { + event_bits = xEventGroupWaitBits(event_group, /* The event group handle. */ + B0 | B1, /* The bit pattern the event group is waiting for. */ + pdTRUE, /* B0 and B1 will be cleared automatically. */ + pdFALSE, /* Don't wait for both bits, either bit unblock task. */ + portMAX_DELAY); /* Block indefinitely to wait for the condition to be met. */ + + if ((event_bits & (B0 | B1)) == (B0 | B1)) + { + PRINTF("Both bits are set."); + } + else if ((event_bits & B0) == B0) + { + PRINTF("Bit B0 is set.\r\n"); + } + else if ((event_bits & B1) == B1) + { + PRINTF("Bit B1 is set.\r\n"); + } + } +} diff --git a/boards/som_mx93/rtos_examples/freertos_event/pin_mux.c b/boards/som_mx93/rtos_examples/freertos_event/pin_mux.c new file mode 100644 index 000000000..4c8d6a119 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_event/pin_mux.c @@ -0,0 +1,65 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/rtos_examples/freertos_event/pin_mux.h b/boards/som_mx93/rtos_examples/freertos_event/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_event/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/rtos_examples/freertos_event/readme.txt b/boards/som_mx93/rtos_examples/freertos_event/readme.txt new file mode 100644 index 000000000..725c260eb --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_event/readme.txt @@ -0,0 +1,58 @@ +Overview +======== +This document explains the freertos_event example. It shows how task waits for an event (defined set +of bits in event group). This event can be set by any other process or interrupt in the system. + +The example application creates three tasks. Two write tasks write_task_1 and write_task_2 +continuously setting event bit 0 and bit 1. + +Read_task is waiting for any event bit and printing actual state on console. Event bits are +automatically cleared after read task is entered. + +Three possible states can occurre: +Both bits are set.z +Bit B0 is set. +Bit B1 is set. + + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Micro USB cable +- USB to UART Adapter +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Proper power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + + +Prepare the Demo +================ +1. Connect the power supply to the board and switch on the board. switch SW301 to power on the board +2. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +3. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +After the board is flashed the Tera Term will start printing the state of event bits. + +Example output: +Bit B1 is set. +Bit B0 is set. +Bit B1 is set. +Bit B0 is set. +Bit B1 is set diff --git a/boards/som_mx93/rtos_examples/freertos_generic/FreeRTOSConfig.h b/boards/som_mx93/rtos_examples/freertos_generic/FreeRTOSConfig.h new file mode 100644 index 000000000..9aebc5756 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_generic/FreeRTOSConfig.h @@ -0,0 +1,182 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)200) +#define configMAX_PRIORITIES 5 +#define configMINIMAL_STACK_SIZE ((unsigned short)90) +#define configMAX_TASK_NAME_LEN 20 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 + +/* Used memory allocation (heap_x.c) */ +#define configFRTOS_MEMORY_SCHEME 4 +/* Tasks.c additions (e.g. Thread Aware Debug capability) */ +#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE ((size_t)(10 * 1024)) +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 1 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Task aware debugging. */ +#define configRECORD_STACK_HIGH_ADDRESS 1 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +/* Define to trap errors during development. */ +#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + + + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) + /* Clock manager provides in this variable system core clock frequency */ + #include + extern uint32_t SystemCoreClock; +#endif + + +#ifndef configENABLE_FPU + #define configENABLE_FPU 1 +#endif +#ifndef configENABLE_MPU + #define configENABLE_MPU 0 +#endif +#ifndef configENABLE_TRUSTZONE + #define configENABLE_TRUSTZONE 0 +#endif +#ifndef configRUN_FREERTOS_SECURE_ONLY + #define configRUN_FREERTOS_SECURE_ONLY 1 +#endif + +/* Redefine: Mutex is needed for SRTM communication */ +#undef configUSE_MUTEXES +#define configUSE_MUTEXES 1 + +#ifndef configTOTAL_HEAP_SIZE +#define configTOTAL_HEAP_SIZE ((size_t)(40 * 1024)) +#endif + +/* Interrupt nesting behaviour configuration. Cortex-M specific. */ +#ifdef __NVIC_PRIO_BITS +/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ +#define configPRIO_BITS __NVIC_PRIO_BITS +#else +#define configPRIO_BITS 3 /* 7 priority levels */ +#endif + +#define configSTACK_DEPTH_TYPE uint32_t + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define vPortPendSVHandler PendSV_Handler +#define vPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ diff --git a/boards/som_mx93/rtos_examples/freertos_generic/armgcc/CMakeLists.txt b/boards/som_mx93/rtos_examples/freertos_generic/armgcc/CMakeLists.txt new file mode 100644 index 000000000..c529b1205 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_generic/armgcc/CMakeLists.txt @@ -0,0 +1,121 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(freertos_generic) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME freertos_generic.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../freertos_generic.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../FreeRTOSConfig.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/rtos/freertos/freertos-kernel + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/serial_manager + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(middleware_freertos-kernel_cm33_nonsecure_port_MIMX9352) + +include(driver_clock_MIMX9352) + +include(middleware_freertos-kernel_heap_4_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(utility_debug_console_MIMX9352) + +include(utility_assert_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_serial_manager_MIMX9352) + +include(component_lists_MIMX9352) + +include(component_serial_manager_uart_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(middleware_freertos-kernel_MIMX9352) + +include(middleware_freertos-kernel_extension_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/rtos_examples/freertos_generic/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/rtos_examples/freertos_generic/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_generic/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/rtos_examples/freertos_generic/armgcc/build_all.bat b/boards/som_mx93/rtos_examples/freertos_generic/armgcc/build_all.bat new file mode 100644 index 000000000..a16d8ae13 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_generic/armgcc/build_all.bat @@ -0,0 +1,15 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/som_mx93/rtos_examples/freertos_generic/armgcc/build_all.sh b/boards/som_mx93/rtos_examples/freertos_generic/armgcc/build_all.sh new file mode 100755 index 000000000..253693061 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_generic/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/rtos_examples/freertos_generic/armgcc/build_debug.bat b/boards/som_mx93/rtos_examples/freertos_generic/armgcc/build_debug.bat new file mode 100644 index 000000000..15123387e --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_generic/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/rtos_examples/freertos_generic/armgcc/build_debug.sh b/boards/som_mx93/rtos_examples/freertos_generic/armgcc/build_debug.sh new file mode 100755 index 000000000..42803761b --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_generic/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/rtos_examples/freertos_generic/armgcc/build_release.bat b/boards/som_mx93/rtos_examples/freertos_generic/armgcc/build_release.bat new file mode 100644 index 000000000..a88e3d668 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_generic/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/rtos_examples/freertos_generic/armgcc/build_release.sh b/boards/som_mx93/rtos_examples/freertos_generic/armgcc/build_release.sh new file mode 100755 index 000000000..47cfb057c --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_generic/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/rtos_examples/freertos_generic/armgcc/clean.bat b/boards/som_mx93/rtos_examples/freertos_generic/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_generic/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/rtos_examples/freertos_generic/armgcc/clean.sh b/boards/som_mx93/rtos_examples/freertos_generic/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_generic/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/rtos_examples/freertos_generic/armgcc/config.cmake b/boards/som_mx93/rtos_examples/freertos_generic/armgcc/config.cmake new file mode 100755 index 000000000..b228f064e --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_generic/armgcc/config.cmake @@ -0,0 +1,3 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_component_serial_manager_uart_MIMX9352 true) +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/rtos_examples/freertos_generic/armgcc/flags.cmake b/boards/som_mx93/rtos_examples/freertos_generic/armgcc/flags.cmake new file mode 100755 index 000000000..d76ba2bff --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_generic/armgcc/flags.cmake @@ -0,0 +1,191 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/rtos_examples/freertos_generic/board.c b/boards/som_mx93/rtos_examples/freertos_generic/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_generic/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/rtos_examples/freertos_generic/board.h b/boards/som_mx93/rtos_examples/freertos_generic/board.h new file mode 100644 index 000000000..5108807ef --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_generic/board.h @@ -0,0 +1,89 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + +/* ADP5585 */ +#define BOARD_ADP5585_I2C LPI2C2 +#define BOARD_ADP5585_I2C_ADDR (0x34U) +#define BOARD_ADP5585_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_ADP5585_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_ADP5585_I2C_CLOCK_ROOT) + +#define BOARD_ADP5585_PDM_MQS_SEL (2U) +#define BOARD_ADP5585_EXP_SEL (4U) +#define BOARD_ADP5585_CAN_STBY (8U) + +/* PCAL6524 */ +#define BOARD_PCAL6524_I2C LPI2C2 +#define BOARD_PCAL6524_I2C_ADDR (0x22U) +#define BOARD_PCAL6524_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_PCAL6524_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_PCAL6524_I2C_CLOCK_ROOT) + +#define BOARD_PCAL6524_ENET1_NRST (8U + 7U) +#define BOARD_PCAL6524_ENET2_NRST (16U + 0U) +#define BOARD_PCAL6524_MIC_CAN_SEL (16U + 1U) +#define BOARD_PCAL6524_EXP_SEL (16U + 6U) +#define BOARD_PCAL6524_CAN_STBY (16U + 7U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/rtos_examples/freertos_generic/clock_config.c b/boards/som_mx93/rtos_examples/freertos_generic/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_generic/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/rtos_examples/freertos_generic/clock_config.h b/boards/som_mx93/rtos_examples/freertos_generic/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_generic/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/rtos_examples/freertos_generic/freertos_generic.c b/boards/som_mx93/rtos_examples/freertos_generic/freertos_generic.c new file mode 100644 index 000000000..e16a474f7 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_generic/freertos_generic.c @@ -0,0 +1,393 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "semphr.h" + +/* TODO Add any manufacture supplied header files necessary for CMSIS functions +to be available here. */ +/* Freescale includes. */ +#include "fsl_device_registers.h" +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "board.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Priorities at which the tasks are created. The event semaphore task is +given the maximum priority of ( configMAX_PRIORITIES - 1 ) to ensure it runs as +soon as the semaphore is given. */ +#define mainQUEUE_RECEIVE_TASK_PRIORITY (tskIDLE_PRIORITY + 2) +#define mainQUEUE_SEND_TASK_PRIORITY (tskIDLE_PRIORITY + 1) +#define mainEVENT_SEMAPHORE_TASK_PRIORITY (configMAX_PRIORITIES - 1) + +/* The rate at which data is sent to the queue, specified in milliseconds, and +converted to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_PERIOD_MS (200 / portTICK_PERIOD_MS) + +/* The period of the example software timer, specified in milliseconds, and +converted to ticks using the portTICK_PERIOD_MS constant. */ +#define mainSOFTWARE_TIMER_PERIOD_MS (1000 / portTICK_PERIOD_MS) + +/* The number of items the queue can hold. This is 1 as the receive task +will remove items as they are added, meaning the send task should always find +the queue empty. */ +#define mainQUEUE_LENGTH (1) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/* + * The queue send and receive tasks as described in the comments at the top of + * this file. + */ +static void prvQueueReceiveTask(void *pvParameters); +static void prvQueueSendTask(void *pvParameters); + +/* + * The callback function assigned to the example software timer as described at + * the top of this file. + */ +static void vExampleTimerCallback(TimerHandle_t xTimer); + +/* + * The event semaphore task as described at the top of this file. + */ +static void prvEventSemaphoreTask(void *pvParameters); + +/******************************************************************************* + * Globals + ******************************************************************************/ +/* The queue used by the queue send and queue receive tasks. */ +static QueueHandle_t xQueue = NULL; + +/* The semaphore (in this case binary) that is used by the FreeRTOS tick hook + * function and the event semaphore task. + */ +static SemaphoreHandle_t xEventSemaphore = NULL; + +/* The counters used by the various examples. The usage is described in the + * comments at the top of this file. + */ +static volatile uint32_t ulCountOfTimerCallbackExecutions = 0; +static volatile uint32_t ulCountOfItemsReceivedOnQueue = 0; +static volatile uint32_t ulCountOfReceivedSemaphores = 0; + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief Main function + */ +int main(void) +{ + TimerHandle_t xExampleSoftwareTimer = NULL; + + /* Init board hardware. */ + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + + /* Create the queue used by the queue send and queue receive tasks. */ + xQueue = xQueueCreate(/* The number of items the queue can hold. */ + mainQUEUE_LENGTH, + /* The size of each item the queue holds. */ + sizeof(uint32_t)); + + /* Enable queue view in MCUX IDE FreeRTOS TAD plugin. */ + if (xQueue != NULL) + { + vQueueAddToRegistry(xQueue, "xQueue"); + } + + /* Create the semaphore used by the FreeRTOS tick hook function and the + event semaphore task. */ + vSemaphoreCreateBinary(xEventSemaphore); + + /* Create the queue receive task as described in the comments at the top + of this file. */ + if (xTaskCreate(/* The function that implements the task. */ + prvQueueReceiveTask, + /* Text name for the task, just to help debugging. */ + "Rx", + /* The size (in words) of the stack that should be created + for the task. */ + configMINIMAL_STACK_SIZE + 166, + /* A parameter that can be passed into the task. Not used + in this simple demo. */ + NULL, + /* The priority to assign to the task. tskIDLE_PRIORITY + (which is 0) is the lowest priority. configMAX_PRIORITIES - 1 + is the highest priority. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, + /* Used to obtain a handle to the created task. Not used in + this simple demo, so set to NULL. */ + NULL) != pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + while (1) + ; + } + + /* Create the queue send task in exactly the same way. Again, this is + described in the comments at the top of the file. */ + if (xTaskCreate(prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE + 166, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL) != + pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + while (1) + ; + } + + /* Create the task that is synchronised with an interrupt using the + xEventSemaphore semaphore. */ + if (xTaskCreate(prvEventSemaphoreTask, "Sem", configMINIMAL_STACK_SIZE + 166, NULL, + mainEVENT_SEMAPHORE_TASK_PRIORITY, NULL) != pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + while (1) + ; + } + + /* Create the software timer as described in the comments at the top of + this file. */ + xExampleSoftwareTimer = xTimerCreate(/* A text name, purely to help + debugging. */ + "LEDTimer", + /* The timer period, in this case + 1000ms (1s). */ + mainSOFTWARE_TIMER_PERIOD_MS, + /* This is a periodic timer, so + xAutoReload is set to pdTRUE. */ + pdTRUE, + /* The ID is not used, so can be set + to anything. */ + (void *)0, + /* The callback function that switches + the LED off. */ + vExampleTimerCallback); + + /* Start the created timer. A block time of zero is used as the timer + command queue cannot possibly be full here (this is the first timer to + be created, and it is not yet running). */ + xTimerStart(xExampleSoftwareTimer, 0); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following line + will never be reached. If the following line does execute, then there was + insufficient FreeRTOS heap memory available for the idle and/or timer tasks + to be created. See the memory management section on the FreeRTOS web site + for more details. */ + for (;;) + ; +} + +/*! + * @brief Timer callback. + */ +static void vExampleTimerCallback(TimerHandle_t xTimer) +{ + /* The timer has expired. Count the number of times this happens. The + timer that calls this function is an auto re-load timer, so it will + execute periodically. */ + ulCountOfTimerCallbackExecutions++; +} + +/*! + * @brief Task prvQueueSendTask periodically sending message. + */ +static void prvQueueSendTask(void *pvParameters) +{ + TickType_t xNextWakeTime; + const uint32_t ulValueToSend = 100UL; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for (;;) + { + /* Place this task in the blocked state until it is time to run again. + The block time is specified in ticks, the constant used converts ticks + to ms. While in the Blocked state this task will not consume any CPU + time. */ + vTaskDelayUntil(&xNextWakeTime, mainQUEUE_SEND_PERIOD_MS); + + /* Send to the queue - causing the queue receive task to unblock and + increment its counter. 0 is used as the block time so the sending + operation will not block - it shouldn't need to block as the queue + should always be empty at this point in the code. */ + xQueueSend(xQueue, &ulValueToSend, 0); + } +} + +/*! + * @brief Task prvQueueReceiveTask waiting for message. + */ +static void prvQueueReceiveTask(void *pvParameters) +{ + uint32_t ulReceivedValue; + + for (;;) + { + /* Wait until something arrives in the queue - this task will block + indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + FreeRTOSConfig.h. */ + xQueueReceive(xQueue, &ulReceivedValue, portMAX_DELAY); + + /* To get here something must have been received from the queue, but + is it the expected value? If it is, increment the counter. */ + if (ulReceivedValue == 100UL) + { + /* Count the number of items that have been received correctly. */ + ulCountOfItemsReceivedOnQueue++; + PRINTF("Receive message counter: %d.\r\n", ulCountOfItemsReceivedOnQueue); + } + } +} + +/*! + * @brief task prvEventSemaphoreTask is waiting for semaphore. + */ +static void prvEventSemaphoreTask(void *pvParameters) +{ + for (;;) + { + /* Block until the semaphore is 'given'. */ + if (xSemaphoreTake(xEventSemaphore, portMAX_DELAY) != pdTRUE) + { + PRINTF("Failed to take semaphore.\r\n"); + } + + /* Count the number of times the semaphore is received. */ + ulCountOfReceivedSemaphores++; + + PRINTF("Event task is running.\r\n"); + } +} + +/*! + * @brief tick hook is executed every tick. + */ +void vApplicationTickHook(void) +{ + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + static uint32_t ulCount = 0; + + /* The RTOS tick hook function is enabled by setting configUSE_TICK_HOOK to + 1 in FreeRTOSConfig.h. + + "Give" the semaphore on every 500th tick interrupt. */ + ulCount++; + if (ulCount >= 500UL) + { + /* This function is called from an interrupt context (the RTOS tick + interrupt), so only ISR safe API functions can be used (those that end + in "FromISR()". + + xHigherPriorityTaskWoken was initialised to pdFALSE, and will be set to + pdTRUE by xSemaphoreGiveFromISR() if giving the semaphore unblocked a + task that has equal or higher priority than the interrupted task. */ + xSemaphoreGiveFromISR(xEventSemaphore, &xHigherPriorityTaskWoken); + ulCount = 0UL; + } + + /* If xHigherPriorityTaskWoken is pdTRUE then a context switch should + normally be performed before leaving the interrupt (because during the + execution of the interrupt a task of equal or higher priority than the + running task was unblocked). The syntax required to context switch from + an interrupt is port dependent, so check the documentation of the port you + are using. + + In this case, the function is running in the context of the tick interrupt, + which will automatically check for the higher priority task to run anyway, + so no further action is required. */ +} + +/*! + * @brief Malloc failed hook. + */ +void vApplicationMallocFailedHook(void) +{ + /* The malloc failed hook is enabled by setting + configUSE_MALLOC_FAILED_HOOK to 1 in FreeRTOSConfig.h. + + Called if a call to pvPortMalloc() fails because there is insufficient + free memory available in the FreeRTOS heap. pvPortMalloc() is called + internally by FreeRTOS API functions that create tasks, queues, software + timers, and semaphores. The size of the FreeRTOS heap is set by the + configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + for (;;) + ; +} + +/*! + * @brief Stack overflow hook. + */ +void vApplicationStackOverflowHook(TaskHandle_t xTask, char *pcTaskName) +{ + (void)pcTaskName; + (void)xTask; + + /* Run time stack overflow checking is performed if + configconfigCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + function is called if a stack overflow is detected. pxCurrentTCB can be + inspected in the debugger if the task name passed into this function is + corrupt. */ + for (;;) + ; +} + +/*! + * @brief Idle hook. + */ +void vApplicationIdleHook(void) +{ + volatile size_t xFreeStackSpace; + + /* The idle task hook is enabled by setting configUSE_IDLE_HOOK to 1 in + FreeRTOSConfig.h. + + This function is called on each cycle of the idle task. In this case it + does nothing useful, other than report the amount of FreeRTOS heap that + remains unallocated. */ + xFreeStackSpace = xPortGetFreeHeapSize(); + + if (xFreeStackSpace > 100) + { + /* By now, the kernel has allocated everything it is going to, so + if there is a lot of heap remaining unallocated then + the value of configTOTAL_HEAP_SIZE in FreeRTOSConfig.h can be + reduced accordingly. */ + } +} diff --git a/boards/som_mx93/rtos_examples/freertos_generic/pin_mux.c b/boards/som_mx93/rtos_examples/freertos_generic/pin_mux.c new file mode 100644 index 000000000..4c8d6a119 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_generic/pin_mux.c @@ -0,0 +1,65 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/rtos_examples/freertos_generic/pin_mux.h b/boards/som_mx93/rtos_examples/freertos_generic/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_generic/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/rtos_examples/freertos_generic/readme.txt b/boards/som_mx93/rtos_examples/freertos_generic/readme.txt new file mode 100644 index 000000000..1e239aab0 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_generic/readme.txt @@ -0,0 +1,71 @@ +Overview +======== + +This document explains the freertos_generic example. It is based on code FreeRTOS documentation from +http://www.freertos.org/Hardware-independent-RTOS-example.html. It shows combination of several +tasks with queue, software timer, tick hook and semaphore. + +The example application creates three tasks. The prvQueueSendTask periodically sending data to +xQueue queue. The prvQueueReceiveTask is waiting for incoming message and counting number of +received messages. Task prvEventSemaphoreTask is waiting for xEventSemaphore semaphore given from +vApplicationTickHook. Tick hook give semaphore every 500 ms. + +Other hook types used for RTOS and resource statistics are also demonstrated in example: +* vApplicationIdleHook +* vApplicationStackOverflowHook +* vApplicationMallocFailedHook + + + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Micro USB cable +- USB to UART Adapter +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Proper power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + +Prepare the Demo +================ +1. Connect the power supply to the board and switch on the board. +2. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +3. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +After the board is flashed the Tera Term will start periodically printing the state of generic example. + +Example output: +Event task is running. +Receive message counter: 1. +Receive message counter: 2. +Receive message counter: 3. +Receive message counter: 4. +Receive message counter: 5. +Receive message counter: 6. +Receive message counter: 7. +Receive message counter: 8. +Receive message counter: 9. +Receive message counter: 10. +Receive message counter: 11. +Receive message counter: 12. +Event task is running. +Receive message counter: 13. +Receive message counter: 14. +... diff --git a/boards/som_mx93/rtos_examples/freertos_hello/FreeRTOSConfig.h b/boards/som_mx93/rtos_examples/freertos_hello/FreeRTOSConfig.h new file mode 100644 index 000000000..6f6bcf9da --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_hello/FreeRTOSConfig.h @@ -0,0 +1,182 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)200) +#define configMAX_PRIORITIES 5 +#define configMINIMAL_STACK_SIZE ((unsigned short)90) +#define configMAX_TASK_NAME_LEN 20 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 + +/* Used memory allocation (heap_x.c) */ +#define configFRTOS_MEMORY_SCHEME 4 +/* Tasks.c additions (e.g. Thread Aware Debug capability) */ +#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE ((size_t)(10 * 1024)) +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Task aware debugging. */ +#define configRECORD_STACK_HIGH_ADDRESS 1 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +/* Define to trap errors during development. */ +#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + + + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) + /* Clock manager provides in this variable system core clock frequency */ + #include + extern uint32_t SystemCoreClock; +#endif + + +#ifndef configENABLE_FPU + #define configENABLE_FPU 1 +#endif +#ifndef configENABLE_MPU + #define configENABLE_MPU 0 +#endif +#ifndef configENABLE_TRUSTZONE + #define configENABLE_TRUSTZONE 0 +#endif +#ifndef configRUN_FREERTOS_SECURE_ONLY + #define configRUN_FREERTOS_SECURE_ONLY 1 +#endif + +/* Redefine: Mutex is needed for SRTM communication */ +#undef configUSE_MUTEXES +#define configUSE_MUTEXES 1 + +#ifndef configTOTAL_HEAP_SIZE +#define configTOTAL_HEAP_SIZE ((size_t)(40 * 1024)) +#endif + +/* Interrupt nesting behaviour configuration. Cortex-M specific. */ +#ifdef __NVIC_PRIO_BITS +/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ +#define configPRIO_BITS __NVIC_PRIO_BITS +#else +#define configPRIO_BITS 3 /* 7 priority levels */ +#endif + +#define configSTACK_DEPTH_TYPE uint32_t + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define vPortPendSVHandler PendSV_Handler +#define vPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ diff --git a/boards/som_mx93/rtos_examples/freertos_hello/armgcc/CMakeLists.txt b/boards/som_mx93/rtos_examples/freertos_hello/armgcc/CMakeLists.txt new file mode 100644 index 000000000..00b69a506 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_hello/armgcc/CMakeLists.txt @@ -0,0 +1,121 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(freertos_hello) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME freertos_hello.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../freertos_hello.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../FreeRTOSConfig.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/rtos/freertos/freertos-kernel + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/serial_manager + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(middleware_freertos-kernel_cm33_nonsecure_port_MIMX9352) + +include(driver_clock_MIMX9352) + +include(middleware_freertos-kernel_heap_4_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(utility_debug_console_MIMX9352) + +include(utility_assert_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_serial_manager_MIMX9352) + +include(component_lists_MIMX9352) + +include(component_serial_manager_uart_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(middleware_freertos-kernel_MIMX9352) + +include(middleware_freertos-kernel_extension_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/rtos_examples/freertos_hello/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/rtos_examples/freertos_hello/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_hello/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/rtos_examples/freertos_hello/armgcc/build_all.bat b/boards/som_mx93/rtos_examples/freertos_hello/armgcc/build_all.bat new file mode 100644 index 000000000..a16d8ae13 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_hello/armgcc/build_all.bat @@ -0,0 +1,15 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/som_mx93/rtos_examples/freertos_hello/armgcc/build_all.sh b/boards/som_mx93/rtos_examples/freertos_hello/armgcc/build_all.sh new file mode 100755 index 000000000..253693061 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_hello/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/rtos_examples/freertos_hello/armgcc/build_debug.bat b/boards/som_mx93/rtos_examples/freertos_hello/armgcc/build_debug.bat new file mode 100644 index 000000000..15123387e --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_hello/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/rtos_examples/freertos_hello/armgcc/build_debug.sh b/boards/som_mx93/rtos_examples/freertos_hello/armgcc/build_debug.sh new file mode 100755 index 000000000..42803761b --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_hello/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/rtos_examples/freertos_hello/armgcc/build_release.bat b/boards/som_mx93/rtos_examples/freertos_hello/armgcc/build_release.bat new file mode 100644 index 000000000..a88e3d668 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_hello/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/rtos_examples/freertos_hello/armgcc/build_release.sh b/boards/som_mx93/rtos_examples/freertos_hello/armgcc/build_release.sh new file mode 100755 index 000000000..47cfb057c --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_hello/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/rtos_examples/freertos_hello/armgcc/clean.bat b/boards/som_mx93/rtos_examples/freertos_hello/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_hello/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/rtos_examples/freertos_hello/armgcc/clean.sh b/boards/som_mx93/rtos_examples/freertos_hello/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_hello/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/rtos_examples/freertos_hello/armgcc/config.cmake b/boards/som_mx93/rtos_examples/freertos_hello/armgcc/config.cmake new file mode 100755 index 000000000..b228f064e --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_hello/armgcc/config.cmake @@ -0,0 +1,3 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_component_serial_manager_uart_MIMX9352 true) +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/rtos_examples/freertos_hello/armgcc/flags.cmake b/boards/som_mx93/rtos_examples/freertos_hello/armgcc/flags.cmake new file mode 100755 index 000000000..d76ba2bff --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_hello/armgcc/flags.cmake @@ -0,0 +1,191 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/rtos_examples/freertos_hello/board.c b/boards/som_mx93/rtos_examples/freertos_hello/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_hello/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/rtos_examples/freertos_hello/board.h b/boards/som_mx93/rtos_examples/freertos_hello/board.h new file mode 100644 index 000000000..5108807ef --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_hello/board.h @@ -0,0 +1,89 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + +/* ADP5585 */ +#define BOARD_ADP5585_I2C LPI2C2 +#define BOARD_ADP5585_I2C_ADDR (0x34U) +#define BOARD_ADP5585_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_ADP5585_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_ADP5585_I2C_CLOCK_ROOT) + +#define BOARD_ADP5585_PDM_MQS_SEL (2U) +#define BOARD_ADP5585_EXP_SEL (4U) +#define BOARD_ADP5585_CAN_STBY (8U) + +/* PCAL6524 */ +#define BOARD_PCAL6524_I2C LPI2C2 +#define BOARD_PCAL6524_I2C_ADDR (0x22U) +#define BOARD_PCAL6524_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_PCAL6524_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_PCAL6524_I2C_CLOCK_ROOT) + +#define BOARD_PCAL6524_ENET1_NRST (8U + 7U) +#define BOARD_PCAL6524_ENET2_NRST (16U + 0U) +#define BOARD_PCAL6524_MIC_CAN_SEL (16U + 1U) +#define BOARD_PCAL6524_EXP_SEL (16U + 6U) +#define BOARD_PCAL6524_CAN_STBY (16U + 7U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/rtos_examples/freertos_hello/clock_config.c b/boards/som_mx93/rtos_examples/freertos_hello/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_hello/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/rtos_examples/freertos_hello/clock_config.h b/boards/som_mx93/rtos_examples/freertos_hello/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_hello/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/rtos_examples/freertos_hello/freertos_hello.c b/boards/som_mx93/rtos_examples/freertos_hello/freertos_hello.c new file mode 100644 index 000000000..c1152cf11 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_hello/freertos_hello.c @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* FreeRTOS kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" + +/* Freescale includes. */ +#include "fsl_device_registers.h" +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "board.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Task priorities. */ +#define hello_task_PRIORITY (configMAX_PRIORITIES - 1) +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static void hello_task(void *pvParameters); + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief Application entry point. + */ +int main(void) +{ + /* Init board hardware. */ + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + if (xTaskCreate(hello_task, "Hello_task", configMINIMAL_STACK_SIZE + 100, NULL, hello_task_PRIORITY, NULL) != + pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + while (1) + ; + } + vTaskStartScheduler(); + for (;;) + ; +} + +/*! + * @brief Task responsible for printing of "Hello world." message. + */ +static void hello_task(void *pvParameters) +{ + for (;;) + { + PRINTF("Hello world.\r\n"); + vTaskSuspend(NULL); + } +} diff --git a/boards/som_mx93/rtos_examples/freertos_hello/pin_mux.c b/boards/som_mx93/rtos_examples/freertos_hello/pin_mux.c new file mode 100644 index 000000000..4c8d6a119 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_hello/pin_mux.c @@ -0,0 +1,65 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/rtos_examples/freertos_hello/pin_mux.h b/boards/som_mx93/rtos_examples/freertos_hello/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_hello/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/rtos_examples/freertos_hello/readme.txt b/boards/som_mx93/rtos_examples/freertos_hello/readme.txt new file mode 100644 index 000000000..75b8050fe --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_hello/readme.txt @@ -0,0 +1,48 @@ +Overview +======== +The Hello World project is a simple demonstration program that uses the SDK UART drivere in +combination with FreeRTOS. The purpose of this demo is to show how to use the debug console and to +provide a simple project for debugging and further development. + +The example application creates one task called hello_task. This task print "Hello world." message +via debug console utility and suspend itself. + + + + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Micro USB cable +- USB to UART Adapter +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Proper power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + +Prepare the Demo +================ +1. Connect the power supply to the board and switch on the board. +2. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +3. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +After the board is flashed the Tera Term will print "Hello world" message on terminal. + +Example output: +Hello world. diff --git a/boards/som_mx93/rtos_examples/freertos_mutex/FreeRTOSConfig.h b/boards/som_mx93/rtos_examples/freertos_mutex/FreeRTOSConfig.h new file mode 100644 index 000000000..6f6bcf9da --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_mutex/FreeRTOSConfig.h @@ -0,0 +1,182 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)200) +#define configMAX_PRIORITIES 5 +#define configMINIMAL_STACK_SIZE ((unsigned short)90) +#define configMAX_TASK_NAME_LEN 20 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 + +/* Used memory allocation (heap_x.c) */ +#define configFRTOS_MEMORY_SCHEME 4 +/* Tasks.c additions (e.g. Thread Aware Debug capability) */ +#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE ((size_t)(10 * 1024)) +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Task aware debugging. */ +#define configRECORD_STACK_HIGH_ADDRESS 1 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +/* Define to trap errors during development. */ +#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + + + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) + /* Clock manager provides in this variable system core clock frequency */ + #include + extern uint32_t SystemCoreClock; +#endif + + +#ifndef configENABLE_FPU + #define configENABLE_FPU 1 +#endif +#ifndef configENABLE_MPU + #define configENABLE_MPU 0 +#endif +#ifndef configENABLE_TRUSTZONE + #define configENABLE_TRUSTZONE 0 +#endif +#ifndef configRUN_FREERTOS_SECURE_ONLY + #define configRUN_FREERTOS_SECURE_ONLY 1 +#endif + +/* Redefine: Mutex is needed for SRTM communication */ +#undef configUSE_MUTEXES +#define configUSE_MUTEXES 1 + +#ifndef configTOTAL_HEAP_SIZE +#define configTOTAL_HEAP_SIZE ((size_t)(40 * 1024)) +#endif + +/* Interrupt nesting behaviour configuration. Cortex-M specific. */ +#ifdef __NVIC_PRIO_BITS +/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ +#define configPRIO_BITS __NVIC_PRIO_BITS +#else +#define configPRIO_BITS 3 /* 7 priority levels */ +#endif + +#define configSTACK_DEPTH_TYPE uint32_t + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define vPortPendSVHandler PendSV_Handler +#define vPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ diff --git a/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/CMakeLists.txt b/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/CMakeLists.txt new file mode 100644 index 000000000..ac9ac2028 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/CMakeLists.txt @@ -0,0 +1,121 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(freertos_mutex) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME freertos_mutex.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../freertos_mutex.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../FreeRTOSConfig.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/rtos/freertos/freertos-kernel + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/serial_manager + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(middleware_freertos-kernel_cm33_nonsecure_port_MIMX9352) + +include(driver_clock_MIMX9352) + +include(middleware_freertos-kernel_heap_4_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(utility_debug_console_MIMX9352) + +include(utility_assert_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_serial_manager_MIMX9352) + +include(component_lists_MIMX9352) + +include(component_serial_manager_uart_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(middleware_freertos-kernel_MIMX9352) + +include(middleware_freertos-kernel_extension_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/build_all.bat b/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/build_all.bat new file mode 100644 index 000000000..a16d8ae13 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/build_all.bat @@ -0,0 +1,15 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/build_all.sh b/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/build_all.sh new file mode 100755 index 000000000..253693061 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/build_debug.bat b/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/build_debug.bat new file mode 100644 index 000000000..15123387e --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/build_debug.sh b/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/build_debug.sh new file mode 100755 index 000000000..42803761b --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/build_release.bat b/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/build_release.bat new file mode 100644 index 000000000..a88e3d668 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/build_release.sh b/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/build_release.sh new file mode 100755 index 000000000..47cfb057c --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/clean.bat b/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/clean.sh b/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/config.cmake b/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/config.cmake new file mode 100755 index 000000000..b228f064e --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/config.cmake @@ -0,0 +1,3 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_component_serial_manager_uart_MIMX9352 true) +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/flags.cmake b/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/flags.cmake new file mode 100755 index 000000000..d76ba2bff --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_mutex/armgcc/flags.cmake @@ -0,0 +1,191 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/rtos_examples/freertos_mutex/board.c b/boards/som_mx93/rtos_examples/freertos_mutex/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_mutex/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/rtos_examples/freertos_mutex/board.h b/boards/som_mx93/rtos_examples/freertos_mutex/board.h new file mode 100644 index 000000000..5108807ef --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_mutex/board.h @@ -0,0 +1,89 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + +/* ADP5585 */ +#define BOARD_ADP5585_I2C LPI2C2 +#define BOARD_ADP5585_I2C_ADDR (0x34U) +#define BOARD_ADP5585_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_ADP5585_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_ADP5585_I2C_CLOCK_ROOT) + +#define BOARD_ADP5585_PDM_MQS_SEL (2U) +#define BOARD_ADP5585_EXP_SEL (4U) +#define BOARD_ADP5585_CAN_STBY (8U) + +/* PCAL6524 */ +#define BOARD_PCAL6524_I2C LPI2C2 +#define BOARD_PCAL6524_I2C_ADDR (0x22U) +#define BOARD_PCAL6524_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_PCAL6524_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_PCAL6524_I2C_CLOCK_ROOT) + +#define BOARD_PCAL6524_ENET1_NRST (8U + 7U) +#define BOARD_PCAL6524_ENET2_NRST (16U + 0U) +#define BOARD_PCAL6524_MIC_CAN_SEL (16U + 1U) +#define BOARD_PCAL6524_EXP_SEL (16U + 6U) +#define BOARD_PCAL6524_CAN_STBY (16U + 7U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/rtos_examples/freertos_mutex/clock_config.c b/boards/som_mx93/rtos_examples/freertos_mutex/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_mutex/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/rtos_examples/freertos_mutex/clock_config.h b/boards/som_mx93/rtos_examples/freertos_mutex/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_mutex/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/rtos_examples/freertos_mutex/freertos_mutex.c b/boards/som_mx93/rtos_examples/freertos_mutex/freertos_mutex.c new file mode 100644 index 000000000..3c5e31ba5 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_mutex/freertos_mutex.c @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "semphr.h" + +/* Freescale includes. */ +#include "fsl_device_registers.h" +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "board.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +SemaphoreHandle_t xMutex; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static void write_task_1(void *pvParameters); +static void write_task_2(void *pvParameters); + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief Main function + */ +int main(void) +{ + xMutex = xSemaphoreCreateMutex(); + + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + if (xTaskCreate(write_task_1, "WRITE_TASK_1", configMINIMAL_STACK_SIZE + 128, NULL, tskIDLE_PRIORITY + 1, NULL) != + pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + while (1) + ; + } + if (xTaskCreate(write_task_2, "WRITE_TASK_2", configMINIMAL_STACK_SIZE + 128, NULL, tskIDLE_PRIORITY + 1, NULL) != + pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + while (1) + ; + } + /* Start scheduling. */ + vTaskStartScheduler(); + for (;;) + ; +} + +/*! + * @brief Write Task 1 function + */ +static void write_task_1(void *pvParameters) +{ + while (1) + { + if (xSemaphoreTake(xMutex, portMAX_DELAY) != pdTRUE) + { + PRINTF("Failed to take semaphore.\r\n"); + } + PRINTF("ABCD |"); + taskYIELD(); + PRINTF(" EFGH\r\n"); + xSemaphoreGive(xMutex); + taskYIELD(); + } +} + +/*! + * @brief Write Task 2 function + */ +static void write_task_2(void *pvParameters) +{ + while (1) + { + if (xSemaphoreTake(xMutex, portMAX_DELAY) != pdTRUE) + { + PRINTF("Failed to take semaphore.\r\n"); + } + PRINTF("1234 |"); + taskYIELD(); + PRINTF(" 5678\r\n"); + xSemaphoreGive(xMutex); + taskYIELD(); + } +} diff --git a/boards/som_mx93/rtos_examples/freertos_mutex/pin_mux.c b/boards/som_mx93/rtos_examples/freertos_mutex/pin_mux.c new file mode 100644 index 000000000..4c8d6a119 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_mutex/pin_mux.c @@ -0,0 +1,65 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/rtos_examples/freertos_mutex/pin_mux.h b/boards/som_mx93/rtos_examples/freertos_mutex/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_mutex/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/rtos_examples/freertos_mutex/readme.txt b/boards/som_mx93/rtos_examples/freertos_mutex/readme.txt new file mode 100644 index 000000000..66e1bded1 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_mutex/readme.txt @@ -0,0 +1,59 @@ +Overview +======== +This document explains the freertos_mutex example. It shows how mutex manage access to common +resource (terminal output). + +The example application creates two identical instances of write_task. Each task will lock the mutex +before printing and unlock it after printing to ensure that the outputs from tasks are not mixed +together. + +The test_task accept output message during creation as function parameter. Output message have two +parts. If xMutex is unlocked, the write_task_1 acquire xMutex and print first part of message. Then +rescheduling is performed. In this moment scheduler check if some other task could run, but second +task write_task+_2 is blocked because xMutex is already locked by first write task. The first +write_task_1 continue from last point by printing of second message part. Finaly the xMutex is +unlocked and second instance of write_task_2 is executed. + + + + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Micro USB cable +- USB to UART Adapter +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Proper power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + +Prepare the Demo +================ +1. Connect the power supply to the board and switch on the board. +2. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +3. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +After the board is flashed the Tera Term will start periodically printing strings synchronized by +mutex. + +Example output: +"ABCD | EFGH" +"1234 | 5678" +"ABCD | EFGH" +"1234 | 5678" diff --git a/boards/som_mx93/rtos_examples/freertos_queue/FreeRTOSConfig.h b/boards/som_mx93/rtos_examples/freertos_queue/FreeRTOSConfig.h new file mode 100644 index 000000000..b1d6c4a2a --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_queue/FreeRTOSConfig.h @@ -0,0 +1,181 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)200) +#define configMAX_PRIORITIES 5 +#define configMINIMAL_STACK_SIZE ((unsigned short)90) +#define configMAX_TASK_NAME_LEN 20 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 + +/* Used memory allocation (heap_x.c) */ +#define configFRTOS_MEMORY_SCHEME 4 +/* Tasks.c additions (e.g. Thread Aware Debug capability) */ +#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE ((size_t)(10 * 1024)) +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Task aware debugging. */ +#define configRECORD_STACK_HIGH_ADDRESS 1 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + + + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) + /* Clock manager provides in this variable system core clock frequency */ + #include + extern uint32_t SystemCoreClock; +#endif + + +#ifndef configENABLE_FPU + #define configENABLE_FPU 1 +#endif +#ifndef configENABLE_MPU + #define configENABLE_MPU 0 +#endif +#ifndef configENABLE_TRUSTZONE + #define configENABLE_TRUSTZONE 0 +#endif +#ifndef configRUN_FREERTOS_SECURE_ONLY + #define configRUN_FREERTOS_SECURE_ONLY 1 +#endif + +/* Redefine: Mutex is needed for SRTM communication */ +#undef configUSE_MUTEXES +#define configUSE_MUTEXES 1 + +#ifndef configTOTAL_HEAP_SIZE +#define configTOTAL_HEAP_SIZE ((size_t)(40 * 1024)) +#endif + +/* Interrupt nesting behaviour configuration. Cortex-M specific. */ +#ifdef __NVIC_PRIO_BITS +/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ +#define configPRIO_BITS __NVIC_PRIO_BITS +#else +#define configPRIO_BITS 3 /* 7 priority levels */ +#endif + +#define configSTACK_DEPTH_TYPE uint32_t + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define vPortPendSVHandler PendSV_Handler +#define vPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ diff --git a/boards/som_mx93/rtos_examples/freertos_queue/armgcc/CMakeLists.txt b/boards/som_mx93/rtos_examples/freertos_queue/armgcc/CMakeLists.txt new file mode 100644 index 000000000..175f33f6a --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_queue/armgcc/CMakeLists.txt @@ -0,0 +1,121 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(freertos_queue) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME freertos_queue.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../freertos_queue.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../FreeRTOSConfig.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/rtos/freertos/freertos-kernel + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/serial_manager + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(middleware_freertos-kernel_cm33_nonsecure_port_MIMX9352) + +include(driver_clock_MIMX9352) + +include(middleware_freertos-kernel_heap_4_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(utility_debug_console_MIMX9352) + +include(utility_assert_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_serial_manager_MIMX9352) + +include(component_lists_MIMX9352) + +include(component_serial_manager_uart_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(middleware_freertos-kernel_MIMX9352) + +include(middleware_freertos-kernel_extension_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/rtos_examples/freertos_queue/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/rtos_examples/freertos_queue/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_queue/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/rtos_examples/freertos_queue/armgcc/build_all.bat b/boards/som_mx93/rtos_examples/freertos_queue/armgcc/build_all.bat new file mode 100644 index 000000000..a16d8ae13 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_queue/armgcc/build_all.bat @@ -0,0 +1,15 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/som_mx93/rtos_examples/freertos_queue/armgcc/build_all.sh b/boards/som_mx93/rtos_examples/freertos_queue/armgcc/build_all.sh new file mode 100755 index 000000000..253693061 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_queue/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/rtos_examples/freertos_queue/armgcc/build_debug.bat b/boards/som_mx93/rtos_examples/freertos_queue/armgcc/build_debug.bat new file mode 100644 index 000000000..15123387e --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_queue/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/rtos_examples/freertos_queue/armgcc/build_debug.sh b/boards/som_mx93/rtos_examples/freertos_queue/armgcc/build_debug.sh new file mode 100755 index 000000000..42803761b --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_queue/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/rtos_examples/freertos_queue/armgcc/build_release.bat b/boards/som_mx93/rtos_examples/freertos_queue/armgcc/build_release.bat new file mode 100644 index 000000000..a88e3d668 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_queue/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/rtos_examples/freertos_queue/armgcc/build_release.sh b/boards/som_mx93/rtos_examples/freertos_queue/armgcc/build_release.sh new file mode 100755 index 000000000..47cfb057c --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_queue/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/rtos_examples/freertos_queue/armgcc/clean.bat b/boards/som_mx93/rtos_examples/freertos_queue/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_queue/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/rtos_examples/freertos_queue/armgcc/clean.sh b/boards/som_mx93/rtos_examples/freertos_queue/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_queue/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/rtos_examples/freertos_queue/armgcc/config.cmake b/boards/som_mx93/rtos_examples/freertos_queue/armgcc/config.cmake new file mode 100755 index 000000000..b228f064e --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_queue/armgcc/config.cmake @@ -0,0 +1,3 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_component_serial_manager_uart_MIMX9352 true) +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/rtos_examples/freertos_queue/armgcc/flags.cmake b/boards/som_mx93/rtos_examples/freertos_queue/armgcc/flags.cmake new file mode 100755 index 000000000..d76ba2bff --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_queue/armgcc/flags.cmake @@ -0,0 +1,191 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/rtos_examples/freertos_queue/board.c b/boards/som_mx93/rtos_examples/freertos_queue/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_queue/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/rtos_examples/freertos_queue/board.h b/boards/som_mx93/rtos_examples/freertos_queue/board.h new file mode 100644 index 000000000..5108807ef --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_queue/board.h @@ -0,0 +1,89 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + +/* ADP5585 */ +#define BOARD_ADP5585_I2C LPI2C2 +#define BOARD_ADP5585_I2C_ADDR (0x34U) +#define BOARD_ADP5585_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_ADP5585_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_ADP5585_I2C_CLOCK_ROOT) + +#define BOARD_ADP5585_PDM_MQS_SEL (2U) +#define BOARD_ADP5585_EXP_SEL (4U) +#define BOARD_ADP5585_CAN_STBY (8U) + +/* PCAL6524 */ +#define BOARD_PCAL6524_I2C LPI2C2 +#define BOARD_PCAL6524_I2C_ADDR (0x22U) +#define BOARD_PCAL6524_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_PCAL6524_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_PCAL6524_I2C_CLOCK_ROOT) + +#define BOARD_PCAL6524_ENET1_NRST (8U + 7U) +#define BOARD_PCAL6524_ENET2_NRST (16U + 0U) +#define BOARD_PCAL6524_MIC_CAN_SEL (16U + 1U) +#define BOARD_PCAL6524_EXP_SEL (16U + 6U) +#define BOARD_PCAL6524_CAN_STBY (16U + 7U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/rtos_examples/freertos_queue/clock_config.c b/boards/som_mx93/rtos_examples/freertos_queue/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_queue/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/rtos_examples/freertos_queue/clock_config.h b/boards/som_mx93/rtos_examples/freertos_queue/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_queue/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/rtos_examples/freertos_queue/freertos_queue.c b/boards/som_mx93/rtos_examples/freertos_queue/freertos_queue.c new file mode 100644 index 000000000..e1867e5de --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_queue/freertos_queue.c @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*System includes.*/ +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" + +/* Freescale includes. */ +#include "fsl_device_registers.h" +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "board.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define MAX_LOG_LENGTH 20 +/******************************************************************************* + * Globals + ******************************************************************************/ +/* Logger queue handle */ +static QueueHandle_t log_queue = NULL; +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/* Application API */ +static void write_task_1(void *pvParameters); +static void write_task_2(void *pvParameters); + +/* Logger API */ +void log_add(char *log); +void log_init(uint32_t queue_length, uint32_t max_log_lenght); +static void log_task(void *pvParameters); +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * @brief Main function + */ +int main(void) +{ + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + /* Initialize logger for 10 logs with maximum lenght of one log 20 B */ + log_init(10, MAX_LOG_LENGTH); + if (xTaskCreate(write_task_1, "WRITE_TASK_1", configMINIMAL_STACK_SIZE + 166, NULL, tskIDLE_PRIORITY + 2, NULL) != + pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + while (1) + ; + } + if (xTaskCreate(write_task_2, "WRITE_TASK_2", configMINIMAL_STACK_SIZE + 166, NULL, tskIDLE_PRIORITY + 2, NULL) != + pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + while (1) + ; + } + vTaskStartScheduler(); + for (;;) + ; +} + +/******************************************************************************* + * Application functions + ******************************************************************************/ +/*! + * @brief write_task_1 function + */ +static void write_task_1(void *pvParameters) +{ + char log[MAX_LOG_LENGTH + 1]; + uint32_t i = 0; + for (i = 0; i < 5; i++) + { + sprintf(log, "Task1 Message %d", (int)i); + log_add(log); + taskYIELD(); + } + vTaskSuspend(NULL); +} + +/*! + * @brief write_task_2 function + */ +static void write_task_2(void *pvParameters) +{ + char log[MAX_LOG_LENGTH + 1]; + uint32_t i = 0; + for (i = 0; i < 5; i++) + { + sprintf(log, "Task2 Message %d", (int)i); + log_add(log); + taskYIELD(); + } + vTaskSuspend(NULL); +} + +/******************************************************************************* + * Logger functions + ******************************************************************************/ +/*! + * @brief log_add function + */ +void log_add(char *log) +{ + xQueueSend(log_queue, log, 0); +} + +/*! + * @brief log_init function + */ +void log_init(uint32_t queue_length, uint32_t max_log_lenght) +{ + log_queue = xQueueCreate(queue_length, max_log_lenght); + /* Enable queue view in MCUX IDE FreeRTOS TAD plugin. */ + if (log_queue != NULL) + { + vQueueAddToRegistry(log_queue, "LogQ"); + } + if (xTaskCreate(log_task, "log_task", configMINIMAL_STACK_SIZE + 166, NULL, tskIDLE_PRIORITY + 1, NULL) != pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + while (1) + ; + } +} + +/*! + * @brief log_print_task function + */ +static void log_task(void *pvParameters) +{ + uint32_t counter = 0; + char log[MAX_LOG_LENGTH + 1]; + while (1) + { + if (xQueueReceive(log_queue, log, portMAX_DELAY) != pdTRUE) + { + PRINTF("Failed to receive queue.\r\n"); + } + PRINTF("Log %d: %s\r\n", counter, log); + counter++; + } +} diff --git a/boards/som_mx93/rtos_examples/freertos_queue/pin_mux.c b/boards/som_mx93/rtos_examples/freertos_queue/pin_mux.c new file mode 100644 index 000000000..4c8d6a119 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_queue/pin_mux.c @@ -0,0 +1,65 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/rtos_examples/freertos_queue/pin_mux.h b/boards/som_mx93/rtos_examples/freertos_queue/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_queue/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/rtos_examples/freertos_queue/readme.txt b/boards/som_mx93/rtos_examples/freertos_queue/readme.txt new file mode 100644 index 000000000..80b3c3af3 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_queue/readme.txt @@ -0,0 +1,62 @@ +Overview +======== + +This document explains the freertos_queue example. This example introduce simple logging mechanism +based on message passing. + +Example could be devided in two parts. First part is logger. It contain three tasks: +log_add().....Add new message into the log. Call xQueueSend function to pass new message into + message queue. +log_init()....Initialize logger (create logging task and message queue log_queue). +log_task()....Task responsible for printing of log output. + +Second part is application of this simple logging mechanism. Each of two tasks write_task_1 and +write_task_2 print 5 messages into log. + + + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Micro USB cable +- USB to UART Adapter +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Proper power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + +Prepare the Demo +================ +1. Connect the power supply to the board and switch on the board. +2. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +3. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +After the board is flashed the Tera Term will show debug console output. + +Example output: +Log 0: Task1 Message 0 +Log 1: Task2 Message 0 +Log 2: Task1 Message 1 +Log 3: Task2 Message 1 +Log 4: Task1 Message 2 +Log 5: Task2 Message 2 +Log 6: Task1 Message 3 +Log 7: Task2 Message 3 +Log 8: Task1 Message 4 +Log 9: Task2 Message 4 diff --git a/boards/som_mx93/rtos_examples/freertos_sem/FreeRTOSConfig.h b/boards/som_mx93/rtos_examples/freertos_sem/FreeRTOSConfig.h new file mode 100644 index 000000000..9616235cf --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_sem/FreeRTOSConfig.h @@ -0,0 +1,182 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)200) +#define configMAX_PRIORITIES 5 +#define configMINIMAL_STACK_SIZE ((unsigned short)90) +#define configMAX_TASK_NAME_LEN 20 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 + +/* Used memory allocation (heap_x.c) */ +#define configFRTOS_MEMORY_SCHEME 4 +/* Tasks.c additions (e.g. Thread Aware Debug capability) */ +#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE ((size_t)(10 * 1024)) +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Task aware debugging. */ +#define configRECORD_STACK_HIGH_ADDRESS 1 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +/* Define to trap errors during development. */ +#define configASSERT(x) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + + + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) + /* Clock manager provides in this variable system core clock frequency */ + #include + extern uint32_t SystemCoreClock; +#endif + + +#ifndef configENABLE_FPU + #define configENABLE_FPU 1 +#endif +#ifndef configENABLE_MPU + #define configENABLE_MPU 0 +#endif +#ifndef configENABLE_TRUSTZONE + #define configENABLE_TRUSTZONE 0 +#endif +#ifndef configRUN_FREERTOS_SECURE_ONLY + #define configRUN_FREERTOS_SECURE_ONLY 1 +#endif + +/* Redefine: Mutex is needed for SRTM communication */ +#undef configUSE_MUTEXES +#define configUSE_MUTEXES 1 + +#ifndef configTOTAL_HEAP_SIZE +#define configTOTAL_HEAP_SIZE ((size_t)(40 * 1024)) +#endif + +/* Interrupt nesting behaviour configuration. Cortex-M specific. */ +#ifdef __NVIC_PRIO_BITS +/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ +#define configPRIO_BITS __NVIC_PRIO_BITS +#else +#define configPRIO_BITS 3 /* 7 priority levels */ +#endif + +#define configSTACK_DEPTH_TYPE uint32_t + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define vPortPendSVHandler PendSV_Handler +#define vPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ diff --git a/boards/som_mx93/rtos_examples/freertos_sem/armgcc/CMakeLists.txt b/boards/som_mx93/rtos_examples/freertos_sem/armgcc/CMakeLists.txt new file mode 100644 index 000000000..03c78fabf --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_sem/armgcc/CMakeLists.txt @@ -0,0 +1,121 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(freertos_sem) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME freertos_sem.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../freertos_sem.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../FreeRTOSConfig.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/rtos/freertos/freertos-kernel + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/serial_manager + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(middleware_freertos-kernel_cm33_nonsecure_port_MIMX9352) + +include(driver_clock_MIMX9352) + +include(middleware_freertos-kernel_heap_4_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(utility_debug_console_MIMX9352) + +include(utility_assert_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_serial_manager_MIMX9352) + +include(component_lists_MIMX9352) + +include(component_serial_manager_uart_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(middleware_freertos-kernel_MIMX9352) + +include(middleware_freertos-kernel_extension_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/rtos_examples/freertos_sem/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/rtos_examples/freertos_sem/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_sem/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/rtos_examples/freertos_sem/armgcc/build_all.bat b/boards/som_mx93/rtos_examples/freertos_sem/armgcc/build_all.bat new file mode 100644 index 000000000..a16d8ae13 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_sem/armgcc/build_all.bat @@ -0,0 +1,15 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/som_mx93/rtos_examples/freertos_sem/armgcc/build_all.sh b/boards/som_mx93/rtos_examples/freertos_sem/armgcc/build_all.sh new file mode 100755 index 000000000..253693061 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_sem/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/rtos_examples/freertos_sem/armgcc/build_debug.bat b/boards/som_mx93/rtos_examples/freertos_sem/armgcc/build_debug.bat new file mode 100644 index 000000000..15123387e --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_sem/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/rtos_examples/freertos_sem/armgcc/build_debug.sh b/boards/som_mx93/rtos_examples/freertos_sem/armgcc/build_debug.sh new file mode 100755 index 000000000..42803761b --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_sem/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/rtos_examples/freertos_sem/armgcc/build_release.bat b/boards/som_mx93/rtos_examples/freertos_sem/armgcc/build_release.bat new file mode 100644 index 000000000..a88e3d668 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_sem/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/rtos_examples/freertos_sem/armgcc/build_release.sh b/boards/som_mx93/rtos_examples/freertos_sem/armgcc/build_release.sh new file mode 100755 index 000000000..47cfb057c --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_sem/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/rtos_examples/freertos_sem/armgcc/clean.bat b/boards/som_mx93/rtos_examples/freertos_sem/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_sem/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/rtos_examples/freertos_sem/armgcc/clean.sh b/boards/som_mx93/rtos_examples/freertos_sem/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_sem/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/rtos_examples/freertos_sem/armgcc/config.cmake b/boards/som_mx93/rtos_examples/freertos_sem/armgcc/config.cmake new file mode 100755 index 000000000..b228f064e --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_sem/armgcc/config.cmake @@ -0,0 +1,3 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_component_serial_manager_uart_MIMX9352 true) +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/rtos_examples/freertos_sem/armgcc/flags.cmake b/boards/som_mx93/rtos_examples/freertos_sem/armgcc/flags.cmake new file mode 100755 index 000000000..d76ba2bff --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_sem/armgcc/flags.cmake @@ -0,0 +1,191 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/rtos_examples/freertos_sem/board.c b/boards/som_mx93/rtos_examples/freertos_sem/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_sem/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/rtos_examples/freertos_sem/board.h b/boards/som_mx93/rtos_examples/freertos_sem/board.h new file mode 100644 index 000000000..5108807ef --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_sem/board.h @@ -0,0 +1,89 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + +/* ADP5585 */ +#define BOARD_ADP5585_I2C LPI2C2 +#define BOARD_ADP5585_I2C_ADDR (0x34U) +#define BOARD_ADP5585_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_ADP5585_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_ADP5585_I2C_CLOCK_ROOT) + +#define BOARD_ADP5585_PDM_MQS_SEL (2U) +#define BOARD_ADP5585_EXP_SEL (4U) +#define BOARD_ADP5585_CAN_STBY (8U) + +/* PCAL6524 */ +#define BOARD_PCAL6524_I2C LPI2C2 +#define BOARD_PCAL6524_I2C_ADDR (0x22U) +#define BOARD_PCAL6524_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_PCAL6524_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_PCAL6524_I2C_CLOCK_ROOT) + +#define BOARD_PCAL6524_ENET1_NRST (8U + 7U) +#define BOARD_PCAL6524_ENET2_NRST (16U + 0U) +#define BOARD_PCAL6524_MIC_CAN_SEL (16U + 1U) +#define BOARD_PCAL6524_EXP_SEL (16U + 6U) +#define BOARD_PCAL6524_CAN_STBY (16U + 7U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/rtos_examples/freertos_sem/clock_config.c b/boards/som_mx93/rtos_examples/freertos_sem/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_sem/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/rtos_examples/freertos_sem/clock_config.h b/boards/som_mx93/rtos_examples/freertos_sem/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_sem/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/rtos_examples/freertos_sem/freertos_sem.c b/boards/som_mx93/rtos_examples/freertos_sem/freertos_sem.c new file mode 100644 index 000000000..ae6d7d7af --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_sem/freertos_sem.c @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "semphr.h" + +/* Freescale includes. */ +#include "fsl_device_registers.h" +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "board.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define TASK_PRIO (configMAX_PRIORITIES - 1) +#define CONSUMER_LINE_SIZE 3 +SemaphoreHandle_t xSemaphore_producer; +SemaphoreHandle_t xSemaphore_consumer; +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static void producer_task(void *pvParameters); +static void consumer_task(void *pvParameters); + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief Main function + */ +int main(void) +{ + /* Init board hardware. */ + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + if (xTaskCreate(producer_task, "PRODUCER_TASK", configMINIMAL_STACK_SIZE + 128, NULL, TASK_PRIO, NULL) != pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + while (1) + ; + } + /* Start scheduling. */ + vTaskStartScheduler(); + for (;;) + ; +} + +/*! + * @brief Task producer_task. + */ +static void producer_task(void *pvParameters) +{ + uint32_t i; + + PRINTF("Producer_task created.\r\n"); + xSemaphore_producer = xSemaphoreCreateBinary(); + if (xSemaphore_producer == NULL) + { + PRINTF("xSemaphore_producer creation failed.\r\n"); + vTaskSuspend(NULL); + } + + xSemaphore_consumer = xSemaphoreCreateBinary(); + if (xSemaphore_consumer == NULL) + { + PRINTF("xSemaphore_consumer creation failed.\r\n"); + vTaskSuspend(NULL); + } + + for (i = 0; i < CONSUMER_LINE_SIZE; i++) + { + if (xTaskCreate(consumer_task, "CONSUMER_TASK", configMINIMAL_STACK_SIZE + 128, (void *)i, TASK_PRIO, NULL) != + pdPASS) + { + PRINTF("Task creation failed!.\r\n"); + vTaskSuspend(NULL); + } + else + { + PRINTF("Consumer_task %d created.\r\n", i); + } + } + + while (1) + { + /* Producer is ready to provide item. */ + xSemaphoreGive(xSemaphore_consumer); + /* Producer is waiting when consumer will be ready to accept item. */ + if (xSemaphoreTake(xSemaphore_producer, portMAX_DELAY) == pdTRUE) + { + PRINTF("Producer released item.\r\n"); + } + else + { + PRINTF("Producer is waiting for customer.\r\n"); + } + } +} + +/*! + * @brief Task consumer_task. + */ +static void consumer_task(void *pvParameters) +{ + PRINTF("Consumer number: %d\r\n", pvParameters); + while (1) + { + /* Consumer is ready to accept. */ + xSemaphoreGive(xSemaphore_producer); + /* Consumer is waiting when producer will be ready to produce item. */ + if (xSemaphoreTake(xSemaphore_consumer, portMAX_DELAY) == pdTRUE) + { + PRINTF("Consumer %d accepted item.\r\n", pvParameters); + } + else + { + PRINTF("Consumer %d is waiting for producer.\r\n", pvParameters); + } + } +} diff --git a/boards/som_mx93/rtos_examples/freertos_sem/pin_mux.c b/boards/som_mx93/rtos_examples/freertos_sem/pin_mux.c new file mode 100644 index 000000000..4c8d6a119 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_sem/pin_mux.c @@ -0,0 +1,65 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/rtos_examples/freertos_sem/pin_mux.h b/boards/som_mx93/rtos_examples/freertos_sem/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_sem/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/rtos_examples/freertos_sem/readme.txt b/boards/som_mx93/rtos_examples/freertos_sem/readme.txt new file mode 100644 index 000000000..b7209baec --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_sem/readme.txt @@ -0,0 +1,63 @@ +Overview +======== +This document explains the freertos_sem example, what to expect when running it and a brief +introduction to the API. The freertos_sem example code shows how semaphores works. Two different +tasks are synchronized in bilateral rendezvous model. + +The example uses four tasks. One producer_task and three consumer_tasks. The producer_task starts by +creating of two semaphores (xSemaphore_producer and xSemaphore_consumer). These semaphores control +access to virtual item. The synchronization is based on bilateral rendezvous pattern. Both of +consumer and producer must be prepared to enable transaction. + + + + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Micro USB cable +- USB to UART Adapter +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Proper power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + +Prepare the Demo +================ +1. Connect the power supply to the board and switch on the board. +2. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +3. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +After the board is flashed the Tera Term will show debug console output. + +Example output: +Producer_task created. +Consumer_task 0 created. +Consumer_task 1 created. +Consumer_task 2 created. +Consumer number: 0 +Consumer 0 accepted item. +Consumer number: 1 +Consumer number: 2 +Producer released item. +Consumer 0 accepted item. +Producer released item. +Consumer 1 accepted item. +Producer released item. +Consumer 2 accepted item. diff --git a/boards/som_mx93/rtos_examples/freertos_swtimer/FreeRTOSConfig.h b/boards/som_mx93/rtos_examples/freertos_swtimer/FreeRTOSConfig.h new file mode 100644 index 000000000..6f6bcf9da --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_swtimer/FreeRTOSConfig.h @@ -0,0 +1,182 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)200) +#define configMAX_PRIORITIES 5 +#define configMINIMAL_STACK_SIZE ((unsigned short)90) +#define configMAX_TASK_NAME_LEN 20 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 /* Deprecated! */ +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 + +/* Used memory allocation (heap_x.c) */ +#define configFRTOS_MEMORY_SCHEME 4 +/* Tasks.c additions (e.g. Thread Aware Debug capability) */ +#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 1 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE ((size_t)(10 * 1024)) +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Task aware debugging. */ +#define configRECORD_STACK_HIGH_ADDRESS 1 + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +/* Define to trap errors during development. */ +#define configASSERT(x) if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);} + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + + + +#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__) + /* Clock manager provides in this variable system core clock frequency */ + #include + extern uint32_t SystemCoreClock; +#endif + + +#ifndef configENABLE_FPU + #define configENABLE_FPU 1 +#endif +#ifndef configENABLE_MPU + #define configENABLE_MPU 0 +#endif +#ifndef configENABLE_TRUSTZONE + #define configENABLE_TRUSTZONE 0 +#endif +#ifndef configRUN_FREERTOS_SECURE_ONLY + #define configRUN_FREERTOS_SECURE_ONLY 1 +#endif + +/* Redefine: Mutex is needed for SRTM communication */ +#undef configUSE_MUTEXES +#define configUSE_MUTEXES 1 + +#ifndef configTOTAL_HEAP_SIZE +#define configTOTAL_HEAP_SIZE ((size_t)(40 * 1024)) +#endif + +/* Interrupt nesting behaviour configuration. Cortex-M specific. */ +#ifdef __NVIC_PRIO_BITS +/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ +#define configPRIO_BITS __NVIC_PRIO_BITS +#else +#define configPRIO_BITS 3 /* 7 priority levels */ +#endif + +#define configSTACK_DEPTH_TYPE uint32_t + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1) + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define vPortPendSVHandler PendSV_Handler +#define vPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ diff --git a/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/CMakeLists.txt b/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/CMakeLists.txt new file mode 100644 index 000000000..c4af99172 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/CMakeLists.txt @@ -0,0 +1,121 @@ +# CROSS COMPILER SETTING +SET(CMAKE_SYSTEM_NAME Generic) +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +# THE VERSION NUMBER +SET (Tutorial_VERSION_MAJOR 1) +SET (Tutorial_VERSION_MINOR 0) + +# ENABLE ASM +ENABLE_LANGUAGE(ASM) + +SET(CMAKE_STATIC_LIBRARY_PREFIX) +SET(CMAKE_STATIC_LIBRARY_SUFFIX) + +SET(CMAKE_EXECUTABLE_LIBRARY_PREFIX) +SET(CMAKE_EXECUTABLE_LIBRARY_SUFFIX) + +# CURRENT DIRECTORY +SET(ProjDirPath ${CMAKE_CURRENT_SOURCE_DIR}) + +SET(EXECUTABLE_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) +SET(LIBRARY_OUTPUT_PATH ${ProjDirPath}/${CMAKE_BUILD_TYPE}) + + +project(freertos_swtimer) + +set(MCUX_BUILD_TYPES debug release) + +set(MCUX_SDK_PROJECT_NAME freertos_swtimer.elf) + +if (NOT DEFINED SdkRootDirPath) + SET(SdkRootDirPath ${ProjDirPath}/../../../../..) +endif() + +include(${ProjDirPath}/flags.cmake) + +include(${ProjDirPath}/config.cmake) + +add_executable(${MCUX_SDK_PROJECT_NAME} +"${ProjDirPath}/../freertos_swtimer.c" +"${ProjDirPath}/../pin_mux.c" +"${ProjDirPath}/../pin_mux.h" +"${ProjDirPath}/../FreeRTOSConfig.h" +"${ProjDirPath}/../board.c" +"${ProjDirPath}/../board.h" +"${ProjDirPath}/../clock_config.c" +"${ProjDirPath}/../clock_config.h" +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${ProjDirPath}/.. +) + +set(CMAKE_MODULE_PATH + ${SdkRootDirPath}/rtos/freertos/freertos-kernel + ${SdkRootDirPath}/devices/MIMX9352/drivers + ${SdkRootDirPath}/devices/MIMX9352 + ${SdkRootDirPath}/devices/MIMX9352/utilities + ${SdkRootDirPath}/components/uart + ${SdkRootDirPath}/components/serial_manager + ${SdkRootDirPath}/components/lists + ${SdkRootDirPath}/CMSIS/Core/Include +) + +# include modules +include(middleware_freertos-kernel_cm33_nonsecure_port_MIMX9352) + +include(driver_clock_MIMX9352) + +include(middleware_freertos-kernel_heap_4_MIMX9352) + +include(driver_common_MIMX9352) + +include(device_MIMX9352_CMSIS_MIMX9352) + +include(utility_debug_console_MIMX9352) + +include(utility_assert_MIMX9352) + +include(component_lpuart_adapter_MIMX9352) + +include(component_serial_manager_MIMX9352) + +include(component_lists_MIMX9352) + +include(component_serial_manager_uart_MIMX9352) + +include(driver_lpuart_MIMX9352) + +include(device_MIMX9352_startup_MIMX9352) + +include(driver_iomuxc_MIMX9352) + +include(driver_rgpio_MIMX9352) + +include(driver_cache_xcache_MIMX9352) + +include(driver_sentinel_MIMX9352) + +include(middleware_freertos-kernel_MIMX9352) + +include(middleware_freertos-kernel_extension_MIMX9352) + +include(CMSIS_Include_core_cm_MIMX9352) + +include(utilities_misc_utilities_MIMX9352) + + +IF(NOT DEFINED TARGET_LINK_SYSTEM_LIBRARIES) + SET(TARGET_LINK_SYSTEM_LIBRARIES "-lm -lc -lgcc -lnosys") +ENDIF() + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--start-group) + +target_link_libraries(${MCUX_SDK_PROJECT_NAME} PRIVATE ${TARGET_LINK_SYSTEM_LIBRARIES}) + +TARGET_LINK_LIBRARIES(${MCUX_SDK_PROJECT_NAME} PRIVATE -Wl,--end-group) + +ADD_CUSTOM_COMMAND(TARGET ${MCUX_SDK_PROJECT_NAME} POST_BUILD COMMAND ${CMAKE_OBJCOPY} +-Obinary ${EXECUTABLE_OUTPUT_PATH}/${MCUX_SDK_PROJECT_NAME} ${EXECUTABLE_OUTPUT_PATH}/sdk20-app.bin) + diff --git a/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/MIMX9352_cm33_ram.ld b/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/MIMX9352_cm33_ram.ld new file mode 100644 index 000000000..e8ae6dfe8 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/MIMX9352_cm33_ram.ld @@ -0,0 +1,246 @@ +/* +** ################################################################### +** Processors: MIMX9352AVTXM_cm33 +** MIMX9352CVUXK_cm33 +** MIMX9352DVUXM_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMX93RM, Internal, November. 2021 +** Version: rev. 1.0, 2021-11-16 +** Build: b230201 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0478 : 0x0; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x0FFE0000, LENGTH = 0x00000478 + m_text (RX) : ORIGIN = 0x0FFE0478, LENGTH = 0x0001FB88 + m_m33_suspend_ram (RW) : ORIGIN = 0x20000000, LENGTH = 0x00002000 + m_a55_suspend_ram (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 + m_data (RW) : ORIGIN = 0x20003000, LENGTH = 0x0001C000 + m_rsc_tbl (RW) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) /* Resource table */ + . = ALIGN(8); + } > m_text + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + __quickcodeaccess_start__ = .; + . = ALIGN(32); + *(CodeQuickAccess) + . = ALIGN(32); + __quickcodeaccess_end__ = .; + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + __quickdataaccess_start__ = .; + . = ALIGN(32); + *(DataQuickAccess) + . = ALIGN(32); + __quickdataaccess_end__ = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .m33_suspend : + { + *(M33SuspendRam) + . = ALIGN(4); + } > m_m33_suspend_ram + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* For Resource table region */ + __RscTblStart = ORIGIN(m_rsc_tbl); + __RscTblEnd = ORIGIN(m_rsc_tbl) + LENGTH(m_rsc_tbl); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/build_all.bat b/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/build_all.bat new file mode 100644 index 000000000..a16d8ae13 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/build_all.bat @@ -0,0 +1,15 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j + +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j + +IF "%1" == "" ( pause ) diff --git a/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/build_all.sh b/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/build_all.sh new file mode 100755 index 000000000..253693061 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/build_all.sh @@ -0,0 +1,15 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j + +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j + diff --git a/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/build_debug.bat b/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/build_debug.bat new file mode 100644 index 000000000..15123387e --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/build_debug.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=debug . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/build_debug.sh b/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/build_debug.sh new file mode 100755 index 000000000..42803761b --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/build_debug.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=debug . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/build_release.bat b/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/build_release.bat new file mode 100644 index 000000000..a88e3d668 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/build_release.bat @@ -0,0 +1,6 @@ +if exist CMakeFiles (RD /s /Q CMakeFiles) +if exist Makefile (DEL /s /Q /F Makefile) +if exist cmake_install.cmake (DEL /s /Q /F cmake_install.cmake) +if exist CMakeCache.txt (DEL /s /Q /F CMakeCache.txt) +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=release . +mingw32-make -j 2> build_log.txt diff --git a/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/build_release.sh b/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/build_release.sh new file mode 100755 index 000000000..47cfb057c --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/build_release.sh @@ -0,0 +1,7 @@ +#!/bin/sh +if [ -d "CMakeFiles" ];then rm -rf CMakeFiles; fi +if [ -f "Makefile" ];then rm -f Makefile; fi +if [ -f "cmake_install.cmake" ];then rm -f cmake_install.cmake; fi +if [ -f "CMakeCache.txt" ];then rm -f CMakeCache.txt; fi +cmake -DCMAKE_TOOLCHAIN_FILE="../../../../../tools/cmake_toolchain_files/armgcc.cmake" -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=release . +make -j 2>&1 | tee build_log.txt diff --git a/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/clean.bat b/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/clean.bat new file mode 100644 index 000000000..f391a79b5 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/clean.bat @@ -0,0 +1,3 @@ +RD /s /Q debug release CMakeFiles +DEL /s /Q /F Makefile cmake_install.cmake CMakeCache.txt +pause diff --git a/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/clean.sh b/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/clean.sh new file mode 100755 index 000000000..795ad8716 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/clean.sh @@ -0,0 +1,3 @@ +#!/bin/sh +rm -rf debug release CMakeFiles +rm -rf Makefile cmake_install.cmake CMakeCache.txt diff --git a/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/config.cmake b/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/config.cmake new file mode 100755 index 000000000..b228f064e --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/config.cmake @@ -0,0 +1,3 @@ +# config to select component, the format is CONFIG_USE_${component} +set(CONFIG_USE_component_serial_manager_uart_MIMX9352 true) +set(CONFIG_USE_driver_lpuart_MIMX9352 true) diff --git a/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/flags.cmake b/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/flags.cmake new file mode 100755 index 000000000..d76ba2bff --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_swtimer/armgcc/flags.cmake @@ -0,0 +1,191 @@ +IF(NOT DEFINED FPU) + SET(FPU "-mfloat-abi=hard -mfpu=fpv5-sp-d16") +ENDIF() + +IF(NOT DEFINED SPECS) + SET(SPECS "--specs=nano.specs --specs=nosys.specs") +ENDIF() + +IF(NOT DEFINED DEBUG_CONSOLE_CONFIG) + SET(DEBUG_CONSOLE_CONFIG "-DSDK_DEBUGCONSOLE=1") +ENDIF() + +SET(CMAKE_ASM_FLAGS_DEBUG " \ + ${CMAKE_ASM_FLAGS_DEBUG} \ + -DDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_ASM_FLAGS_RELEASE " \ + ${CMAKE_ASM_FLAGS_RELEASE} \ + -DNDEBUG \ + -D__STARTUP_CLEAR_BSS \ + -D__STARTUP_INITIALIZE_NONCACHEDATA \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ +") +SET(CMAKE_C_FLAGS_DEBUG " \ + ${CMAKE_C_FLAGS_DEBUG} \ + -DDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_C_FLAGS_RELEASE " \ + ${CMAKE_C_FLAGS_RELEASE} \ + -DNDEBUG \ + -DCPU_MIMX9352DVUXM_cm33 \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DSDK_OS_FREE_RTOS \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -std=gnu99 \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_DEBUG " \ + ${CMAKE_CXX_FLAGS_DEBUG} \ + -DDEBUG \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -g \ + -O0 \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_CXX_FLAGS_RELEASE " \ + ${CMAKE_CXX_FLAGS_RELEASE} \ + -DNDEBUG \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DMCUXPRESSO_SDK \ + -Os \ + -mcpu=cortex-m33 \ + -Wall \ + -mthumb \ + -MMD \ + -MP \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mapcs \ + -fno-rtti \ + -fno-exceptions \ + ${FPU} \ + ${DEBUG_CONSOLE_CONFIG} \ +") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG " \ + ${CMAKE_EXE_LINKER_FLAGS_DEBUG} \ + -g \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE " \ + ${CMAKE_EXE_LINKER_FLAGS_RELEASE} \ + -mcpu=cortex-m33 \ + -Wall \ + -fno-common \ + -ffunction-sections \ + -fdata-sections \ + -ffreestanding \ + -fno-builtin \ + -mthumb \ + -mapcs \ + -Xlinker \ + --gc-sections \ + -Xlinker \ + -static \ + -Xlinker \ + -z \ + -Xlinker \ + muldefs \ + -Xlinker \ + -Map=output.map \ + -Wl,--print-memory-usage \ + ${FPU} \ + ${SPECS} \ + -T${ProjDirPath}/MIMX9352_cm33_ram.ld -static \ +") diff --git a/boards/som_mx93/rtos_examples/freertos_swtimer/board.c b/boards/som_mx93/rtos_examples/freertos_swtimer/board.c new file mode 100644 index 000000000..2a3b145e0 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_swtimer/board.c @@ -0,0 +1,152 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board.h" +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* clang-format off */ + const clock_root_config_t uartClkCfg = { + .clockOff = false, + .mux = 0, // 24MHz oscillator source + .div = 1 + }; + /* clang-format on */ + + CLOCK_SetRootClock(BOARD_DEBUG_UART_CLOCK_ROOT, &uartClkCfg); + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); +} + + +void BOARD_McoreSUSPEND(void) +{ + uint32_t value = 0U; + /* Config OSCPLL LPM setting for M33 SUSPEND */ + for (unsigned int i = OSCPLL_LPM_START; i <= OSCPLL_LPM_END; i++) + { + CCM_CTRL->OSCPLL[i].LPM0 |= CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK; + } + + /* Config GPC_CTRL_CM33 to set Mcore as SUSPEND mode */ + GPC_CTRL_CM33->CM_MODE_CTRL |= GPC_CM_MODE_CTRL_CPU_MODE_TARGET_MASK; + + /* Stop SysTick and enter WFI + * System will goes into system sleep flow + * The STBY LED on board will light with red color + */ + /* Save old value of SYST_CSR */ + value = SYSTICK_CTRL_REG; + SYSTICK_CTRL_REG = SYSTICK_CLOSE; + __WFI(); + /* Enable systick */ + SYSTICK_CTRL_REG = value; +} + +void BOARD_ConfigMPU(void) +{ + uint8_t attr; + + /* Disable code cache(ICache) and system cache(DCache) */ + XCACHE_DisableCache(LPCAC_PC); + XCACHE_DisableCache(LPCAC_PS); + + /* NOTE: All TCRAM is non-cacheable regardless of MPU setting. */ + + /* + * default cache policy(default memory access behavior) after enable mpu on cortex-m33(according to RM of + * cortex-m33): 0x00000000-0x1FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0x20000000-0x3FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x40000000-0x5FFFFFFF Device, Shareable + * 0x60000000-0x7FFFFFFF Normal memory, Non-shareable, Write-Back, Write Allocate + * 0x80000000-0x9FFFFFFF Normal memory, Non-shareable, Write-Through, not Write Allocate + * 0xA0000000-0xDFFFFFFF Device, Shareable + * 0xE0000000-0xE003FFFF Device, Shareable + * 0xE0040000-0xE0043FFF Device, Shareable + * 0xE0044000-0xE00EFFFF Device, Shareable + * 0xF0000000-0xFFFFFFFF Device, Shareable + */ + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: Device-nGnRnE */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: Normal memory, Outer non-cacheable, Inner non-cacheable */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate + */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* + * Change macro definitions as follows when choose cache policy as non-cacheable: + * #define DDR_NONCACHEABLE (1U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Through: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (1U) + * #define DDR_WRITE_BACK (0U) + * + * + * Change macro definitions as follows when choose cache policy as Write-Back: + * #define DDR_NONCACHEABLE (0U) + * #define DDR_WRITE_THROUGH (0U) + * #define DDR_WRITE_BACK (1U) + */ +#define DDR_NONCACHEABLE (1U) +#define DDR_WRITE_THROUGH (0U) +#define DDR_WRITE_BACK (0U) +#if DDR_NONCACHEABLE + /* NOTE: DDR is used as shared memory for A/M core communication, set it to non-cacheable. */ + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 1 + * (non-cacheable). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 1U)); +#elif DDR_WRITE_THROUGH + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 2 + * (Normal memory, Inner write-through transient, read allocate. Inner write-through transient, read allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 2U)); +#elif DDR_WRITE_BACK + /* Region 0: [0x80000000, 0xDFFFFFFF](DRAM), outer shareable, read/write, any privileged, executable. Attr 3 + * (Normal memory, Outer write-back transient, read/write allocate. Inner write-back transient, read/write + * allocate). */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_OUTER, 0U, 1U, 0U), ARM_MPU_RLAR(0xDFFFFFFF, 3U)); +#endif + + /* Enable MPU(use default memory map when access the memory within region) */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable ICache and DCache */ + XCACHE_EnableCache(LPCAC_PC); + XCACHE_EnableCache(LPCAC_PS); + /* flush pipeline */ + __DSB(); + __ISB(); +} diff --git a/boards/som_mx93/rtos_examples/freertos_swtimer/board.h b/boards/som_mx93/rtos_examples/freertos_swtimer/board.h new file mode 100644 index 000000000..5108807ef --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_swtimer/board.h @@ -0,0 +1,89 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_INSTANCE 7U +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_CLOCK_ROOT kCLOCK_Root_Lpuart7 +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(BOARD_DEBUG_UART_CLOCK_ROOT) + +#define VDEV0_VRING_BASE (0x87ee0000U) +#define VDEV1_VRING_BASE (0x87ef0000U) + +#define LED_INIT() +#define LED_TOGGLE() + +#define BOARD_CODEC_I2C_BASEADDR LPI2C1 +#define BOARD_CODEC_I2C_INSTANCE 1U + +/* ADP5585 */ +#define BOARD_ADP5585_I2C LPI2C2 +#define BOARD_ADP5585_I2C_ADDR (0x34U) +#define BOARD_ADP5585_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_ADP5585_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_ADP5585_I2C_CLOCK_ROOT) + +#define BOARD_ADP5585_PDM_MQS_SEL (2U) +#define BOARD_ADP5585_EXP_SEL (4U) +#define BOARD_ADP5585_CAN_STBY (8U) + +/* PCAL6524 */ +#define BOARD_PCAL6524_I2C LPI2C2 +#define BOARD_PCAL6524_I2C_ADDR (0x22U) +#define BOARD_PCAL6524_I2C_CLOCK_ROOT kCLOCK_Root_Lpi2c2 +#define BOARD_PCAL6524_I2C_CLOCK_FREQ CLOCK_GetIpFreq(BOARD_PCAL6524_I2C_CLOCK_ROOT) + +#define BOARD_PCAL6524_ENET1_NRST (8U + 7U) +#define BOARD_PCAL6524_ENET2_NRST (16U + 0U) +#define BOARD_PCAL6524_MIC_CAN_SEL (16U + 1U) +#define BOARD_PCAL6524_EXP_SEL (16U + 6U) +#define BOARD_PCAL6524_CAN_STBY (16U + 7U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); + +/* Mcore suspend setting */ +#define OSCPLL_LPM_START 3U +#define OSCPLL_LPM_END 12U +/* SysTick Control and Status Register(SYST_CSR) of cortex-M33 */ +#define SYSTICK_CTRL_REG (*((volatile uint32_t *)0xe000e010)) +/* + * SYST_CSR[0] ENABLE(Enable counter): + * 0: Counter Disabled + * 1: Counter Enabled + * SYST_CSR[1] TICKINT(Enables SysTick exception request): + * 0: Counting down to zero does not assert the SysTick exception request. + * 1: Counting down to zero asserts the SysTick exception request. + * More info from + * https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-timer--systick/systick-control-and-status-register + */ +#define SYSTICK_CLOSE 0U +void BOARD_McoreSUSPEND(void); + +void BOARD_ConfigMPU(void); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _BOARD_H_ */ diff --git a/boards/som_mx93/rtos_examples/freertos_swtimer/clock_config.c b/boards/som_mx93/rtos_examples/freertos_swtimer/clock_config.c new file mode 100644 index 000000000..961eea2f6 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_swtimer/clock_config.c @@ -0,0 +1,97 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "clock_config.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* clang-format off */ +/* + * SYSTEM_PLL1 + * + * VCO = (24MHz / rdiv) * (mfi + mfn / mfd) = 4000MHz + * Output = VCO / odiv = 1000MHz + */ +const fracn_pll_init_t g_sysPllCfg = { + .rdiv = 1, + .mfi = 166, + .mfn = 2, + .mfd = 3, + .odiv = 4 +}; + +/* SYSTEM_PLL1_PFD0 Output = VCO / (mfi + mfn / 5) = 1000MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd0Cfg = { + .mfi = 4, + .mfn = 0, + .div2_en = true +}; + +/*SYSTEM_PLL1_PFD1 Output = VCO / (mfi + mfn / 5) = 800MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd1Cfg = { + .mfi = 5, + .mfn = 0, + .div2_en = true +}; + +/* SYSTEM_PLL1_PFD2 Output = VCO / (mfi + mfn / 5) = 625MHz */ +const fracn_pll_pfd_init_t g_sysPllPfd2Cfg = { + .mfi = 6, + .mfn = 2, + .div2_en = true +}; + + +/* + * AUDIOPLL1/AUDIOPLL1OUT + * + * VCO = (24MHz / rdiv) * (mfi + (mfn / mfd)) = 3,932,160,000 Hz + * Output = VCO / odiv = 393.216 MHz + */ +const fracn_pll_init_t g_audioPllCfg = { + .rdiv = 1, + .mfi = 163, + .mfn = 84, + .mfd = 100, + .odiv = 10 +}; + + +/* clang-format on */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void BOARD_InitClock(void) +{ + g_clockSourceFreq[kCLOCK_Osc24M] = 24000000U; + g_clockSourceFreq[kCLOCK_SysPll1] = 4000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0] = 1000000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd0Div2] = 500000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1] = 800000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd1Div2] = 400000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2] = 625000000U; + g_clockSourceFreq[kCLOCK_SysPll1Pfd2Div2] = 312500000U; + g_clockSourceFreq[kCLOCK_AudioPll1Out] = 393216000U; + g_clockSourceFreq[kCLOCK_AudioPll1] = 393216000U; +} + +void BOARD_BootClockRUN(void) +{ + BOARD_InitClock(); + + /* ROM has already initialized PLL */ + CLOCK_PllInit(AUDIOPLL, &g_audioPllCfg); +#if 0 + CLOCK_PllInit(SYSPLL, &g_sysPllCfg); + CLOCK_PllPfdInit(SYSPLL, 0, &g_sysPllPfd0Cfg); + CLOCK_PllPfdInit(SYSPLL, 1, &g_sysPllPfd1Cfg); + CLOCK_PllPfdInit(SYSPLL, 2, &g_sysPllPfd2Cfg); +#endif +} diff --git a/boards/som_mx93/rtos_examples/freertos_swtimer/clock_config.h b/boards/som_mx93/rtos_examples/freertos_swtimer/clock_config.h new file mode 100644 index 000000000..9793da5a9 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_swtimer/clock_config.h @@ -0,0 +1,29 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_clock.h" + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/boards/som_mx93/rtos_examples/freertos_swtimer/freertos_swtimer.c b/boards/som_mx93/rtos_examples/freertos_swtimer/freertos_swtimer.c new file mode 100644 index 000000000..a11332147 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_swtimer/freertos_swtimer.c @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* Standard includes. */ +#include +#include +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" + +/* Freescale includes. */ +#include "fsl_device_registers.h" +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "board.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The software timer period. */ +#define SW_TIMER_PERIOD_MS (1000 / portTICK_PERIOD_MS) +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/* The callback function. */ +static void SwTimerCallback(TimerHandle_t xTimer); + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief Main function + */ +int main(void) +{ + TimerHandle_t SwTimerHandle = NULL; + + /* Init board hardware. */ + BOARD_InitBootPins(); + BOARD_BootClockRUN(); + BOARD_InitDebugConsole(); + SystemCoreClockUpdate(); + /* Create the software timer. */ + SwTimerHandle = xTimerCreate("SwTimer", /* Text name. */ + SW_TIMER_PERIOD_MS, /* Timer period. */ + pdTRUE, /* Enable auto reload. */ + 0, /* ID is not used. */ + SwTimerCallback); /* The callback function. */ + /* Start timer. */ + xTimerStart(SwTimerHandle, 0); + /* Start scheduling. */ + vTaskStartScheduler(); + for (;;) + ; +} + +/*! + * @brief Software timer callback. + */ +static void SwTimerCallback(TimerHandle_t xTimer) +{ + PRINTF("Tick.\r\n"); +} diff --git a/boards/som_mx93/rtos_examples/freertos_swtimer/pin_mux.c b/boards/som_mx93/rtos_examples/freertos_swtimer/pin_mux.c new file mode 100644 index 000000000..4c8d6a119 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_swtimer/pin_mux.c @@ -0,0 +1,65 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v12.0 +processor: MIMX9352xxxxM +package_id: MIMX9352DVUXM +mcu_data: ksdk2_0 +processor_version: 0.12.3 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33} +- pin_list: + - {pin_num: M21, peripheral: LPUART7, signal: lpuart_rx, pin_signal: GPIO_IO09, FSEL1: SlOW_SLEW_RATE, DSE: NO_DRIVE} + - {pin_num: M20, peripheral: LPUART7, signal: lpuart_tx, pin_signal: GPIO_IO08, PD: DISABLED, FSEL1: SlOW_SLEW_RATE} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { /*!< Function assigned for the core: undefined[cm33] */ + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, 0U); + + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO09__LPUART7_RX, + IOMUXC_PAD_PD_MASK); + IOMUXC_SetPinConfig(IOMUXC_PAD_GPIO_IO08__LPUART7_TX, + IOMUXC_PAD_DSE(15U)); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/rtos_examples/freertos_swtimer/pin_mux.h b/boards/som_mx93/rtos_examples/freertos_swtimer/pin_mux.h new file mode 100644 index 000000000..8dc55eff5 --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_swtimer/pin_mux.h @@ -0,0 +1,54 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +#include "fsl_iomuxc.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /*!< Function assigned for the core: undefined[cm33] */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/boards/som_mx93/rtos_examples/freertos_swtimer/readme.txt b/boards/som_mx93/rtos_examples/freertos_swtimer/readme.txt new file mode 100644 index 000000000..91c3fc2ba --- /dev/null +++ b/boards/som_mx93/rtos_examples/freertos_swtimer/readme.txt @@ -0,0 +1,49 @@ +Overview +======== +This document explains the freertos_swtimer example. It shows usage of software timer and its +callback. + +The example application creates one software timer SwTimer. The timer’s callback SwTimerCallback is +periodically executed and text “Tick.” is printed to terminal. + + + + +Toolchain supported +=================== +- IAR embedded Workbench 9.30.1 +- GCC ARM Embedded 10.3.1 + +Hardware requirements +===================== +- Micro USB cable +- USB to UART Adapter +- VAR-SOM-MX93 SoM(s) and Symphony Board(s) +- Proper power supply +- Personal Computer + +Board settings +============== +No special settings are required. + + +Prepare the Demo +================ +1. Connect the power supply to the board and switch on the board. +2. Connect the micro USB to J29 (Cortex-A55s) and the USB to UART adapter to J18.5/J18.3 (RX/TX) (Cortex-M33). +3. Open a serial terminal on the Cortex-M33 serial port with the following settings: + - 115200 baud rate + - 8 data bits + - No parity + - One stop bit + - No flow control +4. Load and start the demo on the M33 using either U-Boot (bootaux) or Linux (remoteproc) per the variwiki guide. + +Running the demo +================ +After the board is flashed the Tera Term will show output message. + +Example output: +Tick. +Tick. +Tick.