some vxdef code for testing

ir/types.vxdef

@@ -0,0 +1,54 @@
+scope vx
+
+class SizedRegister(
+    usize  bitsWidth,
+    string asm,
+    [Flag] requiredFlags
+)
+
+virt class Slot(
+    # if it is [0], then no data can be stored in it and it's a special slot, like the flags register
+    [usize] sizeAliases
+)
+
+virt class Register(
+    string name,
+    [SizedRegister] variants
+) : Slot(variants.*.bitsWidth)
+
+virt class Flag(
+    string name,
+    [Flag] infer
+)
+
+virt class Target(
+    [Flag] flags
+)
+
+virt class Value()
+
+class ImmIntValue(
+    u64 imm
+) : Value()
+
+class ImmFltValue(
+    f64 imm
+) : Value()
+
+class VarValue(
+    vx_IrVar var
+) : Value()
+
+class LabelValue(
+    usize label
+) : Value()
+
+class BlockValue(
+    vx_IrBlock* block
+) : Value()
+
+class BlockRefValue(
+    vx_IrBlock* block
+) : Value()
+
+include "ops.vxdef"

targets/x86/flags.vxdef

@@ -0,0 +1,125 @@
+included_only
+
+enum class X86Flag(
+    string name,
+    [Flag] infer
+) : Flag(name, infer)
+{
+    CMOV ("cmov",  []),
+    FPU  ("fpu",   []),
+    MMX  ("mmx",   [FPU]),
+    ADX  ("adx",   []),
+    AES  ("aes",   []),
+    AMD64("amd64", [FPU]),
+    AMX_TILE   ("amx_tile",    [AMD64]),
+    AMX_BF16   ("amx_bf16",    [AMX_TILE]),
+    AMX_FP16   ("amx_fp16",    [AMX_TILE]),
+    AMX_INT8   ("amx_int8",    [AMX_TILE]),
+    AMX_COMPLEX("amx_complex", [AMX_TILE, AMX_FP16]),
+    AVX ("avx",  [AMD64]),
+    AVX2("avx2", [AMD64]),
+
+    # Don't use SystemV64 redzone
+    _NO_REDZONE("no-redzone", []),
+}
+
+# TODO: the following + APX
+
+# AVX10_1_512,
+# AVX10_1_256,
+# AVX5124FMAPS,
+# AVX5124VNNIW,
+# AVX512BF16,
+# AVX512BITALG,
+# AVX512BW,
+# AVX512CD,
+# AVX512DQ,
+# AVX512ER,
+# AVX512F,
+# AVX512FP16,
+# AVX512IFMA,
+# AVX512PF,
+# AVX512VBMI,
+# AVX512VBMI2,
+# AVX512VL,
+# AVX512VNNI,
+# AVX512VP2INTERSECT,
+# AVX512VPOPCNTDQ,
+# AVXIFMA,
+# AVXNECONVERT,
+# AVXVNNI,
+# AVXVNNIINT16,
+# AVXVNNIINT8,
+# BMI,
+# BMI2,
+# CLDEMOTE,
+# CLFLUSHOPT,
+# CLWB,
+# CLZERO,
+# CMPCCXADD,
+# CMPXCHG16B,
+# CMPXCHG8B,
+# CRC32,
+# ENQCMD,
+# EVEX512,
+# F16C,
+# FMA,
+# FMA4,
+# FSGSBASE,
+# FXSR,
+# GFNI,
+# HRESET,
+# INVPCID,
+# KL,
+# LWP,
+# LZCNT,
+# MMX,
+# MOVBE,
+# MOVDIR64B,
+# MOVDIRI,
+# MWAITX,
+# PCLMUL,
+# PCONFIG,
+# PKU,
+# POPCNT,
+# PREFETCHI,
+# PREFETCHWT1,
+# PRFCHW,
+# PTWRITE,
+# RAOINT,
+# RDPID,
+# RDPRU,
+# RDRND,
+# RDSEED,
+# RTM,
+# SAHF,
+# SERIALIZE,
+# SGX,
+# SHA,
+# SHA512,
+# SHSTK,
+# SM3,
+# SM4,
+# SSE,
+# SSE2,
+# SSE3,
+# SSE4_1,
+# SSE4_2,
+# SSE4_A,
+# SSSE3,
+# TBM,
+# TSXLDTRK,
+# UINTR,
+# USERMSR,
+# VAES,
+# VPCLMULQDQ,
+# VZEROUPPER,
+# WAITPKG,
+# WBNOINVD,
+# WIDEKL,
+# X87,
+# XOP,
+# XSAVE,
+# XSAVEC,
+# XSAVEOPT,
+# XSAVES,

targets/x86/lower/cmp.vxdef

@@ -0,0 +1,24 @@
+included_only
+
+pattern LowerCmp requires(
+    opkind   op      [IsCompareOp()],
+    variable cond    [],
+    value    a       [],
+    value    b       [],
+) constraints[
+    oneOf(
+        Is_R_I(a,b),
+        Is_R_R(a,b),
+        Is_R_R(a,b),
+    )
+] creates(
+    variable flag from var_alloc(size=0, params=[inSlot(X86Register::FLAGS)]),
+    variable temp from var_alloc(size=8, params=[IsIntReg()])
+    value    cc   from CCLut(opkind),
+) {
+    cond = op(a=a, b=b)[];
+} replace {
+    flag = X86Ops::CMP(a=a, b=b);
+    temp = X86Ops::SETCC(cond=flag, x86_cc=cc)[];
+    cond = imm(val=temp);
+}

targets/x86/lower/cmp_cond_jump.vxdef

@@ -0,0 +1,31 @@
+included_only
+
+pattern LowerCmpCondJump requires(
+    opkind   op      [IsCompareOp()],
+    variable cond    [],
+    value    a       [],
+    value    b       [],
+    value    label   [],
+    opseq    between [doesNotMutate(cond), doesNotMutate(a), doesNotMutate(b)]
+) constraints[
+    oneOf(
+        Is_R_I(a,b),
+        Is_R_R(a,b),
+        Is_R_R(a,b),
+    )
+] creates(
+    variable flag from var_alloc(size=0, params=[inSlot(X86Register::FLAGS)]),
+    value    cc   from CCLut(opkind),
+) {
+    cond = op(a=a, b=b)[];
+    *between;
+    Ops::COND(id=label, cond=cond)[];
+} replace {
+    # keep op here because other ops might ref the result too
+    cond = op(a=a, b=b)[];
+    *between;
+    flag = X86Ops::CMP(a=a, b=b);
+    X86Ops::COND(id=label, cond=flag, x86_cc=cc);
+}
+
+

targets/x86/lower/lea.vxdef

@@ -0,0 +1,58 @@
+included_only
+
+pattern GenLea1Add requires(
+    variable out     [IsIntReg()],
+    value    a       [IsIntReg()],
+    value    b       [is(ImmIntValue)],
+) creates(
+    value ea from X86EA1Value(
+        a.slot().as(X86Register),
+        b.value
+    )
+) {
+    out = Ops::ADD(a=a, b=b)[];
+} replace {
+    out = X86Ops::LEA(val=ea);
+}
+
+pattern GenLea1Sub requires(
+    variable out     [IsIntReg()],
+    value    a       [is(ImmIntValue)],
+    value    b       [IsImm()],
+) creates(
+    value ea from X86EA1Value(
+        a.slot().as(X86Register),
+        b.value.neg()
+    )
+) {
+    out = Ops::SUB(a=a, b=b)[];
+} replace {
+    out = X86Ops::LEA(val=ea);
+}
+
+# TODO: other combinations of lea
+
+pattern GenLea2Simple requires(
+    variable out     [IsIntReg()],
+    variable temp    [],
+    value    a       [is(ImmIntValue)],
+    value    b       [IsIntReg()],
+    value    c       [IsIntReg()]
+    opseq    between [doesNotMutate(temp), doesNotMutate(c), doesNotMutate(b)]
+) creates(
+    value ea from X86EA2Value(
+        c.slot().as(X86Register),
+        b.slot().as(X86Register),
+        1,
+        a.value
+    )
+) {
+    temp = Ops::ADD(a=c, b=b)[];
+    *between;
+    out = Ops::ADD(a=a, b=temp)[];
+} replace {
+    # keep temp even tough we don't need it anymore
+    temp = Ops::ADD(a=c, b=b)[];
+    *between;
+    out = X86Ops::LEA(val=ea);
+}

targets/x86/ops.vxdef

@@ -0,0 +1,79 @@
+included_only
+
+extension class X86Op(
+
+) : Op
+
+extension enum X86Ops : Ops
+{
+    CMP(args="a, b",
+        debug="_cmp",
+        descr="x86 compare op",
+        inlineCost=1,
+        execCost=1,
+        endsFlow=false,
+        hasEffect=true,
+        volatile=false,
+        sideEffect=false,
+    ),
+
+    TEST(
+        args="a, b",
+        debug="_test",
+        descr="x86 test op",
+        inlineCost=1,
+        execCost=1,
+        endsFlow=false,
+        hasEffect=true,
+        volatile=false,
+        sideEffect=false,
+    ),
+
+    COND(
+        args="id, cond: flags, cc: x86_cc",
+        debug="_cond",
+        descr="x86 conditional jump,
+        inlineCost=1,
+        execCost=2,
+        endsFlow=false,
+        hasEffect=true,
+        volatile=false,
+        sideEffect=true,
+    ),
+
+    SETCC(
+        args="cond: flags, cc: x86_cc",
+        debug="_setcc",
+        descr="x86 setcc op",
+        inlineCost=1,
+        execCost=1,
+        endsFlow=false,
+        hasEffect=true,
+        volatile=false,
+        sideEffect=false,
+    ),
+
+    SETCC_MEM(
+        args="cond: flags, cc: x86_cc, addr: addr",
+        debug="_setccm",
+        descr="x86 setcc into mem op",
+        inlineCost=1,
+        execCost=1,
+        endsFlow=false,
+        hasEffect=true,
+        volatile=false,
+        sideEffect=true,
+    ),
+
+    LEA(
+        args="val: x86_ea",
+        debug="_lea",
+        descr="x86 load effective address",
+        inlineCost=2,
+        execCost=1,
+        endsFlow=false,
+        hasEffect=true,
+        volatile=false,
+        sideEffect=false
+    )
+}