diff --git a/kernel/cost.h b/kernel/cost.h
index 585c589514e..15d74d7b30e 100644
--- a/kernel/cost.h
+++ b/kernel/cost.h
@@ -85,8 +85,9 @@ struct CellCosts
 	}
 
 	// Get the cell cost for a cell based on its parameters.
-	// This cost is an upper bound for the number of gates the cell will
-	// get mapped to with "opt -fast; techmap"
+	// This cost is an *approximate* upper bound for the number of gates that
+	// the cell will get mapped to with "opt -fast; techmap"
+	// The intended usage is for flattening heuristics and similar situations
 	unsigned int get(RTLIL::Cell *cell);
 	// Sum up the cell costs of all cells in the module
 	// and all its submodules recursively
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index 88ebdca3218..fc2aac2f83d 100644
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -769,8 +769,8 @@ struct TestCellPass : public Pass {
 		log("    -bloat {factor}\n");
 		log("        increase cell size limits b{factor} times where possible\n");
 		log("    -check_cost\n");
-		log("        check the estimated cell cost is a valid upper bound for the techmapped\n");
-		log("        cell count \n");
+		log("        check if the estimated cell cost is a valid upper bound for\n");
+		log("        the techmapped cell count \n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design*) override
@@ -1063,8 +1063,10 @@ struct TestCellPass : public Pass {
 				delete design;
 			}
 			if (check_cost && failed) {
-				log_warning("Cell type %s failed in %.1f%% cases with worst offender being by %d (%.1f%%)\n", cell_type.c_str(),
-					    100 * (float)failed / (float)num_iter, worst_abs, 100 * worst_rel);
+				log_warning("Cell type %s cost underestimated in %.1f%% cases "
+					    "with worst offender being by %d (%.1f%%)\n",
+					    cell_type.c_str(), 100 * (float)failed / (float)num_iter,
+						worst_abs, 100 * worst_rel);
 			}
 		}
 		if (vlog_file.is_open()) {