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imx283.c
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// SPDX-License-Identifier: GPL-2.0
/*
* V4L2 Support for the IMX283
*
* The IMX283 has BigEndian register addresses
* and uses little-endian value.
*
*/
#include <asm/unaligned.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-event.h>
#include <media/v4l2-fwnode.h>
#include <media/v4l2-mediabus.h>
struct cci_reg_sequence {
u32 reg;
u64 val;
};
#define CCI_REG_ADDR_MASK GENMASK(15, 0)
#define CCI_REG_WIDTH_SHIFT 16
#define CCI_REG_WIDTH_MASK GENMASK(19, 16)
#define CCI_REG_LE BIT(20)
#define CCI_REG8(x) ((1 << CCI_REG_WIDTH_SHIFT) | (x))
#define CCI_REG16(x) ((2 << CCI_REG_WIDTH_SHIFT) | (x))
#define CCI_REG24(x) ((3 << CCI_REG_WIDTH_SHIFT) | (x))
#define CCI_REG32(x) ((4 << CCI_REG_WIDTH_SHIFT) | (x))
#define CCI_REG64(x) ((8 << CCI_REG_WIDTH_SHIFT) | (x))
#define CCI_REG16_LE(x) (CCI_REG_LE | (2U << CCI_REG_WIDTH_SHIFT) | (x))
#define CCI_REG24_LE(x) (CCI_REG_LE | (3U << CCI_REG_WIDTH_SHIFT) | (x))
#define CCI_REG32_LE(x) (CCI_REG_LE | (4U << CCI_REG_WIDTH_SHIFT) | (x))
#define CCI_REG64_LE(x) (CCI_REG_LE | (8U << CCI_REG_WIDTH_SHIFT) | (x))
/*
* TODOs
* - Move to active state api
* - Add 720 MBps speed mode to link_freq
* - HMAX/VMAX must be calculated based on link-freq to support this.
* - Support arbitrary cropping
*
* - account for the VOB
* - Identify where the HOB is coming from.
*
* - Remove 'events' that are not used.
* - Fix/remove HFLIP/VFLIP which aren't well supported at all.
* - Fix exposure and blanking calculations
*/
/* Chip ID */
#define IMX283_REG_CHIP_ID CCI_REG8(0x3000)
#define IMX283_CHIP_ID 0x0b // Default power on state
#define IMX283_REG_STANDBY CCI_REG8(0x3000)
#define IMX283_ACTIVE 0
#define IMX283_STANDBY BIT(0)
#define IMX283_STBLOGIC BIT(1)
#define IMX283_STBMIPI BIT(2)
#define IMX283_STBDV BIT(3)
#define IMX283_SLEEP BIT(4)
#define IMX283_REG_CLAMP CCI_REG8(0x3001)
#define IMX283_CLPSQRST BIT(4)
#define IMX283_REG_PLSTMG08 CCI_REG8(0x3003)
#define IMX283_PLSTMG08_VAL 0x77
#define IMX283_REG_MDSEL1 CCI_REG8(0x3004)
#define IMX283_REG_MDSEL2 CCI_REG8(0x3005)
#define IMX283_REG_MDSEL3 CCI_REG8(0x3006)
#define IMX283_REG_MDSEL4 CCI_REG8(0x3007)
#define IMX283_REG_SVR CCI_REG16_LE(0x3009)
#define IMX283_REG_HTRIMMING CCI_REG8(0x300b)
#define IMX283_MDVREV BIT(0) // VFLIP
#define IMX283_HTRIMMING_EN BIT(4)
#define IMX283_HTRIMMING_RESERVED BIT(5)
#define IMX283_REG_VWINPOS CCI_REG16_LE(0x300f)
#define IMX283_REG_VWIDCUT CCI_REG16_LE(0x3011)
#define IMX283_REG_MDSEL7 CCI_REG16_LE(0x3013)
/* CSI Clock Configuration */
#define IMX283_REG_TCLKPOST CCI_REG8(0x3018)
#define IMX283_REG_THSPREPARE CCI_REG8(0x301a)
#define IMX283_REG_THSZERO CCI_REG8(0x301c)
#define IMX283_REG_THSTRAIL CCI_REG8(0x3020)
#define IMX283_REG_TCLKPREPARE CCI_REG8(0x3022)
#define IMX283_REG_TCLKZERO CCI_REG16_LE(0x3024)
#define IMX283_REG_TLPX CCI_REG8(0x3026)
#define IMX283_REG_THSEXIT CCI_REG8(0x3028)
#define IMX283_REG_TCLKPRE CCI_REG8(0x302a)
#define IMX283_REG_Y_OUT_SIZE CCI_REG16_LE(0x302f)
#define IMX283_REG_WRITE_VSIZE CCI_REG16_LE(0x3031)
#define IMX283_REG_OB_SIZE_V CCI_REG8(0x3033)
/* HMAX internal HBLANK*/
#define IMX283_REG_HMAX CCI_REG16_LE(0x3036)
#define IMX283_HMAX_MAX 0xffff
/* VMAX internal VBLANK */
#define IMX283_REG_VMAX CCI_REG24_LE(0x3038)
#define IMX283_VMAX_MAX 0xfffff
/* SHR internal */
#define IMX283_REG_SHR CCI_REG16_LE(0x303b)
#define IMX283_SHR_MIN 11
/*
* Analog gain control
* Gain [dB] = –20log{(2048 – value [10:0]) /2048}
* Range: 0dB to approximately +27dB
*/
#define IMX283_REG_ANALOG_GAIN CCI_REG16_LE(0x3042)
#define IMX283_ANA_GAIN_MIN 0
#define IMX283_ANA_GAIN_MAX 1957
#define IMX283_ANA_GAIN_STEP 1
#define IMX283_ANA_GAIN_DEFAULT 0x0
/*
* Digital gain control
* Gain [dB] = value * 6
* Range: 0dB to +18db
*/
#define IMX283_REG_DIGITAL_GAIN CCI_REG8(0x3044)
#define IMX283_DGTL_GAIN_MIN 0
#define IMX283_DGTL_GAIN_MAX 3
#define IMX283_DGTL_GAIN_DEFAULT 0
#define IMX283_DGTL_GAIN_STEP 1
#define IMX283_REG_HTRIMMING_START CCI_REG16_LE(0x3058)
#define IMX283_REG_HTRIMMING_END CCI_REG16_LE(0x305a)
#define IMX283_REG_MDSEL18 CCI_REG16_LE(0x30f6)
/* Master Mode Operation Control */
#define IMX283_REG_XMSTA CCI_REG8(0x3105)
#define IMX283_XMSTA BIT(0)
#define IMX283_REG_SYNCDRV CCI_REG8(0x3107)
#define IMX283_SYNCDRV_XHS_XVS (0xa0 | 0x02)
#define IMX283_SYNCDRV_HIZ (0xa0 | 0x03)
/* PLL Standby */
#define IMX283_REG_STBPL CCI_REG8(0x320b)
#define IMX283_STBPL_NORMAL 0x00
#define IMX283_STBPL_STANDBY 0x03
/* Input Frequency Setting */
#define IMX283_REG_PLRD1 CCI_REG8(0x36c1)
#define IMX283_REG_PLRD2 CCI_REG16_LE(0x36c2)
#define IMX283_REG_PLRD3 CCI_REG8(0x36f7)
#define IMX283_REG_PLRD4 CCI_REG8(0x36f8)
#define IMX283_REG_PLSTMG02 CCI_REG8(0x36aa)
#define IMX283_PLSTMG02_VAL 0x00
#define IMX283_REG_EBD_X_OUT_SIZE CCI_REG16_LE(0x3a54)
/* Test pattern generator */
#define IMX283_REG_TPG_CTRL CCI_REG8(0x3156)
#define IMX283_TPG_CTRL_CLKEN BIT(0)
#define IMX283_TPG_CTRL_PATEN BIT(4)
#define IMX283_REG_TPG_PAT CCI_REG8(0x3157)
#define IMX283_TPG_PAT_ALL_000 0x00
#define IMX283_TPG_PAT_ALL_FFF 0x01
#define IMX283_TPG_PAT_ALL_555 0x02
#define IMX283_TPG_PAT_ALL_AAA 0x03
#define IMX283_TPG_PAT_H_COLOR_BARS 0x0a
#define IMX283_TPG_PAT_V_COLOR_BARS 0x0b
#define MHZ(x) ((x) * 1000 * 1000)
/* MIPI link speed is fixed at 1.44Gbps for all the modes */
#define IMX283_DEFAULT_LINK_FREQ MHZ(720)
/* Exposure control */
#define IMX283_EXPOSURE_MIN 52
#define IMX283_EXPOSURE_STEP 1
#define IMX283_EXPOSURE_DEFAULT 1000
#define IMX283_EXPOSURE_MAX 49865
/* Embedded metadata stream structure */
#define IMX283_EMBEDDED_LINE_WIDTH 16384
#define IMX283_NUM_EMBEDDED_LINES 1
#define IMAGE_PAD 0
/* imx283 native and active pixel array size. */
static const struct v4l2_rect imx283_native_area = {
.top = 0,
.left = 0,
.width = 5592,
.height = 3710,
};
static const struct v4l2_rect imx283_active_area = {
.top = 108,
.left = 40,
.width = 5472,
.height = 3648,
};
struct IMX283_reg_list {
unsigned int num_of_regs;
const struct cci_reg_sequence *regs;
};
/* Mode : resolution and related config&values */
struct imx283_mode {
unsigned int mode;
/* Bits per pixel */
unsigned int bpp;
/* Frame width */
unsigned int width;
/* Frame height */
unsigned int height;
/* minimum H-timing */
u64 min_HMAX;
/* minimum V-timing */
u64 min_VMAX;
/* default H-timing */
u64 default_HMAX;
/* default V-timing */
u64 default_VMAX;
/* minimum SHR */
u64 min_SHR;
/* Optical Blanking */
u32 horizontal_ob;
u32 vertical_ob;
/* Analog crop rectangle. */
struct v4l2_rect crop;
};
struct imx283_input_frequency {
unsigned int mhz;
unsigned int reg_count;
struct cci_reg_sequence regs[4];
};
static const struct imx283_input_frequency imx283_frequencies[] = {
{
.mhz = MHZ(6),
.reg_count = 4,
.regs = {
{ IMX283_REG_PLRD1, 0x00 },
{ IMX283_REG_PLRD2, 0x00f0 },
{ IMX283_REG_PLRD3, 0x00 },
{ IMX283_REG_PLRD4, 0xc0 },
},
},
{
.mhz = MHZ(12),
.reg_count = 4,
.regs = {
{ IMX283_REG_PLRD1, 0x01 },
{ IMX283_REG_PLRD2, 0x00f0 },
{ IMX283_REG_PLRD3, 0x01 },
{ IMX283_REG_PLRD4, 0xc0 },
},
},
{
.mhz = MHZ(18),
.reg_count = 4,
.regs = {
{ IMX283_REG_PLRD1, 0x01 },
{ IMX283_REG_PLRD2, 0x00a0 },
{ IMX283_REG_PLRD3, 0x01 },
{ IMX283_REG_PLRD4, 0x80 },
},
},
{
.mhz = MHZ(24),
.reg_count = 4,
.regs = {
{ IMX283_REG_PLRD1, 0x02 },
{ IMX283_REG_PLRD2, 0x00f0 },
{ IMX283_REG_PLRD3, 0x02 },
{ IMX283_REG_PLRD4, 0xc0 },
},
},
};
enum imx283_modes {
IMX283_MODE_0,
IMX283_MODE_1,
IMX283_MODE_1A,
IMX283_MODE_1S,
IMX283_MODE_2,
IMX283_MODE_2A,
IMX283_MODE_3,
IMX283_MODE_4,
IMX283_MODE_5,
IMX283_MODE_6,
};
struct imx283_readout_mode {
u64 mdsel1;
u64 mdsel2;
u64 mdsel3;
u64 mdsel4;
};
static const struct imx283_readout_mode imx283_readout_modes[] = {
/* All pixel scan modes */
[IMX283_MODE_0] = { 0x04, 0x03, 0x10, 0x00 }, /* 12 bit */
[IMX283_MODE_1] = { 0x04, 0x01, 0x00, 0x00 }, /* 10 bit */
[IMX283_MODE_1A] = { 0x04, 0x01, 0x20, 0x50 }, /* 10 bit */
[IMX283_MODE_1S] = { 0x04, 0x41, 0x20, 0x50 }, /* 10 bit */
/* Horizontal / Vertical 2/2-line binning */
[IMX283_MODE_2] = { 0x0d, 0x11, 0x50, 0x00 }, /* 12 bit */
[IMX283_MODE_2A] = { 0x0d, 0x11, 0x70, 0x50 }, /* 12 bit */
/* Horizontal / Vertical 3/3-line binning */
[IMX283_MODE_3] = { 0x1e, 0x18, 0x10, 0x00 }, /* 12 bit */
/* Veritcal 2/9 subsampling, horizontal 3 binning cropping */
[IMX283_MODE_4] = { 0x29, 0x18, 0x30, 0x50 }, /* 12 bit */
/* Vertical 2/19 subsampling binning, horizontal 3 binning */
[IMX283_MODE_5] = { 0x2d, 0x18, 0x10, 0x00 }, /* 12 bit */
/* Vertical 2 binning horizontal 2/4, subsampling 16:9 cropping */
[IMX283_MODE_6] = { 0x18, 0x21, 0x00, 0x09 }, /* 10 bit */
};
static const struct cci_reg_sequence mipi_data_rate_1440Mbps[] = {
/* The default register settings provide the 1440Mbps rate */
#if 0
{ CCI_REG8(0x36c5), 0x00 }, /* Undocumented */
{ CCI_REG8(0x3ac4), 0x00 }, /* Undocumented */
{ CCI_REG8(0x320B), 0x00 }, /* STBPL */
{ CCI_REG8(0x3018), 0xa7 }, /* TCLKPOST */
{ CCI_REG8(0x301A), 0x6f }, /* THSPREPARE */
{ CCI_REG8(0x301C), 0x9f }, /* THSZERO */
{ CCI_REG8(0x301E), 0x5f }, /* THSTRAIL */
{ CCI_REG8(0x3020), 0x5f }, /* TCLKTRAIL */
{ CCI_REG8(0x3022), 0x6f }, /* TCLKPREPARE */
{ CCI_REG8(0x3024), 0x7f }, /* TCLKZERO[7:0] */
{ CCI_REG8(0x3025), 0x01 }, /* TCLKZERO[8] */
{ CCI_REG8(0x3026), 0x4f }, /* TLPX*/
{ CCI_REG8(0x3028), 0x47 }, /* THSEXIT */
{ CCI_REG8(0x302A), 0x07 }, /* TCKLPRE */
{ CCI_REG8(0x3104), 0x02 }, /* SYSMODE */
#endif
};
static const struct cci_reg_sequence mipi_data_rate_720Mbps[] = {
/* Undocumented Arducam Additions "For 720MBps" Setting */
{ CCI_REG8(0x36c5), 0x01 }, /* Undocumented */
{ CCI_REG8(0x3ac4), 0x01 }, /* Undocumented */
{ CCI_REG8(0x320B), 0x00 }, /* STBPL */
{ CCI_REG8(0x3018), 0x77 }, /* TCLKPOST */
{ CCI_REG8(0x301A), 0x37 }, /* THSPREPARE */
{ CCI_REG8(0x301C), 0x67 }, /* THSZERO */
{ CCI_REG8(0x301E), 0x37 }, /* THSTRAIL */
{ CCI_REG8(0x3020), 0x37 }, /* TCLKTRAIL */
{ CCI_REG8(0x3022), 0x37 }, /* TCLKPREPARE */
{ CCI_REG8(0x3024), 0xDF }, /* TCLKZERO[7:0] */
{ CCI_REG8(0x3025), 0x00 }, /* TCLKZERO[8] */
{ CCI_REG8(0x3026), 0x2F }, /* TLPX*/
{ CCI_REG8(0x3028), 0x47 }, /* THSEXIT */
{ CCI_REG8(0x302A), 0x0F }, /* TCKLPRE */
{ CCI_REG8(0x3104), 0x02 }, /* SYSMODE */
};
static const s64 link_frequencies[] = {
MHZ(720), /* 1440 Mbps lane data rate */
MHZ(360), /* 720 Mbps data lane rate */
};
static const struct IMX283_reg_list link_freq_reglist[] = {
{ /* MHZ(720)*/
.num_of_regs = ARRAY_SIZE(mipi_data_rate_1440Mbps),
.regs = mipi_data_rate_1440Mbps,
},
{ /* MHZ(360) */
.num_of_regs = ARRAY_SIZE(mipi_data_rate_720Mbps),
.regs = mipi_data_rate_720Mbps,
},
};
#define CENTERED_RECTANGLE(rect, _width, _height) \
{ \
.left = rect.left + ((rect.width - (_width)) / 2), \
.top = rect.top + ((rect.height - (_height)) / 2), \
.width = (_width), \
.height = (_height), \
}
/* Mode configs */
static const struct imx283_mode supported_modes_12bit[] = {
{
/* 5568x3664 21.40fps readout mode 0 */
.mode = IMX283_MODE_0,
.bpp = 12,
.width = 5472 + 96,
.height = 3648 + 16,
.min_HMAX = 887,
.min_VMAX = 3793,
.default_HMAX = 900,
.default_VMAX = 4000,
.min_SHR = 12,
.horizontal_ob = 96,
.vertical_ob = 16,
.crop = CENTERED_RECTANGLE(imx283_active_area, 5472, 3648),
},
{
/* 2784x1828 51.80fps readout mode 2 */
.mode = IMX283_MODE_2,
.bpp = 12,
.width = (5472 + 96)/2,
.height = (3648 + 8)/2,
.min_HMAX = 362,
.min_VMAX = 3840,
.default_HMAX = 375,
.default_VMAX = 3840,
.min_SHR = 12,
.horizontal_ob = 96/2,
.vertical_ob = 8/2,
.crop = CENTERED_RECTANGLE(imx283_active_area, 5472, 3648),
},
};
static const struct imx283_mode supported_modes_10bit[] = {
{
/* 5568x3664 25.48fps readout mode 1 */
.mode = IMX283_MODE_1,
.bpp = 10,
.width = 5472 + 96,
.height = 3648 + 16,
.min_HMAX = 745,
.min_VMAX = 3793,
.default_HMAX = 750,
.default_VMAX = 3840,
.min_SHR = 12,
.horizontal_ob = 96,
.vertical_ob = 16,
.crop = CENTERED_RECTANGLE(imx283_active_area, 5472, 3648),
},
{
/* 5568x3094 30.17fps readout mode 1A */
.mode = IMX283_MODE_1A,
.bpp = 10,
.width = 5472 + 96,
.height = 3078 + 16,
.min_HMAX = 745,
.min_VMAX = 3203,
.default_HMAX = 750,
.default_VMAX = 3840,
.min_SHR = 12,
.horizontal_ob = 96,
.vertical_ob = 16,
.crop = CENTERED_RECTANGLE(imx283_active_area, 5472, 3078),
},
};
/*
* The supported formats.
* This table MUST contain 4 entries per format, to cover the various flip
* combinations in the order
* - no flip
* - h flip
* - v flip
* - h&v flips
*/
static const u32 codes[] = {
/* 12-bit modes. */
MEDIA_BUS_FMT_SRGGB12_1X12,
MEDIA_BUS_FMT_SGRBG12_1X12,
MEDIA_BUS_FMT_SGBRG12_1X12,
MEDIA_BUS_FMT_SBGGR12_1X12,
/* 10-bit modes. */
MEDIA_BUS_FMT_SRGGB10_1X10,
MEDIA_BUS_FMT_SGRBG10_1X10,
MEDIA_BUS_FMT_SGBRG10_1X10,
MEDIA_BUS_FMT_SBGGR10_1X10,
};
/* regulator supplies */
static const char * const imx283_supply_name[] = {
/* Supplies can be enabled in any order */
"VANA", /* Analog (2.8V) supply */
"VDIG", /* Digital Core (1.1V) supply */
"VDDL", /* IF (1.8V) supply */
};
#define imx283_NUM_SUPPLIES ARRAY_SIZE(imx283_supply_name)
/*
* Initialisation delay between XCLR low->high and the moment when the sensor
* can start capture (i.e. can leave software standby), given by T7 in the
* datasheet is 8ms. This does include I2C setup time as well.
*
* Note, that delay between XCLR low->high and reading the CCI ID register (T6
* in the datasheet) is much smaller - 600us.
*/
#define imx283_XCLR_MIN_DELAY_US 100000
#define imx283_XCLR_DELAY_RANGE_US 1000
struct imx283 {
struct device *dev;
const struct imx283_input_frequency *freq;
/* Selected link_frequency */
unsigned int link_freq_idx;
struct v4l2_subdev sd;
struct media_pad pad;
unsigned int fmt_code;
struct clk *xclk;
struct gpio_desc *reset_gpio;
struct regulator_bulk_data supplies[imx283_NUM_SUPPLIES];
struct v4l2_ctrl_handler ctrl_handler;
/* V4L2 Controls */
struct v4l2_ctrl *pixel_rate;
struct v4l2_ctrl *link_freq;
struct v4l2_ctrl *exposure;
struct v4l2_ctrl *vflip;
struct v4l2_ctrl *hflip;
struct v4l2_ctrl *vblank;
struct v4l2_ctrl *hblank;
/* Current mode */
const struct imx283_mode *mode;
u16 hmax;
u32 vmax;
/*
* Mutex for serialized access:
* Protect sensor module set pad format and start/stop streaming safely.
*/
struct mutex mutex;
/* Streaming on/off */
bool streaming;
};
int cci_read(struct imx283 *imx283, u32 reg, u64 *val, int *err) {
if (err && *err)
return *err;
struct i2c_client *client = v4l2_get_subdevdata(&imx283->sd);
u32 reg_addr = reg & CCI_REG_ADDR_MASK;
u32 width = (reg & CCI_REG_WIDTH_MASK) >> CCI_REG_WIDTH_SHIFT;
u8 addr_buf[2] = { reg_addr >> 8, reg_addr & 0xff };
u8 data_buf[8] = { 0 }; // Max 8 bytes for 64-bit data
struct i2c_msg msgs[2];
int ret;
if (width == 0 || width > 8) {
if (err) *err = -EINVAL;
return -EINVAL;
}
// Setup I2C message to write the register address
msgs[0].addr = client->addr;
msgs[0].flags = 0;
msgs[0].len = sizeof(addr_buf);
msgs[0].buf = addr_buf;
// Setup I2C message to read data from the register
msgs[1].addr = client->addr;
msgs[1].flags = I2C_M_RD;
msgs[1].len = width;
msgs[1].buf = data_buf;
ret = i2c_transfer(client->adapter, msgs, 2);
if (ret != 2) {
if (err) *err = -EIO;
return -EIO;
}
// Assuming big-endian register format
*val = 0;
for (int i = 0; i < width; i++) {
*val = (*val << 8) | data_buf[i];
}
return 0;
}
int cci_write(struct imx283 *imx283, u32 reg, u64 val, int *err) {
struct i2c_client *client = v4l2_get_subdevdata(&imx283->sd);
u32 reg_addr = reg & CCI_REG_ADDR_MASK;
u32 width = (reg & CCI_REG_WIDTH_MASK) >> CCI_REG_WIDTH_SHIFT;
bool is_le = reg & CCI_REG_LE;
u8 buf[10]; // Maximum size needed: 2 bytes for address + 8 bytes for data
int ret, i;
// Set the register address (big-endian)
buf[0] = (reg_addr >> 8) & 0xff;
buf[1] = reg_addr & 0xff;
// Set the data
for (i = 0; i < width; i++) {
if (is_le) {
// Little-endian: lower address bytes have lower value bytes
buf[2 + i] = (val >> (8 * i)) & 0xff;
} else {
// Big-endian: lower address bytes have higher value bytes
buf[2 + width - 1 - i] = (val >> (8 * i)) & 0xff;
}
}
ret = i2c_master_send(client, buf, 2 + width);
if (ret < 0) {
if (err) *err = ret;
return ret;
}
return 0;
}
int cci_multi_reg_write(struct imx283 *imx283, const struct cci_reg_sequence *regs, unsigned int num_regs, int *err) {
for (unsigned int i = 0; i < num_regs; i++) {
*err = cci_write(imx283, regs[i].reg, regs[i].val, err);
if (*err)
return *err;
}
return 0;
}
static inline struct imx283 *to_imx283(struct v4l2_subdev *_sd)
{
return container_of(_sd, struct imx283, sd);
}
static inline void get_mode_table(unsigned int code,
const struct imx283_mode **mode_list,
unsigned int *num_modes)
{
switch (code) {
/* 12-bit */
case MEDIA_BUS_FMT_SRGGB12_1X12:
case MEDIA_BUS_FMT_SGRBG12_1X12:
case MEDIA_BUS_FMT_SGBRG12_1X12:
case MEDIA_BUS_FMT_SBGGR12_1X12:
*mode_list = supported_modes_12bit;
*num_modes = ARRAY_SIZE(supported_modes_12bit);
break;
/* 10-bit */
case MEDIA_BUS_FMT_SRGGB10_1X10:
case MEDIA_BUS_FMT_SGRBG10_1X10:
case MEDIA_BUS_FMT_SGBRG10_1X10:
case MEDIA_BUS_FMT_SBGGR10_1X10:
*mode_list = supported_modes_10bit;
*num_modes = ARRAY_SIZE(supported_modes_10bit);
break;
default:
*mode_list = NULL;
*num_modes = 0;
}
}
/* Get bayer order based on flip setting. */
static u32 imx283_get_format_code(struct imx283 *imx283, u32 code)
{
unsigned int i;
lockdep_assert_held(&imx283->mutex);
for (i = 0; i < ARRAY_SIZE(codes); i++)
if (codes[i] == code)
break;
return codes[i];
}
static void imx283_set_default_format(struct imx283 *imx283)
{
/* Set default mode to max resolution */
imx283->mode = &supported_modes_12bit[0];
imx283->fmt_code = MEDIA_BUS_FMT_SRGGB12_1X12;
}
// Move this to .init_cfg
static int imx283_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
{
struct imx283 *imx283 = to_imx283(sd);
struct v4l2_mbus_framefmt *try_fmt_img =
v4l2_subdev_get_try_format(sd, fh->state, IMAGE_PAD);
struct v4l2_rect *try_crop;
mutex_lock(&imx283->mutex);
/* Initialize try_fmt for the image pad */
try_fmt_img->width = supported_modes_12bit[0].width;
try_fmt_img->height = supported_modes_12bit[0].height;
try_fmt_img->code = imx283_get_format_code(imx283,
MEDIA_BUS_FMT_SRGGB12_1X12);
try_fmt_img->field = V4L2_FIELD_NONE;
/* Initialize try_crop */
try_crop = v4l2_subdev_get_try_crop(sd, fh->state, IMAGE_PAD);
*try_crop = imx283_active_area;
mutex_unlock(&imx283->mutex);
return 0;
}
static u64 calculate_v4l2_cid_exposure(u64 hmax, u64 vmax, u64 shr, u64 svr, u64 offset) {
u64 numerator;
numerator = (vmax * (svr + 1) - shr) * hmax + offset;
do_div(numerator, hmax);
numerator = clamp_t(uint32_t, numerator, 0, 0xFFFFFFFF);
return numerator;
}
static void calculate_min_max_v4l2_cid_exposure(u64 hmax, u64 vmax, u64 min_shr, u64 svr, u64 offset, u64 *min_exposure, u64 *max_exposure) {
u64 max_shr = (svr + 1) * vmax - 4;
max_shr = min_t(uint64_t, max_shr, 0xFFFF);
*min_exposure = calculate_v4l2_cid_exposure(hmax, vmax, max_shr, svr, offset);
*max_exposure = calculate_v4l2_cid_exposure(hmax, vmax, min_shr, svr, offset);
}
/*
Integration Time [s] = [{VMAX × (SVR + 1) – (SHR)}
× HMAX + offset] / (72 × 10^6)
Integration Time [s] = exposure * HMAX / (72 × 10^6)
*/
static uint32_t calculate_shr(uint32_t exposure, uint32_t hmax, uint64_t vmax, uint32_t svr, uint32_t offset) {
uint64_t temp;
uint32_t shr;
temp = ((uint64_t)exposure * hmax - offset);
do_div(temp, hmax);
shr = (uint32_t)(vmax * (svr + 1) - temp);
return shr;
}
static const char * const imx283_tpg_menu[] = {
"Disabled",
"All 000h",
"All FFFh",
"All 555h",
"All AAAh",
"Horizontal color bars",
"Vertical color bars",
};
static const int imx283_tpg_val[] = {
IMX283_TPG_PAT_ALL_000,
IMX283_TPG_PAT_ALL_000,
IMX283_TPG_PAT_ALL_FFF,
IMX283_TPG_PAT_ALL_555,
IMX283_TPG_PAT_ALL_AAA,
IMX283_TPG_PAT_H_COLOR_BARS,
IMX283_TPG_PAT_V_COLOR_BARS,
};
static int imx283_update_test_pattern(struct imx283 *imx283, u32 pattern_index)
{
int ret;
if (pattern_index >= ARRAY_SIZE(imx283_tpg_val))
return -EINVAL;
if (pattern_index) {
ret = cci_write(imx283, IMX283_REG_TPG_PAT,
imx283_tpg_val[pattern_index], NULL);
if (ret)
return ret;
ret = cci_write(imx283, IMX283_REG_TPG_CTRL,
IMX283_TPG_CTRL_CLKEN | IMX283_TPG_CTRL_PATEN, NULL);
} else {
ret = cci_write(imx283, IMX283_REG_TPG_CTRL, 0x00, NULL);
}
return ret;
}
static int imx283_set_ctrl(struct v4l2_ctrl *ctrl)
{
struct imx283 *imx283 =
container_of(ctrl->handler, struct imx283, ctrl_handler);
const struct imx283_mode *mode = imx283->mode;
u64 shr, pixel_rate, hmax = 0;
int ret = 0;
//state = v4l2_subdev_get_locked_active_state(&imx283->sd);
//format = v4l2_subdev_get_pad_format(&imx283->sd, state, 0);
/*
* The VBLANK control may change the limits of usable exposure, so check
* and adjust if necessary.
*/
if (ctrl->id == V4L2_CID_VBLANK){
/* Honour the VBLANK limits when setting exposure. */
u64 current_exposure, max_exposure, min_exposure, vmax;
vmax = ((u64)mode->height + ctrl->val) ;
imx283->vmax = vmax;
calculate_min_max_v4l2_cid_exposure(imx283->hmax, imx283->vmax,
(u64)mode->min_SHR, 0, 209,
&min_exposure, &max_exposure);
current_exposure = clamp_t(uint32_t, current_exposure, min_exposure, max_exposure);
dev_info(imx283->dev,"exposure_max:%lld, exposure_min:%lld, current_exposure:%lld\n",max_exposure, min_exposure, current_exposure);
dev_info(imx283->dev, "\tVMAX:%d, HMAX:%d\n", imx283->vmax, imx283->hmax);
__v4l2_ctrl_modify_range(imx283->exposure, min_exposure,max_exposure, 1,current_exposure);
}
/*
* Applying V4L2 control value only happens
* when power is up for streaming
*/
if (pm_runtime_get_if_in_use(imx283->dev) == 0)
return 0;
switch (ctrl->id) {
case V4L2_CID_EXPOSURE:
{
dev_info(imx283->dev,"V4L2_CID_EXPOSURE : %d\n",ctrl->val);
dev_info(imx283->dev,"\tvblank:%d, hblank:%d\n",imx283->vblank->val, imx283->hblank->val);
dev_info(imx283->dev, "\tVMAX:%d, HMAX:%d\n", imx283->vmax, imx283->hmax);
shr = calculate_shr(ctrl->val, imx283->hmax, imx283->vmax, 0, 209);
dev_info(imx283->dev,"\tSHR:%lld\n",shr);
ret = cci_write(imx283, IMX283_REG_SHR, shr, NULL);
}
break;
case V4L2_CID_HBLANK:
{
dev_info(imx283->dev, "V4L2_CID_HBLANK : %d\n", ctrl->val);
//int hmax = (IMX283_NATIVE_WIDTH + ctrl->val) * 72000000; / IMX283_PIXEL_RATE;
pixel_rate = (u64)mode->width * 72000000;
do_div(pixel_rate, mode->min_HMAX);
hmax = (u64)(mode->width + ctrl->val) * 72000000;
do_div(hmax, pixel_rate);
imx283->hmax = hmax;
dev_info(imx283->dev, "\tHMAX : %d\n", imx283->hmax);
ret = cci_write(imx283, IMX283_REG_HMAX, hmax, NULL);
}
break;
case V4L2_CID_VBLANK:
{
dev_info(imx283->dev,"V4L2_CID_VBLANK : %d\n",ctrl->val);
imx283->vmax = ((u64)mode->height + ctrl->val);
dev_info(imx283->dev, "\tVMAX : %d\n", imx283->vmax);
ret = cci_write(imx283, IMX283_REG_VMAX, imx283->vmax, NULL);
}
break;
case V4L2_CID_ANALOGUE_GAIN:
dev_info(imx283->dev, "V4L2_CID_ANALOGUE_GAIN : %d\n", ctrl->val);
ret = cci_write(imx283, IMX283_REG_ANALOG_GAIN, ctrl->val, NULL);
break;
case V4L2_CID_DIGITAL_GAIN:
dev_info(imx283->dev, "V4L2_CID_DIGITAL_GAIN : %d\n", ctrl->val);
ret = cci_write(imx283, IMX283_REG_DIGITAL_GAIN, ctrl->val, NULL);
break;
case V4L2_CID_HFLIP:
case V4L2_CID_VFLIP:
//dev_info(imx283->dev,"V4L2_CID_HFLIP : %d\n",imx283->hflip->val);
//dev_info(imx283->dev,"V4L2_CID_VFLIP : %d\n",imx283->vflip->val);
//ret = imx283_write_reg_1byte(imx283, IMX283_REG_VFLIP, imx283->vflip->val);
break;
case V4L2_CID_TEST_PATTERN:
ret = imx283_update_test_pattern(imx283, ctrl->val);
break;
default:
dev_info(imx283->dev,
"ctrl(id:0x%x,val:0x%x) is not handled\n",
ctrl->id, ctrl->val);
//ret = -EINVAL;
break;
}
pm_runtime_put(imx283->dev);
return ret;
}
static const struct v4l2_ctrl_ops imx283_ctrl_ops = {
.s_ctrl = imx283_set_ctrl,
};
static int imx283_enum_mbus_code(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_mbus_code_enum *code)
{
struct imx283 *imx283 = to_imx283(sd);
if (code->index >= (ARRAY_SIZE(codes) / 4))
return -EINVAL;
code->code = imx283_get_format_code(imx283, codes[code->index * 4]);
return 0;
}
static int imx283_enum_frame_size(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_frame_size_enum *fse)
{
struct imx283 *imx283 = to_imx283(sd);
const struct imx283_mode *mode_list;
unsigned int num_modes;
get_mode_table(fse->code, &mode_list, &num_modes);
if (fse->index >= num_modes)
return -EINVAL;
if (fse->code != imx283_get_format_code(imx283, fse->code))
return -EINVAL;
fse->min_width = mode_list[fse->index].width;
fse->max_width = fse->min_width;
fse->min_height = mode_list[fse->index].height;
fse->max_height = fse->min_height;
return 0;
}
static void imx283_reset_colorspace(struct v4l2_mbus_framefmt *fmt)
{
fmt->colorspace = V4L2_COLORSPACE_RAW;
fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace);
fmt->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true,
fmt->colorspace,
fmt->ycbcr_enc);
fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt->colorspace);
}
static void imx283_update_image_pad_format(struct imx283 *imx283,
const struct imx283_mode *mode,
struct v4l2_subdev_format *fmt)
{
fmt->format.width = mode->width;
fmt->format.height = mode->height;
fmt->format.field = V4L2_FIELD_NONE;
imx283_reset_colorspace(&fmt->format);
}