diff --git a/CODEOWNERS b/CODEOWNERS index 4c737dc9642dd6..f22493bf63e473 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -422,7 +422,7 @@ /dts/arm/nxp/ @mmahadevan108 @dleach02 /dts/arm/nxp/nxp_s32* @manuargue /dts/arm/microchip/ @franciscomunoz @albertofloyd @sjvasanth1 -/dts/arm/rpi_pico/ @yonsch +/dts/arm/raspberry/rpi_pico/ @yonsch /dts/arm/silabs/efm32_pg_1b.dtsi @rdmeneze /dts/arm/silabs/efm32gg11b* @oanerer /dts/arm/silabs/efr32bg13p* @mnkp diff --git a/Kconfig.zephyr b/Kconfig.zephyr index 68abf89b42fc49..2675f9cd5218d8 100644 --- a/Kconfig.zephyr +++ b/Kconfig.zephyr @@ -765,7 +765,8 @@ config BUILD_OUTPUT_UF2_FAMILY_ID default "0xada52840" if SOC_NRF52840_QIAA default "0x4fb2d5bd" if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX default "0x2abc77ec" if SOC_SERIES_LPC55XXX - default "0xe48bff56" if SOC_SERIES_RP2XXX + default "0xe48bff56" if SOC_SERIES_RP2040 + default "0xe48bff57" if SOC_SERIES_RP2350 default "0x68ed2b88" if SOC_SERIES_SAMD21 default "0x55114460" if SOC_SERIES_SAMD51 default "0x647824b6" if SOC_SERIES_STM32F0X diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index f2d75109d55f48..a16d6accba25be 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -3501,7 +3501,7 @@ Raspberry Pi Pico Platforms: - boards/raspberrypi/ - boards/adafruit/kb2040/ - boards/sparkfun/pro_micro_rp2040/ - - dts/arm/rpi_pico/ + - dts/arm/raspberrypi/rpi_pico/ - dts/bindings/*/raspberrypi,pico* - drivers/*/*rpi_pico - drivers/*/*rpi_pico*/ diff --git a/boards/adafruit/kb2040/adafruit_kb2040-pinctrl.dtsi b/boards/adafruit/kb2040/adafruit_kb2040-pinctrl.dtsi index cf1289acedc34c..79681bb8ad3467 100644 --- a/boards/adafruit/kb2040/adafruit_kb2040-pinctrl.dtsi +++ b/boards/adafruit/kb2040/adafruit_kb2040-pinctrl.dtsi @@ -48,9 +48,6 @@ }; }; - clocks_default: clocks_default { - }; - ws2812_pio0_default: ws2812_pio0_default { ws2812 { pinmux = ; diff --git a/boards/adafruit/kb2040/adafruit_kb2040.dts b/boards/adafruit/kb2040/adafruit_kb2040.dts index 45ff45595d29c8..c79794217b54c6 100644 --- a/boards/adafruit/kb2040/adafruit_kb2040.dts +++ b/boards/adafruit/kb2040/adafruit_kb2040.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include +#include #include "adafruit_kb2040-pinctrl.dtsi" #include "sparkfun_pro_micro_connector.dtsi" #include @@ -56,11 +56,6 @@ }; }; -&clocks { - pinctrl-0 = <&clocks_default>; - pinctrl-names = "default"; -}; - &uart0 { current-speed = <115200>; status = "okay"; diff --git a/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040-pinctrl.dtsi b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040-pinctrl.dtsi index d2e84ae41f8637..561db005e65c55 100644 --- a/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040-pinctrl.dtsi +++ b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040-pinctrl.dtsi @@ -59,9 +59,6 @@ }; }; - clocks_default: clocks_default { - }; - ws2812_pio1_default: ws2812_pio1_default { ws2812 { pinmux = ; diff --git a/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts index 0209c1b86cd291..94fca20837c2de 100644 --- a/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts +++ b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include +#include #include "adafruit_qt_py_rp2040-pinctrl.dtsi" #include "seeed_xiao_connector.dtsi" #include @@ -56,11 +56,6 @@ }; }; -&clocks { - pinctrl-0 = <&clocks_default>; - pinctrl-names = "default"; -}; - &uart1 { current-speed = <115200>; status = "okay"; diff --git a/boards/raspberrypi/common/rpi_pico-led.dtsi b/boards/raspberrypi/common/rpi_pico-led.dtsi new file mode 100644 index 00000000000000..951e36260f2007 --- /dev/null +++ b/boards/raspberrypi/common/rpi_pico-led.dtsi @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2021 Yonatan Schachter + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Pico and Pico 2 boards (but not Pico W) have a common LED placement. */ +/ { + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; + label = "LED"; + }; + }; + + pwm_leds { + compatible = "pwm-leds"; + status = "disabled"; + pwm_led0: pwm_led_0 { + pwms = <&pwm 9 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "PWM_LED"; + }; + }; + + aliases { + led0 = &led0; + pwm-led0 = &pwm_led0; + }; +}; diff --git a/boards/raspberrypi/common/rpi_pico-pinctrl-common.dtsi b/boards/raspberrypi/common/rpi_pico-pinctrl-common.dtsi new file mode 100644 index 00000000000000..66ccfd2089592d --- /dev/null +++ b/boards/raspberrypi/common/rpi_pico-pinctrl-common.dtsi @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2021, Yonatan Schachter + * SPDX-License-Identifier: Apache-2.0 + */ + +/* The Pico and Pico 2 are pin compatible. */ +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , ; + input-enable; + input-schmitt-enable; + }; + }; + + i2c1_default: i2c1_default { + group1 { + pinmux = , ; + input-enable; + input-schmitt-enable; + }; + }; + + spi0_default: spi0_default { + group1 { + pinmux = , , ; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + + pwm_ch4b_default: pwm_ch4b_default { + group1 { + pinmux = ; + }; + }; + + adc_default: adc_default { + group1 { + pinmux = , , , ; + input-enable; + }; + }; +}; diff --git a/boards/raspberrypi/rpi_pico/board.cmake b/boards/raspberrypi/rpi_pico/board.cmake index e9cd4edc18f594..8d09fe3ab05ef4 100644 --- a/boards/raspberrypi/rpi_pico/board.cmake +++ b/boards/raspberrypi/rpi_pico/board.cmake @@ -13,7 +13,7 @@ # The value must be the 'stem' part of the name of one of the files # in the openocd interface configuration file. # The setting is store to CMakeCache.txt. -if ("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "") +if("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "") set(RPI_PICO_DEBUG_ADAPTER "cmsis-dap") endif() diff --git a/boards/raspberrypi/rpi_pico/doc/index.rst b/boards/raspberrypi/rpi_pico/doc/index.rst index 47ce4401f66bfc..c4ab80620f8e73 100644 --- a/boards/raspberrypi/rpi_pico/doc/index.rst +++ b/boards/raspberrypi/rpi_pico/doc/index.rst @@ -96,6 +96,8 @@ hardware features: - :kconfig:option:`CONFIG_SPI` - :dtcompatible:`raspberrypi,pico-spi-pio` +.. _rpi_pico_pin_mapping: + Pin Mapping =========== diff --git a/boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi b/boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi index 2b40cf3540bc09..811dafcdf7732c 100644 --- a/boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi +++ b/boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi @@ -6,7 +6,7 @@ #include -#include +#include #include "rpi_pico-pinctrl.dtsi" #include @@ -89,11 +89,6 @@ }; }; -&clocks { - pinctrl-0 = <&clocks_default>; - pinctrl-names = "default"; -}; - &uart0 { current-speed = <115200>; status = "okay"; diff --git a/boards/raspberrypi/rpi_pico/rpi_pico-pinctrl.dtsi b/boards/raspberrypi/rpi_pico/rpi_pico-pinctrl.dtsi index 761354420c6160..5556638daa6d8c 100644 --- a/boards/raspberrypi/rpi_pico/rpi_pico-pinctrl.dtsi +++ b/boards/raspberrypi/rpi_pico/rpi_pico-pinctrl.dtsi @@ -5,56 +5,4 @@ #include -&pinctrl { - uart0_default: uart0_default { - group1 { - pinmux = ; - }; - group2 { - pinmux = ; - input-enable; - }; - }; - - i2c0_default: i2c0_default { - group1 { - pinmux = , ; - input-enable; - input-schmitt-enable; - }; - }; - - i2c1_default: i2c1_default { - group1 { - pinmux = , ; - input-enable; - input-schmitt-enable; - }; - }; - - spi0_default: spi0_default { - group1 { - pinmux = , , ; - }; - group2 { - pinmux = ; - input-enable; - }; - }; - - pwm_ch4b_default: pwm_ch4b_default { - group1 { - pinmux = ; - }; - }; - - adc_default: adc_default { - group1 { - pinmux = , , , ; - input-enable; - }; - }; - - clocks_default: clocks_default { - }; -}; +#include "../common/rpi_pico-pinctrl-common.dtsi" diff --git a/boards/raspberrypi/rpi_pico/rpi_pico.dts b/boards/raspberrypi/rpi_pico/rpi_pico.dts index 97d721024d7497..807dc8e7800539 100644 --- a/boards/raspberrypi/rpi_pico/rpi_pico.dts +++ b/boards/raspberrypi/rpi_pico/rpi_pico.dts @@ -7,27 +7,4 @@ /dts-v1/; #include "rpi_pico-common.dtsi" - -/ { - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; - label = "LED"; - }; - }; - - pwm_leds { - compatible = "pwm-leds"; - status = "disabled"; - pwm_led0: pwm_led_0 { - pwms = <&pwm 9 PWM_MSEC(20) PWM_POLARITY_NORMAL>; - label = "PWM_LED"; - }; - }; - - aliases { - led0 = &led0; - pwm-led0 = &pwm_led0; - }; -}; +#include "../common/rpi_pico-led.dtsi" diff --git a/boards/raspberrypi/rpi_pico2/Kconfig.defconfig b/boards/raspberrypi/rpi_pico2/Kconfig.defconfig new file mode 100644 index 00000000000000..d122f3e4918aab --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Andrew Featherstone +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RPI_PICO2 + +config USB_SELF_POWERED + default n + +endif # BOARD_RPI_PICO2 diff --git a/boards/raspberrypi/rpi_pico2/Kconfig.rpi_pico2 b/boards/raspberrypi/rpi_pico2/Kconfig.rpi_pico2 new file mode 100644 index 00000000000000..bcce97758fbe4c --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/Kconfig.rpi_pico2 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Andrew Featherstone +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RPI_PICO2 + select SOC_RP2350A_M33 if BOARD_RPI_PICO2_RP2350A_M33 diff --git a/boards/raspberrypi/rpi_pico2/board.cmake b/boards/raspberrypi/rpi_pico2/board.cmake new file mode 100644 index 00000000000000..feae063129ac7a --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/board.cmake @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +if("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "") + set(RPI_PICO_DEBUG_ADAPTER "cmsis-dap") +endif() + +board_runner_args(openocd --cmd-pre-init "source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]") +board_runner_args(openocd --cmd-pre-init "source [find target/rp2350.cfg]") + +# The adapter speed is expected to be set by interface configuration. +# The Raspberry Pi's OpenOCD fork doesn't, so match their documentation at +# https://www.raspberrypi.com/documentation/microcontrollers/debug-probe.html#debugging-with-swd +board_runner_args(openocd --cmd-pre-init "set_adapter_speed_if_not_set 5000") + +board_runner_args(uf2 "--board-id=RP2350") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake) diff --git a/boards/raspberrypi/rpi_pico2/board.yml b/boards/raspberrypi/rpi_pico2/board.yml new file mode 100644 index 00000000000000..2ab8ee599891eb --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/board.yml @@ -0,0 +1,6 @@ +board: + name: rpi_pico2 + full_name: Raspberry Pi Pico 2 + vendor: raspberrypi + socs: + - name: rp2350a diff --git a/boards/raspberrypi/rpi_pico2/doc/img/rpi_pico2.webp b/boards/raspberrypi/rpi_pico2/doc/img/rpi_pico2.webp new file mode 100644 index 00000000000000..6a4895ba7b285b Binary files /dev/null and b/boards/raspberrypi/rpi_pico2/doc/img/rpi_pico2.webp differ diff --git a/boards/raspberrypi/rpi_pico2/doc/index.rst b/boards/raspberrypi/rpi_pico2/doc/index.rst new file mode 100644 index 00000000000000..1457a8b849e496 --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/doc/index.rst @@ -0,0 +1,93 @@ +.. zephyr:board:: rpi_pico2 + +Overview +******** + +The Raspberry Pi Pico 2 is the second-generation product in the Raspberry Pi +Pico family. From the `Raspberry Pi website `_ is referred to as Pico 2. + +There are many limitations of the board currently. Including but not limited to: +- The Zephyr build only supports configuring the RP2350A with the Cortex-M33 cores. +- As with the Pico 1, there's no support for running any code on the second core. + +Hardware +******** + +- Dual Cortex-M33 or Hazard3 processors at up to 150MHz +- 520KB of SRAM, and 4MB of on-board flash memory +- USB 1.1 with device and host support +- Low-power sleep and dormant modes +- Drag-and-drop programming using mass storage over USB +- 26 multi-function GPIO pins including 3 that can be used for ADC +- 2 SPI, 2 I2C, 2 UART, 3 12-bit 500ksps Analogue to Digital - Converter (ADC), 24 controllable PWM channels +- 2 Timer with 4 alarms, 1 AON Timer +- Temperature sensor +- 3 Programmable IO (PIO) blocks, 12 state machines total for custom peripheral support + + - Flexible, user-programmable high-speed IO + - Can emulate interfaces such as SD Card and VGA + +Supported Features +================== + +The ``rpi_pico2/rp2350a/m33`` board target supports the following +hardware features: + +.. list-table:: + :header-rows: 1 + + * - Peripheral + - Kconfig option + - Devicetree compatible + * - NVIC + - N/A + - :dtcompatible:`arm,v8m-nvic` + * - ADC + - :kconfig:option:`CONFIG_ADC` + - :dtcompatible:`raspberrypi,pico-adc` + * - Clock controller + - :kconfig:option:`CONFIG_CLOCK_CONTROL` + - :dtcompatible:`raspberrypi,pico-clock-controller` + * - Counter + - :kconfig:option:`CONFIG_COUNTER` + - :dtcompatible:`raspberrypi,pico-timer` + * - DMA + - :kconfig:option:`CONFIG_DMA` + - :dtcompatible:`raspberrypi,pico-dma` + * - GPIO + - :kconfig:option:`CONFIG_GPIO` + - :dtcompatible:`raspberrypi,pico-gpio` + * - HWINFO + - :kconfig:option:`CONFIG_HWINFO` + - N/A + * - I2C + - :kconfig:option:`CONFIG_I2C` + - :dtcompatible:`snps,designware-i2c` + * - PWM + - :kconfig:option:`CONFIG_PWM` + - :dtcompatible:`raspberrypi,pico-pwm` + * - SPI + - :kconfig:option:`CONFIG_SPI` + - :dtcompatible:`raspberrypi,pico-spi` + * - UART + - :kconfig:option:`CONFIG_SERIAL` + - :dtcompatible:`raspberrypi,pico-uart` + * - UART (PIO) + - :kconfig:option:`CONFIG_SERIAL` + - :dtcompatible:`raspberrypi,pico-uart-pio` + +Connections and IOs +=================== + +The default pin mapping is unchanged from the Pico 1 (see :ref:`rpi_pico_pin_mapping`). + +Programming and Debugging +************************* + +As with the Pico 1, the SWD interface can be used to program and debug the +device, e.g. using OpenOCD with the `Raspberry Pi Debug Probe `_ . + +References +********** + +.. target-notes:: diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2-pinctrl.dtsi b/boards/raspberrypi/rpi_pico2/rpi_pico2-pinctrl.dtsi new file mode 100644 index 00000000000000..a7841dc2da6ced --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2-pinctrl.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2024, Andrew Featherstone + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include "../common/rpi_pico-pinctrl-common.dtsi" diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2.dtsi b/boards/raspberrypi/rpi_pico2/rpi_pico2.dtsi new file mode 100644 index 00000000000000..85cdb97e8457ed --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2.dtsi @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2024 Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include +#include + +#include "rpi_pico2-pinctrl.dtsi" +#include "../common/rpi_pico-led.dtsi" + +/ { + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,code-partition = &code_partition; + }; + + aliases { + watchdog0 = &wdt0; + }; + + pico_header: connector { + compatible = "raspberrypi,pico-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 0 0>, /* GP0 */ + <1 0 &gpio0 1 0>, /* GP1 */ + <2 0 &gpio0 2 0>, /* GP2 */ + <3 0 &gpio0 3 0>, /* GP3 */ + <4 0 &gpio0 4 0>, /* GP4 */ + <5 0 &gpio0 5 0>, /* GP5 */ + <6 0 &gpio0 6 0>, /* GP6 */ + <7 0 &gpio0 7 0>, /* GP7 */ + <8 0 &gpio0 8 0>, /* GP8 */ + <9 0 &gpio0 9 0>, /* GP9 */ + <10 0 &gpio0 10 0>, /* GP10 */ + <11 0 &gpio0 11 0>, /* GP11 */ + <12 0 &gpio0 12 0>, /* GP12 */ + <13 0 &gpio0 13 0>, /* GP13 */ + <14 0 &gpio0 14 0>, /* GP14 */ + <15 0 &gpio0 15 0>, /* GP15 */ + <16 0 &gpio0 16 0>, /* GP16 */ + <17 0 &gpio0 17 0>, /* GP17 */ + <18 0 &gpio0 18 0>, /* GP18 */ + <19 0 &gpio0 19 0>, /* GP19 */ + <20 0 &gpio0 20 0>, /* GP20 */ + <21 0 &gpio0 21 0>, /* GP21 */ + <22 0 &gpio0 22 0>, /* GP22 */ + <26 0 &gpio0 26 0>, /* GP26 */ + <27 0 &gpio0 27 0>, /* GP27 */ + <28 0 &gpio0 28 0>; /* GP28 */ + }; +}; + +&flash0 { + reg = <0x10000000 DT_SIZE_M(4)>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserved memory for an image definition block. The block is much + * smaller than 256 bytes, but in practice the linker places the vector + * table at a much larger alignment offset. + */ + image_def: partition@0 { + label = "image_def"; + reg = <0x00000000 0x100>; + read-only; + }; + + /* + * Usable flash. Starts at 0x100, after the image definition block. + * The partition size is 4MB minus the 0x100 bytes taken by the + * image definition. + */ + code_partition: partition@100 { + label = "code-partition"; + reg = <0x100 (DT_SIZE_M(4) - 0x100)>; + read-only; + }; + }; +}; + +&uart0 { + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&spi0 { + clock-frequency = ; + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; +}; + +&i2c0 { + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c1 { + clock-frequency = ; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&adc { + pinctrl-0 = <&adc_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm { + pinctrl-0 = <&pwm_ch4b_default>; + pinctrl-names = "default"; + divider-int-0 = <255>; +}; + +&timer0 { + status = "okay"; +}; + +zephyr_udc0: &usbd { + status = "okay"; +}; + +pico_serial: &uart0 {}; diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33.dts b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33.dts new file mode 100644 index 00000000000000..f96491f44e2e5c --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33.dts @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2024 Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +/* The build system assumes that there's a cpucluster-specific file. + * + * This file provides composition of the device tree: + * 1. The common features of the SoC + * 2. Core-specific configuration. + * 3. Board-specific configuration. + */ +#include +#include + +/* there's nothing specific to the Cortex-M33 cores vs the (not yet + * implemented) Hazard3 cores. + */ +#include "rpi_pico2.dtsi" diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33.yaml b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33.yaml new file mode 100644 index 00000000000000..d3c340d88b14a1 --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33.yaml @@ -0,0 +1,21 @@ +identifier: rpi_pico2/rp2350a/m33 +name: Raspberry Pi Pico 2 (Cortex-M33) +type: mcu +arch: arm +flash: 4096 +ram: 520 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - adc + - clock + - counter + - dma + - gpio + - hwinfo + - i2c + - pwm + - spi + - uart diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_defconfig b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_defconfig new file mode 100644 index 00000000000000..8bd68e3511391d --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_defconfig @@ -0,0 +1,14 @@ +# This configuration is orthogonal to whether the Cortex-M33 or Hazard3 cores +# are in use, but Zephyr does not support providing a qualifier-agnostic +# _defconfig file. +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_CLOCK_CONTROL=y +CONFIG_CONSOLE=y +CONFIG_GPIO=y +CONFIG_RESET=y +CONFIG_SERIAL=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=150000000 +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/raspberrypi/rpi_pico2/support/openocd.cfg b/boards/raspberrypi/rpi_pico2/support/openocd.cfg new file mode 100644 index 00000000000000..82666bb53314ce --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/support/openocd.cfg @@ -0,0 +1,11 @@ +# Copyright (c) 2024 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +# Checking and set 'adapter speed'. +# Set the adaptor speed, if unset, and given as an argument. +proc set_adapter_speed_if_not_set { speed } { + puts "checking adapter speed..." + if { [catch {adapter speed} ret] } { + adapter speed $speed + } +} diff --git a/boards/seeed/xiao_rp2040/xiao_rp2040-pinctrl.dtsi b/boards/seeed/xiao_rp2040/xiao_rp2040-pinctrl.dtsi index 0e235884bf22c5..eb72fe503c00ee 100644 --- a/boards/seeed/xiao_rp2040/xiao_rp2040-pinctrl.dtsi +++ b/boards/seeed/xiao_rp2040/xiao_rp2040-pinctrl.dtsi @@ -57,9 +57,6 @@ }; }; - clocks_default: clocks_default { - }; - ws2812_pio0_default: ws2812_pio0_default { ws2812 { pinmux = ; diff --git a/boards/seeed/xiao_rp2040/xiao_rp2040.dts b/boards/seeed/xiao_rp2040/xiao_rp2040.dts index 0a52f47d672d4e..728af5e28b4f61 100644 --- a/boards/seeed/xiao_rp2040/xiao_rp2040.dts +++ b/boards/seeed/xiao_rp2040/xiao_rp2040.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include +#include #include "xiao_rp2040-pinctrl.dtsi" #include "seeed_xiao_connector.dtsi" #include @@ -86,11 +86,6 @@ }; }; -&clocks { - pinctrl-0 = <&clocks_default>; - pinctrl-names = "default"; -}; - &timer { status = "okay"; }; diff --git a/boards/sparkfun/pro_micro_rp2040/board.cmake b/boards/sparkfun/pro_micro_rp2040/board.cmake index 7d557630b9be38..9add174b5659af 100644 --- a/boards/sparkfun/pro_micro_rp2040/board.cmake +++ b/boards/sparkfun/pro_micro_rp2040/board.cmake @@ -16,7 +16,7 @@ # The value must be the 'stem' part of the name of one of the files # in the openocd interface configuration file. # The setting is store to CMakeCache.txt. -if ("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "") +if("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "") set(RPI_PICO_DEBUG_ADAPTER "cmsis-dap") endif() diff --git a/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040-pinctrl.dtsi b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040-pinctrl.dtsi index 5b9c353f802fc5..b2386014d6f718 100644 --- a/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040-pinctrl.dtsi +++ b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040-pinctrl.dtsi @@ -47,9 +47,6 @@ }; }; - clocks_default: clocks_default { - }; - ws2812_pio0_default: ws2812_pio_default { ws2812 { pinmux = ; diff --git a/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.dts b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.dts index 43761b85a14264..999da05609536e 100644 --- a/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.dts +++ b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "sparkfun_pro_micro_rp2040-pinctrl.dtsi" #include "sparkfun_pro_micro_connector.dtsi" #include @@ -58,11 +58,6 @@ }; }; -&clocks { - pinctrl-0 = <&clocks_default>; - pinctrl-names = "default"; -}; - &uart0 { current-speed = <115200>; status = "okay"; diff --git a/boards/wiznet/w5500_evb_pico/board.cmake b/boards/wiznet/w5500_evb_pico/board.cmake index e95d4d3767f655..a52ac5d15e0cb2 100644 --- a/boards/wiznet/w5500_evb_pico/board.cmake +++ b/boards/wiznet/w5500_evb_pico/board.cmake @@ -13,7 +13,7 @@ # The value must be the 'stem' part of the name of one of the files # in the openocd interface configuration file. # The setting is store to CMakeCache.txt. -if ("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "") +if("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "") set(RPI_PICO_DEBUG_ADAPTER "cmsis-dap") endif() diff --git a/boards/wiznet/w5500_evb_pico/w5500_evb_pico-pinctrl.dtsi b/boards/wiznet/w5500_evb_pico/w5500_evb_pico-pinctrl.dtsi index 761354420c6160..747b0d04e40958 100644 --- a/boards/wiznet/w5500_evb_pico/w5500_evb_pico-pinctrl.dtsi +++ b/boards/wiznet/w5500_evb_pico/w5500_evb_pico-pinctrl.dtsi @@ -54,7 +54,4 @@ input-enable; }; }; - - clocks_default: clocks_default { - }; }; diff --git a/boards/wiznet/w5500_evb_pico/w5500_evb_pico.dts b/boards/wiznet/w5500_evb_pico/w5500_evb_pico.dts index c14cb0b7d649d7..3f853ce06051b9 100644 --- a/boards/wiznet/w5500_evb_pico/w5500_evb_pico.dts +++ b/boards/wiznet/w5500_evb_pico/w5500_evb_pico.dts @@ -9,7 +9,7 @@ #include -#include +#include #include "w5500_evb_pico-pinctrl.dtsi" #include @@ -112,11 +112,6 @@ }; }; -&clocks { - pinctrl-0 = <&clocks_default>; - pinctrl-names = "default"; -}; - &uart0 { current-speed = <115200>; status = "okay"; diff --git a/doc/releases/migration-guide-4.1.rst b/doc/releases/migration-guide-4.1.rst index d35ab96073c736..a6f2383083ca4a 100644 --- a/doc/releases/migration-guide-4.1.rst +++ b/doc/releases/migration-guide-4.1.rst @@ -24,6 +24,8 @@ Kernel Boards ****** +* Raspberry Pi: ``CONFIG_SOC_SERIES_RP2XXX`` is renamed to :kconfig:option:`CONFIG_SOC_SERIES_RP2040`. + Modules ******* diff --git a/doc/releases/release-notes-4.1.rst b/doc/releases/release-notes-4.1.rst index 202fdb20489ba5..216ecd443d6bb5 100644 --- a/doc/releases/release-notes-4.1.rst +++ b/doc/releases/release-notes-4.1.rst @@ -60,10 +60,14 @@ Boards & SoC Support * Added support for these SoC series: + * Added Raspberry Pi RP2350 + * Made these changes in other SoC series: * Added support for these boards: + * :zephyr:board:`Raspberry Pi Pico 2 `: ``rpi_pico2`` + * Made these board changes: * Added support for the following shields: diff --git a/drivers/clock_control/clock_control_rpi_pico.c b/drivers/clock_control/clock_control_rpi_pico.c index e7f058ee32b507..e5d630aebf8971 100644 --- a/drivers/clock_control/clock_control_rpi_pico.c +++ b/drivers/clock_control/clock_control_rpi_pico.c @@ -10,7 +10,11 @@ #include #include #include -#include +#if defined(CONFIG_SOC_SERIES_RP2040) +#include +#else +#include +#endif #include #include @@ -18,6 +22,7 @@ #include #include #include +#include /* Undefine to prevent conflicts with header definitions */ #undef pll_sys @@ -77,6 +82,7 @@ #define CLOCK_FREQ_clk_gpout1 DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_gpout1), clock_frequency) #define CLOCK_FREQ_clk_gpout2 DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_gpout2), clock_frequency) #define CLOCK_FREQ_clk_gpout3 DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_gpout3), clock_frequency) +#define CLOCK_FREQ_clk_hstx DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_hstx), clock_frequency) #define CLOCK_FREQ_clk_ref DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_ref), clock_frequency) #define CLOCK_FREQ_clk_sys DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_sys), clock_frequency) #define CLOCK_FREQ_clk_usb DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_usb), clock_frequency) @@ -102,9 +108,16 @@ #define AUXSRC_clk_sys CLK_SYS #define AUXSRC_clk_usb CLK_USB #define AUXSRC_clk_adc CLK_ADC -#define AUXSRC_clk_rtc CLK_RTC #define AUXSRC_clk_gpin0 CLKSRC_GPIN0 #define AUXSRC_clk_gpin1 CLKSRC_GPIN1 +#if defined(CONFIG_SOC_SERIES_RP2040) +#define AUXSRC_clk_rtc CLK_RTC +#else +#define AUXSRC_pll_usb_primary_ref_opcg CLKSRC_PLL_PLL_USB_PRIMARY_REF_OPCG +#define AUXSRC_lposc LPOSC_CLKSRC +#define AUXSRC_clk_hstx CLK_HSTX +#define AUXSRC_otp_clk2fc OTP_CLK2FC +#endif #define AUXSTEM_clk_gpout0 CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_ #define AUXSTEM_clk_gpout1 CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_ @@ -114,8 +127,12 @@ #define AUXSTEM_clk_sys CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ #define AUXSTEM_clk_usb CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_ #define AUXSTEM_clk_adc CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_ -#define AUXSTEM_clk_rtc CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_ -#define AUXSTEM_clk_peri CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_ +#define AUXSTEM_clk_peri CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_ +#if defined(CONFIG_SOC_SERIES_RP2040) +#define AUXSTEM_clk_rtc CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_ +#else +#define AUXSTEM_clk_hstx CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_ +#endif #define TUPLE_ENTRY(n, p, i) \ { \ @@ -141,7 +158,9 @@ enum rpi_pico_clkid { rpi_pico_clkid_clk_peri = RPI_PICO_CLKID_CLK_PERI, rpi_pico_clkid_clk_usb = RPI_PICO_CLKID_CLK_USB, rpi_pico_clkid_clk_adc = RPI_PICO_CLKID_CLK_ADC, +#if defined(RPI_PICO_CLKID_CLK_RTC) rpi_pico_clkid_clk_rtc = RPI_PICO_CLKID_CLK_RTC, +#endif rpi_pico_clkid_pll_sys = RPI_PICO_CLKID_PLL_SYS, rpi_pico_clkid_pll_usb = RPI_PICO_CLKID_PLL_USB, rpi_pico_clkid_xosc = RPI_PICO_CLKID_XOSC, @@ -223,9 +242,11 @@ uint64_t rpi_pico_frequency_count(const struct device *dev, clock_control_subsys case rpi_pico_clkid_clk_adc: fc0_id = CLOCKS_FC0_SRC_VALUE_CLK_ADC; break; +#if defined(CONFIG_SOC_SERIES_RP2040) case rpi_pico_clkid_clk_rtc: fc0_id = CLOCKS_FC0_SRC_VALUE_CLK_RTC; break; +#endif case rpi_pico_clkid_pll_sys: fc0_id = CLOCKS_FC0_SRC_VALUE_PLL_SYS_CLKSRC_PRIMARY; break; @@ -284,10 +305,13 @@ static int rpi_pico_rosc_write(const struct device *dev, io_rw_32 *addr, uint32_ static enum rpi_pico_clkid rpi_pico_get_clock_src(const struct device *dev, enum rpi_pico_clkid id) { const struct clock_control_rpi_pico_config *config = dev->config; - enum rpi_pico_clkid srcid = rpi_pico_clkid_none; + enum rpi_pico_clkid srcid; - if (id == rpi_pico_clkid_clk_gpout0 || id == rpi_pico_clkid_clk_gpout1 || - id == rpi_pico_clkid_clk_gpout2 || id == rpi_pico_clkid_clk_gpout3) { + switch (id) { + case rpi_pico_clkid_clk_gpout0: + case rpi_pico_clkid_clk_gpout1: + case rpi_pico_clkid_clk_gpout2: + case rpi_pico_clkid_clk_gpout3: { const static enum rpi_pico_clkid table[] = { rpi_pico_clkid_pll_sys, rpi_pico_clkid_gpin0, @@ -298,7 +322,9 @@ static enum rpi_pico_clkid rpi_pico_get_clock_src(const struct device *dev, enum rpi_pico_clkid_clk_sys, rpi_pico_clkid_clk_usb, rpi_pico_clkid_clk_adc, +#if defined(CONFIG_SOC_SERIES_RP2040) rpi_pico_clkid_clk_rtc, +#endif rpi_pico_clkid_clk_ref, }; @@ -306,7 +332,9 @@ static enum rpi_pico_clkid rpi_pico_get_clock_src(const struct device *dev, enum uint32_t aux = ((clock_hw->ctrl & CTRL_AUXSRC_BITS) >> CTRL_AUXSRC_LSB); srcid = table[aux]; - } else if (id == rpi_pico_clkid_clk_ref) { + break; + } + case rpi_pico_clkid_clk_ref: { const static enum rpi_pico_clkid table[] = { rpi_pico_clkid_pll_usb, rpi_pico_clkid_gpin0, @@ -324,7 +352,9 @@ static enum rpi_pico_clkid rpi_pico_get_clock_src(const struct device *dev, enum } else { srcid = table[aux]; } - } else if (id == rpi_pico_clkid_clk_sys) { + break; + } + case rpi_pico_clkid_clk_sys: { const static enum rpi_pico_clkid table[] = { rpi_pico_clkid_pll_sys, rpi_pico_clkid_pll_usb, @@ -343,7 +373,9 @@ static enum rpi_pico_clkid rpi_pico_get_clock_src(const struct device *dev, enum } else { srcid = table[aux]; } - } else if (id == rpi_pico_clkid_clk_peri) { + break; + } + case rpi_pico_clkid_clk_peri: { const static enum rpi_pico_clkid table[] = { rpi_pico_clkid_clk_sys, rpi_pico_clkid_pll_sys, @@ -358,8 +390,16 @@ static enum rpi_pico_clkid rpi_pico_get_clock_src(const struct device *dev, enum uint32_t aux = ((clock_hw->ctrl & CTRL_AUXSRC_BITS) >> CTRL_AUXSRC_LSB); srcid = table[aux]; - } else if (id == rpi_pico_clkid_clk_usb || id == rpi_pico_clkid_clk_adc || - id == rpi_pico_clkid_clk_rtc) { + break; + } + case rpi_pico_clkid_clk_usb: + case rpi_pico_clkid_clk_adc: +#if defined(RPI_PICO_CLKID_CLK_RTC) + case rpi_pico_clkid_clk_rtc: +#else + +#endif + { const static enum rpi_pico_clkid table[] = { rpi_pico_clkid_pll_usb, rpi_pico_clkid_pll_sys, @@ -373,8 +413,16 @@ static enum rpi_pico_clkid rpi_pico_get_clock_src(const struct device *dev, enum uint32_t aux = ((clock_hw->ctrl & CTRL_AUXSRC_BITS) >> CTRL_AUXSRC_LSB); srcid = table[aux]; - } else if (id == rpi_pico_clkid_pll_sys || id == rpi_pico_clkid_pll_usb) { + break; + } + case rpi_pico_clkid_pll_sys: + case rpi_pico_clkid_pll_usb: { srcid = rpi_pico_clkid_xosc; + break; + } + default: + srcid = rpi_pico_clkid_none; + break; } return srcid; @@ -396,7 +444,9 @@ static bool rpi_pico_is_clock_enabled(const struct device *dev, enum rpi_pico_cl } else if (id == rpi_pico_clkid_clk_usb || id == rpi_pico_clkid_clk_peri || id == rpi_pico_clkid_clk_adc || +#if defined(RPI_PICO_CLKID_CLK_RTC) id == rpi_pico_clkid_clk_rtc || +#endif id == rpi_pico_clkid_clk_gpout0 || id == rpi_pico_clkid_clk_gpout1 || id == rpi_pico_clkid_clk_gpout2 || @@ -444,7 +494,9 @@ static float rpi_pico_calc_clock_freq(const struct device *dev, enum rpi_pico_cl if (id == rpi_pico_clkid_clk_sys || id == rpi_pico_clkid_clk_usb || id == rpi_pico_clkid_clk_adc || +#if defined(RPI_PICO_CLKID_CLK_RTC) id == rpi_pico_clkid_clk_rtc || +#endif id == rpi_pico_clkid_clk_ref || id == rpi_pico_clkid_clk_gpout0 || id == rpi_pico_clkid_clk_gpout1 || @@ -595,6 +647,7 @@ void rpi_pico_clkid_tuple_reorder_by_dependencies(struct rpi_pico_clkid_tuple *t static int clock_control_rpi_pico_init(const struct device *dev) { + const uint32_t cycles_per_tick = CLOCK_FREQ_xosc / 1000000; const struct clock_control_rpi_pico_config *config = dev->config; struct clock_control_rpi_pico_data *data = dev->data; clocks_hw_t *clocks_regs = config->clocks_regs; @@ -608,17 +661,26 @@ static int clock_control_rpi_pico_init(const struct device *dev) /* Reset all function before clock configuring */ reset_block(~(RESETS_RESET_IO_QSPI_BITS | RESETS_RESET_PADS_QSPI_BITS | RESETS_RESET_PLL_USB_BITS | RESETS_RESET_USBCTRL_BITS | - RESETS_RESET_PLL_USB_BITS | RESETS_RESET_SYSCFG_BITS | - RESETS_RESET_PLL_SYS_BITS)); + RESETS_RESET_SYSCFG_BITS | RESETS_RESET_PLL_SYS_BITS)); unreset_block_wait(RESETS_RESET_BITS & - ~(RESETS_RESET_ADC_BITS | RESETS_RESET_RTC_BITS | + ~(RESETS_RESET_ADC_BITS | +#if defined(RESETS_RESET_RTC_BITS) + RESETS_RESET_RTC_BITS | +#endif +#if defined(RESETS_RESET_HSTX_BITS) + RESETS_RESET_HSTX_BITS | +#endif RESETS_RESET_SPI0_BITS | RESETS_RESET_SPI1_BITS | RESETS_RESET_UART0_BITS | RESETS_RESET_UART1_BITS | - RESETS_RESET_USBCTRL_BITS | RESETS_RESET_PWM_BITS)); + RESETS_RESET_USBCTRL_BITS)); /* Start tick in watchdog */ - watchdog_hw->tick = ((CLOCK_FREQ_xosc/1000000) | WATCHDOG_TICK_ENABLE_BITS); + watchdog_start_tick(cycles_per_tick); +#if defined(CONFIG_SOC_SERIES_RP2350) + tick_start(TICK_TIMER0, cycles_per_tick); + tick_start(TICK_TIMER1, cycles_per_tick); +#endif clocks_regs->resus.ctrl = 0; @@ -714,7 +776,7 @@ static int clock_control_rpi_pico_init(const struct device *dev) } ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); - if (ret < 0) { + if (ret < 0 && ret != -ENOENT) { return ret; } @@ -756,8 +818,10 @@ BUILD_ASSERT(SRC_CLOCK_FREQ(clk_usb) >= CLOCK_FREQ_clk_usb, "clk_usb: clock divider is out of range"); BUILD_ASSERT(SRC_CLOCK_FREQ(clk_adc) >= CLOCK_FREQ_clk_adc, "clk_adc: clock divider is out of range"); +#if defined(CONFIG_SOC_SERIES_RP2040) BUILD_ASSERT(SRC_CLOCK_FREQ(clk_rtc) >= CLOCK_FREQ_clk_rtc, "clk_rtc: clock divider is out of range"); +#endif BUILD_ASSERT(SRC_CLOCK_FREQ(clk_peri) >= CLOCK_FREQ_clk_peri, "clk_peri: clock divider is out of range"); @@ -839,12 +903,21 @@ static const struct clock_control_rpi_pico_config clock_control_rpi_pico_config .source_rate = SRC_CLOCK_FREQ(clk_adc), .rate = CLOCK_FREQ(clk_adc), }, +#if defined(RPI_PICO_CLKID_CLK_RTC) [RPI_PICO_CLKID_CLK_RTC] = { .source = 0, .aux_source = CLOCK_AUX_SOURCE(clk_rtc), .source_rate = SRC_CLOCK_FREQ(clk_rtc), .rate = CLOCK_FREQ(clk_rtc), }, +#elif defined(RPI_PICO_CLKID_CLK_HSTX) + [RPI_PICO_CLKID_CLK_HSTX] = { + .source = 0, + .aux_source = CLOCK_AUX_SOURCE(clk_hstx), + .source_rate = SRC_CLOCK_FREQ(clk_hstx), + .rate = CLOCK_FREQ(clk_hstx), + }, +#endif }, .plls_data = { [RPI_PICO_PLL_SYS] = { diff --git a/drivers/counter/counter_rpi_pico_timer.c b/drivers/counter/counter_rpi_pico_timer.c index c2140d58777483..341aa20c923682 100644 --- a/drivers/counter/counter_rpi_pico_timer.c +++ b/drivers/counter/counter_rpi_pico_timer.c @@ -95,11 +95,11 @@ static int counter_rpi_pico_timer_set_alarm(const struct device *dev, uint8_t id chdata->callback = alarm_cfg->callback; chdata->user_data = alarm_cfg->user_data; - missed = hardware_alarm_set_target(id, alarm_at); + missed = timer_hardware_alarm_set_target(config->timer, id, alarm_at); if (missed) { if (alarm_cfg->flags & COUNTER_ALARM_CFG_EXPIRE_WHEN_LATE) { - hardware_alarm_force_irq(id); + timer_hardware_alarm_force_irq(config->timer, id); } chdata->callback = NULL; chdata->user_data = NULL; @@ -113,10 +113,11 @@ static int counter_rpi_pico_timer_cancel_alarm(const struct device *dev, uint8_t { struct counter_rpi_pico_timer_data *data = dev->data; struct counter_rpi_pico_timer_ch_data *chdata = &data->ch_data[id]; + const struct counter_rpi_pico_timer_config *config = dev->config; chdata->callback = NULL; chdata->user_data = NULL; - hardware_alarm_cancel(id); + timer_hardware_alarm_cancel(config->timer, id); return 0; } @@ -203,7 +204,8 @@ static const struct counter_driver_api counter_rpi_pico_driver_api = { #define RPI_PICO_TIMER_IRQ_ENABLE(node_id, name, idx) \ do { \ - hardware_alarm_set_callback(idx, counter_rpi_pico_irq_handle); \ + timer_hardware_alarm_set_callback((timer_hw_t *)DT_REG_ADDR(node_id), idx, \ + counter_rpi_pico_irq_handle); \ IRQ_CONNECT((DT_IRQ_BY_IDX(node_id, idx, irq)), \ (DT_IRQ_BY_IDX(node_id, idx, priority)), hardware_alarm_irq_handler, \ (DEVICE_DT_GET(node_id)), 0); \ diff --git a/drivers/dma/dma_rpi_pico.c b/drivers/dma/dma_rpi_pico.c index 57c23ced657f1b..3732ca6ead1c42 100644 --- a/drivers/dma/dma_rpi_pico.c +++ b/drivers/dma/dma_rpi_pico.c @@ -10,7 +10,11 @@ #include #include #include -#include +#if defined(CONFIG_SOC_SERIES_RP2040) +#include +#elif defined(CONFIG_SOC_SERIES_RP2350) +#include +#endif #include @@ -288,8 +292,7 @@ static bool dma_rpi_pico_api_chan_filter(const struct device *dev, int ch, void uint32_t filter; if (!filter_param) { - LOG_ERR("filter_param must not be NULL"); - return false; + return true; } filter = *((uint32_t *)filter_param); diff --git a/drivers/hwinfo/Kconfig b/drivers/hwinfo/Kconfig index 2e27074061929b..04cec3c6a42c0a 100644 --- a/drivers/hwinfo/Kconfig +++ b/drivers/hwinfo/Kconfig @@ -130,7 +130,7 @@ config HWINFO_IMXRT config HWINFO_RPI_PICO bool "Raspberry Pi Pico hwinfo driver" default y - depends on SOC_SERIES_RP2XXX + depends on SOC_FAMILY_RPI_PICO select HWINFO_HAS_DRIVER select PICOSDK_USE_FLASH help diff --git a/drivers/hwinfo/hwinfo_rpi_pico.c b/drivers/hwinfo/hwinfo_rpi_pico.c index 89d5cb5654cda5..b83078e4b494bf 100644 --- a/drivers/hwinfo/hwinfo_rpi_pico.c +++ b/drivers/hwinfo/hwinfo_rpi_pico.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2022 Yonatan Schachter + * Copyright (c) 2024 Andrew Featherstone * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,13 +8,23 @@ #include #include #include +#if defined(CONFIG_SOC_SERIES_RP2040) #include +#else +#include +#endif #define FLASH_RUID_DATA_BYTES 8 +#if defined(CONFIG_SOC_SERIES_RP2040) #define HAD_RUN_BIT BIT(VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_LSB) #define HAD_PSM_RESTART_BIT BIT(VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_LSB) #define HAD_POR_BIT BIT(VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_LSB) +#else +#define HAD_RUN_BIT BIT(POWMAN_CHIP_RESET_HAD_RUN_LOW_LSB) +#define HAD_PSM_RESTART_BIT BIT(POWMAN_CHIP_RESET_HAD_DP_RESET_REQ_LSB) +#define HAD_POR_BIT BIT(POWMAN_CHIP_RESET_HAD_POR_LSB) +#endif ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length) { @@ -41,7 +52,11 @@ ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length) int z_impl_hwinfo_get_reset_cause(uint32_t *cause) { uint32_t flags = 0; +#if defined(CONFIG_SOC_SERIES_RP2040) uint32_t reset_register = vreg_and_chip_reset_hw->chip_reset; +#else + uint32_t reset_register = powman_hw->chip_reset; +#endif if (reset_register & HAD_POR_BIT) { flags |= RESET_POR; @@ -54,6 +69,18 @@ int z_impl_hwinfo_get_reset_cause(uint32_t *cause) if (reset_register & HAD_PSM_RESTART_BIT) { flags |= RESET_DEBUG; } +#if defined(CONFIG_SOC_SERIES_RP2350) + if (reset_register & POWMAN_CHIP_RESET_HAD_BOR_BITS) { + flags |= RESET_BROWNOUT; + } + + if (reset_register & (POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM_BITS | + POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE_BITS | + POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_BITS | + POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC_BITS)) { + flags |= RESET_WATCHDOG; + } +#endif *cause = flags; return 0; @@ -69,6 +96,9 @@ int z_impl_hwinfo_clear_reset_cause(void) int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported) { *supported = RESET_PIN | RESET_DEBUG | RESET_POR; +#if defined(CONFIG_SOC_SERIES_RP2350) + *supported |= RESET_BROWNOUT | RESET_WATCHDOG; +#endif return 0; } diff --git a/drivers/watchdog/wdt_rpi_pico.c b/drivers/watchdog/wdt_rpi_pico.c index 7d3f2a5fc60784..d9ab8f4979620a 100644 --- a/drivers/watchdog/wdt_rpi_pico.c +++ b/drivers/watchdog/wdt_rpi_pico.c @@ -7,6 +7,7 @@ #define DT_DRV_COMPAT raspberrypi_pico_watchdog #include +#include #include #include #include @@ -15,9 +16,13 @@ #include LOG_MODULE_REGISTER(wdt_rpi_pico, CONFIG_WDT_LOG_LEVEL); +#ifdef CONFIG_SOC_RP2040 /* Maximum watchdog time is halved due to errata RP2040-E1 */ -#define RPI_PICO_MAX_WDT_TIME (0xffffff / 2) #define RPI_PICO_WDT_TIME_MULTIPLICATION_FACTOR 2 +#else +#define RPI_PICO_WDT_TIME_MULTIPLICATION_FACTOR 1 +#endif +#define RPI_PICO_MAX_WDT_TIME (0xffffff / RPI_PICO_WDT_TIME_MULTIPLICATION_FACTOR) /* Watchdog requires a 1MHz clock source, divided from the crystal oscillator */ #define RPI_PICO_CLK_REF_FREQ_WDT_TICK_DIVISOR 1000000 @@ -89,8 +94,13 @@ static int wdt_rpi_pico_setup(const struct device *dev, uint8_t options) return err; } +#ifdef CONFIG_SOC_RP2040 watchdog_hw->tick = (ref_clk / RPI_PICO_CLK_REF_FREQ_WDT_TICK_DIVISOR) | WATCHDOG_TICK_ENABLE_BITS; +#else + ticks_hw->ticks[TICK_WATCHDOG].cycles = ref_clk / RPI_PICO_CLK_REF_FREQ_WDT_TICK_DIVISOR; + ticks_hw->ticks[TICK_WATCHDOG].ctrl = TICKS_WATCHDOG_CTRL_ENABLE_BITS; +#endif return 0; } diff --git a/dts/arm/raspberrypi/rpi_pico/m33.dtsi b/dts/arm/raspberrypi/rpi_pico/m33.dtsi new file mode 100644 index 00000000000000..3f8ff861aad842 --- /dev/null +++ b/dts/arm/raspberrypi/rpi_pico/m33.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2024 Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/* Model in the device tree a Cortex-M33 core being 'plugged' into each + * 'socket' within the SoC. Within the datasheet these are core 0 and core 1. + */ +&cpu0 { + compatible = "arm,cortex-m33"; +}; + +&cpu1 { + compatible = "arm,cortex-m33"; +}; + +&nvic { + arm,num-irq-priority-bits = <4>; +}; diff --git a/dts/arm/rpi_pico/rp2040.dtsi b/dts/arm/raspberrypi/rpi_pico/rp2040.dtsi similarity index 98% rename from dts/arm/rpi_pico/rp2040.dtsi rename to dts/arm/raspberrypi/rpi_pico/rp2040.dtsi index 1709d01c970d4d..d2fed1b49fe1d4 100644 --- a/dts/arm/rpi_pico/rp2040.dtsi +++ b/dts/arm/raspberrypi/rpi_pico/rp2040.dtsi @@ -7,12 +7,15 @@ #include #include #include -#include +#include #include #include +#include #include -#include "rpi_pico_common.dtsi" +#ifndef RPI_PICO_DEFAULT_IRQ_PRIORITY +#define RPI_PICO_DEFAULT_IRQ_PRIORITY 3 +#endif / { aliases { diff --git a/dts/arm/raspberrypi/rpi_pico/rp2350.dtsi b/dts/arm/raspberrypi/rpi_pico/rp2350.dtsi new file mode 100644 index 00000000000000..687cafc19aade7 --- /dev/null +++ b/dts/arm/raspberrypi/rpi_pico/rp2350.dtsi @@ -0,0 +1,438 @@ +/* + * Copyright (c) 2024 Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include + +#ifndef RPI_PICO_DEFAULT_IRQ_PRIORITY +#define RPI_PICO_DEFAULT_IRQ_PRIORITY 7 +#endif + +/ { + aliases { + die-temp0 = &die_temp; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + /* There are two CPU sockets in the RP2350-series SoCs. + * Represent the sockets in the device tree as these two + * partially-defined CPU instances. Use a separate DTSI file to + * define what kind of CPU cores they are. + */ + cpu0: cpu@0 { + reg = <0>; + }; + + cpu1: cpu@1 { + reg = <1>; + }; + }; + + clocks { + clk_gpout0: clk-gpout0 { + compatible = "raspberrypi,pico-clock"; + clocks = <&pll_sys>; + clock-names = "pll_sys"; + clock-frequency = <150000000>; + #clock-cells = <0>; + #address-cells = <0>; + }; + + clk_gpout1: clk-gpout1 { + compatible = "raspberrypi,pico-clock"; + clocks = <&pll_sys>; + clock-names = "pll_sys"; + clock-frequency = <150000000>; + #clock-cells = <0>; + }; + + clk_gpout2: clk-gpout2 { + compatible = "raspberrypi,pico-clock"; + clocks = <&pll_sys>; + clock-names = "pll_sys"; + clock-frequency = <150000000>; + #clock-cells = <0>; + }; + + clk_gpout3: clk-gpout3 { + compatible = "raspberrypi,pico-clock"; + clocks = <&pll_sys>; + clock-names = "pll_sys"; + clock-frequency = <150000000>; + #clock-cells = <0>; + }; + + clk_hstx: clk-hstx { + compatible = "raspberrypi,pico-clock"; + clocks = <&pll_sys>; + clock-names = "pll_sys"; + clock-frequency = <150000000>; + #clock-cells = <0>; + }; + + clk_ref: clk-ref { + compatible = "raspberrypi,pico-clock"; + clocks = <&xosc>; + clock-names = "xosc"; + clock-frequency = <12000000>; + #clock-cells = <0>; + }; + + clk_sys: clk-sys { + compatible = "raspberrypi,pico-clock"; + clocks = <&pll_sys>; + clock-names = "pll_sys"; + clock-frequency = <150000000>; + #clock-cells = <0>; + }; + + clk_usb: clk-usb { + compatible = "raspberrypi,pico-clock"; + clocks = <&pll_usb>; + clock-names = "pll_usb"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + + clk_adc: clk-adc { + compatible = "raspberrypi,pico-clock"; + clocks = <&pll_usb>; + clock-names = "pll_usb"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + + clk_peri: clk-peri { + compatible = "raspberrypi,pico-clock"; + clocks = <&clk_sys>; + clock-names = "clk_sys"; + clock-frequency = <150000000>; + #clock-cells = <0>; + }; + + pll_sys: pll-sys { + compatible = "raspberrypi,pico-pll"; + clocks = <&xosc>; + clock-names = "xosc"; + clock-div= <1>; + fb-div= <125>; + post-div1 = <5>; + post-div2 = <2>; + #clock-cells = <0>; + }; + + pll_usb: pll-usb { + compatible = "raspberrypi,pico-pll"; + clocks = <&xosc>; + clock-names = "xosc"; + clock-div= <1>; + fb-div = <100>; + post-div1 = <5>; + post-div2 = <5>; + #clock-cells = <0>; + }; + + rosc: rosc { + compatible = "raspberrypi,pico-rosc"; + clock-frequency = <6500000>; + range = ; + stage-drive-strength = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>; + clock-div = <16>; + phase = <0>; + #clock-cells = <0>; + }; + + rosc_ph: rosc-ph { + compatible = "raspberrypi,pico-clock"; + clock-frequency = <6500000>; + clocks = <&rosc>; + clock-names = "rosc"; + #clock-cells = <0>; + }; + + xosc: xosc { + compatible = "raspberrypi,pico-xosc"; + clock-frequency = <12000000>; + #clock-cells = <0>; + }; + + gpin0: gpin0 { + compatible = "raspberrypi,pico-clock"; + status = "disabled"; + clock-frequency = <0>; + #clock-cells = <0>; + }; + + gpin1: gpin1 { + compatible = "raspberrypi,pico-clock"; + status = "disabled"; + clock-frequency = <0>; + #clock-cells = <0>; + }; + }; + + soc { + compatible = "raspberrypi,rp2350", "simple-bus"; + + sram0: memory@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 DT_SIZE_K(520)>; + }; + + qmi: flash-controller@400d0000 { + compatible = "raspberrypi,pico-flash-controller"; + reg = <0x400d0000 0xfc>; + + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@10000000 { + compatible = "soc-nv-flash"; + write-block-size = <1>; + erase-block-size = ; + }; + status = "disabled"; + }; + + reset: reset-controller@40020000 { + compatible = "raspberrypi,pico-reset"; + reg = <0x40020000 DT_SIZE_K(4)>; + reg-width = <4>; + active-low = <0>; + #reset-cells = <1>; + }; + + clocks: clock-controller@40010000 { + compatible = "raspberrypi,pico-clock-controller"; + reg = <0x40010000 DT_SIZE_K(4) + 0x40048000 DT_SIZE_K(4) + 0x40050000 DT_SIZE_K(4) + 0x40058000 DT_SIZE_K(4) + 0x400e8000 DT_SIZE_K(4)>; + reg-names = "clocks", "xosc", "pll_sys", "pll_usb", "rosc"; + #clock-cells = <1>; + status = "okay"; + clocks = <&clk_gpout0>, <&clk_gpout1>, <&clk_gpout2>, <&clk_gpout3>, + <&clk_hstx>, <&clk_ref>, <&clk_sys>, <&clk_peri>, + <&clk_usb>, <&clk_adc>, + <&pll_sys>, <&pll_usb>, <&xosc>, <&rosc>, <&rosc_ph>, + <&gpin0>, <&gpin1>; + clock-names = "clk_gpout0", "clk_gpout1", "clk_gpout2", "clk_gpout3", + "clk_hstx", "clk_ref", "clk_sys", "clk_peri", + "clk_usb", "clk_adc", + "pll_sys", "pll_usb", "xosc", "rosc", "rosc_ph", + "gpin0", "gpin1"; + }; + + gpio0: gpio@40028000 { + compatible = "raspberrypi,pico-gpio"; + reg = <0x40028000 DT_SIZE_K(4)>; + interrupts = <21 RPI_PICO_DEFAULT_IRQ_PRIORITY>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + uart0: uart@40070000 { + compatible = "raspberrypi,pico-uart", "arm,pl011"; + reg = <0x40070000 DT_SIZE_K(4)>; + clocks = <&clocks RPI_PICO_CLKID_CLK_PERI>; + resets = <&reset RPI_PICO_RESETS_RESET_UART0>; + interrupts = <33 RPI_PICO_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "uart0"; + status = "disabled"; + }; + + uart1: uart@40078000 { + compatible = "raspberrypi,pico-uart", "arm,pl011"; + reg = <0x40078000 DT_SIZE_K(4)>; + clocks = <&clocks RPI_PICO_CLKID_CLK_PERI>; + resets = <&reset RPI_PICO_RESETS_RESET_UART1>; + interrupts = <34 RPI_PICO_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "uart1"; + status = "disabled"; + }; + + spi0: spi@40080000 { + compatible = "raspberrypi,pico-spi", "arm,pl022"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40080000 DT_SIZE_K(4)>; + clocks = <&clocks RPI_PICO_CLKID_CLK_PERI>; + resets = <&reset RPI_PICO_RESETS_RESET_SPI0>; + interrupts = <31 RPI_PICO_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "spi0"; + status = "disabled"; + }; + + spi1: spi@40088000 { + compatible = "raspberrypi,pico-spi", "arm,pl022"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40088000 DT_SIZE_K(4)>; + resets = <&reset RPI_PICO_RESETS_RESET_SPI1>; + clocks = <&clocks RPI_PICO_CLKID_CLK_PERI>; + interrupts = <32 RPI_PICO_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "spi1"; + status = "disabled"; + }; + + i2c0: i2c@40090000 { + compatible = "raspberrypi,pico-i2c", "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40090000 DT_SIZE_K(4)>; + resets = <&reset RPI_PICO_RESETS_RESET_I2C0>; + clocks = <&clocks RPI_PICO_CLKID_CLK_SYS>; + interrupts = <36 RPI_PICO_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "i2c0"; + status = "disabled"; + }; + + i2c1: i2c@40098000 { + compatible = "raspberrypi,pico-i2c", "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40098000 DT_SIZE_K(4)>; + resets = <&reset RPI_PICO_RESETS_RESET_I2C1>; + clocks = <&clocks RPI_PICO_CLKID_CLK_SYS>; + interrupts = <37 RPI_PICO_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "i2c1"; + status = "disabled"; + }; + + adc: adc@400a0000 { + compatible = "raspberrypi,pico-adc"; + reg = <0x400a0000 DT_SIZE_K(4)>; + resets = <&reset RPI_PICO_RESETS_RESET_ADC>; + clocks = <&clocks RPI_PICO_CLKID_CLK_ADC>; + interrupts = <35 RPI_PICO_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "adc0"; + status = "disabled"; + #io-channel-cells = <1>; + }; + + pwm: pwm@400a8000 { + compatible = "raspberrypi,pico-pwm"; + reg = <0x400a8000 DT_SIZE_K(4)>; + resets = <&reset RPI_PICO_RESETS_RESET_PWM>; + clocks = <&clocks RPI_PICO_CLKID_CLK_SYS>; + interrupts = <8 RPI_PICO_DEFAULT_IRQ_PRIORITY>, + <9 RPI_PICO_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "PWM_IRQ_WRAP_0", + "PWM_IRQ_WRAP_1"; + status = "disabled"; + #pwm-cells = <3>; + }; + + timer0: timer@400b0000 { + compatible = "raspberrypi,pico-timer"; + reg = <0x400b0000 DT_SIZE_K(4)>; + resets = <&reset RPI_PICO_RESETS_RESET_TIMER0>; + clocks = <&clocks RPI_PICO_CLKID_CLK_REF>; + interrupts = <0 RPI_PICO_DEFAULT_IRQ_PRIORITY>, + <1 RPI_PICO_DEFAULT_IRQ_PRIORITY>, + <2 RPI_PICO_DEFAULT_IRQ_PRIORITY>, + <3 RPI_PICO_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "TIMER0_IRQ_0", + "TIMER0_IRQ_1", + "TIMER0_IRQ_2", + "TIMER0_IRQ_3"; + status = "disabled"; + }; + + timer1: timer@400b8000 { + compatible = "raspberrypi,pico-timer"; + reg = <0x400b8000 DT_SIZE_K(4)>; + resets = <&reset RPI_PICO_RESETS_RESET_TIMER1>; + clocks = <&clocks RPI_PICO_CLKID_CLK_REF>; + interrupts = <4 RPI_PICO_DEFAULT_IRQ_PRIORITY>, + <5 RPI_PICO_DEFAULT_IRQ_PRIORITY>, + <6 RPI_PICO_DEFAULT_IRQ_PRIORITY>, + <7 RPI_PICO_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "TIMER1_IRQ_0", + "TIMER1_IRQ_1", + "TIMER1_IRQ_2", + "TIMER1_IRQ_3"; + status = "disabled"; + }; + + wdt0: watchdog@400d8000 { + compatible = "raspberrypi,pico-watchdog"; + reg = <0x400d8000 DT_SIZE_K(4)>; + clocks = <&clocks RPI_PICO_CLKID_CLK_REF>; + status = "disabled"; + }; + + dma: dma@50000000 { + compatible = "raspberrypi,pico-dma"; + reg = <0x50000000 DT_SIZE_K(64)>; + resets = <&reset RPI_PICO_RESETS_RESET_DMA>; + clocks = <&clocks RPI_PICO_CLKID_CLK_SYS>; + interrupts = <10 RPI_PICO_DEFAULT_IRQ_PRIORITY>, + <11 RPI_PICO_DEFAULT_IRQ_PRIORITY>, + <12 RPI_PICO_DEFAULT_IRQ_PRIORITY>, + <13 RPI_PICO_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "dma0", "dma1", "dma2", "dma3"; + dma-channels = <16>; + status = "disabled"; + #dma-cells = <3>; + }; + + usbd: usbd@50100000 { + compatible = "raspberrypi,pico-usbd"; + reg = <0x50100000 0x10000>; + resets = <&reset RPI_PICO_RESETS_RESET_USBCTRL>; + clocks = <&clocks RPI_PICO_CLKID_CLK_USB>; + interrupts = <14 RPI_PICO_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "usbctrl"; + num-bidir-endpoints = <16>; + status = "disabled"; + }; + + pio0: pio@50200000 { + compatible = "raspberrypi,pico-pio"; + reg = <0x50200000 DT_SIZE_K(4)>; + clocks = <&clocks RPI_PICO_CLKID_CLK_SYS>; + resets = <&reset RPI_PICO_RESETS_RESET_PIO0>; + status = "disabled"; + }; + + pio1: pio@50300000 { + compatible = "raspberrypi,pico-pio"; + reg = <0x50300000 DT_SIZE_K(4)>; + clocks = <&clocks RPI_PICO_CLKID_CLK_SYS>; + resets = <&reset RPI_PICO_RESETS_RESET_PIO1>; + status = "disabled"; + }; + + pio2: pio@50400000 { + compatible = "raspberrypi,pico-pio"; + reg = <0x50400000 DT_SIZE_K(4)>; + clocks = <&clocks RPI_PICO_CLKID_CLK_SYS>; + resets = <&reset RPI_PICO_RESETS_RESET_PIO2>; + status = "disabled"; + }; + }; + + pinctrl: pin-controller { + compatible = "raspberrypi,pico-pinctrl"; + status = "okay"; + }; + + die_temp: dietemp { + compatible = "raspberrypi,pico-temp"; + status = "disabled"; + }; +}; diff --git a/dts/arm/raspberrypi/rpi_pico/rp2350a.dtsi b/dts/arm/raspberrypi/rpi_pico/rp2350a.dtsi new file mode 100644 index 00000000000000..762af8d82c3a7d --- /dev/null +++ b/dts/arm/raspberrypi/rpi_pico/rp2350a.dtsi @@ -0,0 +1,9 @@ +#include + +&gpio0 { + ngpios = <30>; +}; + +&die_temp { + io-channels = <&adc 4>; +}; diff --git a/dts/arm/rpi_pico/rpi_pico_common.dtsi b/dts/arm/rpi_pico/rpi_pico_common.dtsi deleted file mode 100644 index 58e7fff37201e3..00000000000000 --- a/dts/arm/rpi_pico/rpi_pico_common.dtsi +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2021 Yonatan Schachter - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef RPI_PICO_DEFAULT_IRQ_PRIORITY -#define RPI_PICO_DEFAULT_IRQ_PRIORITY 3 -#endif - -#define RPI_PICO_RESETS_RESET_ADC 0 -#define RPI_PICO_RESETS_RESET_BUSCTRL 1 -#define RPI_PICO_RESETS_RESET_DMA 2 -#define RPI_PICO_RESETS_RESET_I2C0 3 -#define RPI_PICO_RESETS_RESET_I2C1 4 -#define RPI_PICO_RESETS_RESET_IO_BANK0 5 -#define RPI_PICO_RESETS_RESET_IO_QSPI 6 -#define RPI_PICO_RESETS_RESET_JTAG 7 -#define RPI_PICO_RESETS_RESET_PADS_BANK0 8 -#define RPI_PICO_RESETS_RESET_PADS_QSPI 9 -#define RPI_PICO_RESETS_RESET_PIO0 10 -#define RPI_PICO_RESETS_RESET_PIO1 11 -#define RPI_PICO_RESETS_RESET_PLL_SYS 12 -#define RPI_PICO_RESETS_RESET_PLL_USB 13 -#define RPI_PICO_RESETS_RESET_PWM 14 -#define RPI_PICO_RESETS_RESET_RTC 15 -#define RPI_PICO_RESETS_RESET_SPI0 16 -#define RPI_PICO_RESETS_RESET_SPI1 17 -#define RPI_PICO_RESETS_RESET_SYSCFG 18 -#define RPI_PICO_RESETS_RESET_SYSINFO 19 -#define RPI_PICO_RESETS_RESET_TBMAN 20 -#define RPI_PICO_RESETS_RESET_TIMER 21 -#define RPI_PICO_RESETS_RESET_UART0 22 -#define RPI_PICO_RESETS_RESET_UART1 23 -#define RPI_PICO_RESETS_RESET_USBCTRL 24 diff --git a/dts/bindings/clock/raspberrypi,pico-xosc.yaml b/dts/bindings/clock/raspberrypi,pico-xosc.yaml index de01d3c4d5e9f9..924db759ae854a 100644 --- a/dts/bindings/clock/raspberrypi,pico-xosc.yaml +++ b/dts/bindings/clock/raspberrypi,pico-xosc.yaml @@ -11,4 +11,6 @@ include: raspberrypi,pico-clock.yaml properties: startup-delay-multiplier: type: int - description: Startup delay multiplier + default: 1 + description: | + Startup delay multiplier. The default value matches the Pico SDK. diff --git a/dts/bindings/dma/raspberrypi,pico-dma.yaml b/dts/bindings/dma/raspberrypi,pico-dma.yaml index 10263958b1372f..8c74377d199e4a 100644 --- a/dts/bindings/dma/raspberrypi,pico-dma.yaml +++ b/dts/bindings/dma/raspberrypi,pico-dma.yaml @@ -7,7 +7,8 @@ description: | channel: Select channel for data transmitting slot: Select peripheral data request - Use the definitions defined in `zephyr/dt-bindings/dma/rpi_pico_dma.h`. + Use the definitions defined in `zephyr/dt-bindings/dma/rpi-pico-dma-rp2040.h`, + or `zephyr/dt-bindings/dma/rpi-pico-dma-rp2350.h` channel-config: A 32bit mask specifying the DMA channel configuration - bit 3: Enable Quiet IRQ diff --git a/include/zephyr/dt-bindings/clock/rpi_pico_clock.h b/include/zephyr/dt-bindings/clock/rpi_pico_clock_common.h similarity index 77% rename from include/zephyr/dt-bindings/clock/rpi_pico_clock.h rename to include/zephyr/dt-bindings/clock/rpi_pico_clock_common.h index 07522be66329c8..f19c9baaa645ed 100644 --- a/include/zephyr/dt-bindings/clock/rpi_pico_clock.h +++ b/include/zephyr/dt-bindings/clock/rpi_pico_clock_common.h @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_CLOCK_H_ -#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_CLOCK_H_ +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_CLOCK_COMMON_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_CLOCK_COMMON_H_ #define RPI_PICO_PLL_SYS 0 #define RPI_PICO_PLL_USB 1 @@ -21,9 +21,7 @@ #define RPI_PICO_CLKID_CLK_REF 4 #define RPI_PICO_CLKID_CLK_SYS 5 #define RPI_PICO_CLKID_CLK_PERI 6 -#define RPI_PICO_CLKID_CLK_USB 7 -#define RPI_PICO_CLKID_CLK_ADC 8 -#define RPI_PICO_CLKID_CLK_RTC 9 +/* N.b. clock ids 7-9 are defined in SoC-specific files. */ #define RPI_PICO_CLKID_PLL_SYS 10 #define RPI_PICO_CLKID_PLL_USB 11 @@ -41,4 +39,4 @@ #define RPI_PICO_CLOCK_COUNT 10 -#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_CLOCK_H_ */ +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_CLOCK_COMMON_H_ */ diff --git a/include/zephyr/dt-bindings/clock/rpi_pico_rp2040_clock.h b/include/zephyr/dt-bindings/clock/rpi_pico_rp2040_clock.h new file mode 100644 index 00000000000000..e0c679b4110373 --- /dev/null +++ b/include/zephyr/dt-bindings/clock/rpi_pico_rp2040_clock.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2022 Andrei-Edward Popa + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_RP2040_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_RP2040_CLOCK_H_ + +#include "rpi_pico_clock_common.h" + +#define RPI_PICO_CLKID_CLK_USB 7 +#define RPI_PICO_CLKID_CLK_ADC 8 +#define RPI_PICO_CLKID_CLK_RTC 9 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_RP2040_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/rpi_pico_rp2350_clock.h b/include/zephyr/dt-bindings/clock/rpi_pico_rp2350_clock.h new file mode 100644 index 00000000000000..7a5e48c284f46c --- /dev/null +++ b/include/zephyr/dt-bindings/clock/rpi_pico_rp2350_clock.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2024 Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_RP2350_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_RP2350_CLOCK_H_ + +#include "rpi_pico_clock_common.h" + +#define RPI_PICO_CLKID_CLK_HSTX 7 +#define RPI_PICO_CLKID_CLK_USB 8 +#define RPI_PICO_CLKID_CLK_ADC 9 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_RP2350_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/dma/rpi-pico-dma-common.h b/include/zephyr/dt-bindings/dma/rpi-pico-dma-common.h new file mode 100644 index 00000000000000..8a17cc830ebae9 --- /dev/null +++ b/include/zephyr/dt-bindings/dma/rpi-pico-dma-common.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2023 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RPI_PICO_DMA_COMMON_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_RPI_PICO_DMA_COMMON_H_ + +/* + * Use lower 6-bit of inverted DREQ value for `slot` cell. + * Need to be able to work for memory-to-memory transfer + * with zero, which is the default value. + */ +#define RPI_PICO_DMA_SLOT_TO_DREQ(s) (~(s)&0x3F) +#define RPI_PICO_DMA_DREQ_TO_SLOT RPI_PICO_DMA_SLOT_TO_DREQ + +#define RPI_PICO_DMA_SLOT_PIO0_TX0 RPI_PICO_DMA_DREQ_TO_SLOT(0x00) +#define RPI_PICO_DMA_SLOT_PIO0_TX1 RPI_PICO_DMA_DREQ_TO_SLOT(0x01) +#define RPI_PICO_DMA_SLOT_PIO0_TX2 RPI_PICO_DMA_DREQ_TO_SLOT(0x02) +#define RPI_PICO_DMA_SLOT_PIO0_TX3 RPI_PICO_DMA_DREQ_TO_SLOT(0x03) +#define RPI_PICO_DMA_SLOT_PIO0_RX0 RPI_PICO_DMA_DREQ_TO_SLOT(0x04) +#define RPI_PICO_DMA_SLOT_PIO0_RX1 RPI_PICO_DMA_DREQ_TO_SLOT(0x05) +#define RPI_PICO_DMA_SLOT_PIO0_RX2 RPI_PICO_DMA_DREQ_TO_SLOT(0x06) +#define RPI_PICO_DMA_SLOT_PIO0_RX3 RPI_PICO_DMA_DREQ_TO_SLOT(0x07) +#define RPI_PICO_DMA_SLOT_PIO1_TX0 RPI_PICO_DMA_DREQ_TO_SLOT(0x08) +#define RPI_PICO_DMA_SLOT_PIO1_TX1 RPI_PICO_DMA_DREQ_TO_SLOT(0x09) +#define RPI_PICO_DMA_SLOT_PIO1_TX2 RPI_PICO_DMA_DREQ_TO_SLOT(0x0A) +#define RPI_PICO_DMA_SLOT_PIO1_TX3 RPI_PICO_DMA_DREQ_TO_SLOT(0x0B) +#define RPI_PICO_DMA_SLOT_PIO1_RX0 RPI_PICO_DMA_DREQ_TO_SLOT(0x0C) +#define RPI_PICO_DMA_SLOT_PIO1_RX1 RPI_PICO_DMA_DREQ_TO_SLOT(0x0D) +#define RPI_PICO_DMA_SLOT_PIO1_RX2 RPI_PICO_DMA_DREQ_TO_SLOT(0x0E) +#define RPI_PICO_DMA_SLOT_PIO1_RX3 RPI_PICO_DMA_DREQ_TO_SLOT(0x0F) + +#define RPI_PICO_DMA_SLOT_DMA_TIMER0 RPI_PICO_DMA_DREQ_TO_SLOT(0x3B) +#define RPI_PICO_DMA_SLOT_DMA_TIMER1 RPI_PICO_DMA_DREQ_TO_SLOT(0x3C) +#define RPI_PICO_DMA_SLOT_DMA_TIMER2 RPI_PICO_DMA_DREQ_TO_SLOT(0x3D) +#define RPI_PICO_DMA_SLOT_DMA_TIMER3 RPI_PICO_DMA_DREQ_TO_SLOT(0x3E) +#define RPI_PICO_DMA_SLOT_FORCE RPI_PICO_DMA_DREQ_TO_SLOT(0x3F) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RPI_PICO_DMA_COMMON_H_ */ diff --git a/include/zephyr/dt-bindings/dma/rpi-pico-dma-rp2040.h b/include/zephyr/dt-bindings/dma/rpi-pico-dma-rp2040.h new file mode 100644 index 00000000000000..2ef5f4efa5f10b --- /dev/null +++ b/include/zephyr/dt-bindings/dma/rpi-pico-dma-rp2040.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2023 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RPI_PICO_DMA_RP2040_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_RPI_PICO_DMA_RP2040_H_ + +#include "rpi-pico-dma-common.h" + +#define RPI_PICO_DMA_SLOT_SPI0_TX RPI_PICO_DMA_DREQ_TO_SLOT(0x10) +#define RPI_PICO_DMA_SLOT_SPI0_RX RPI_PICO_DMA_DREQ_TO_SLOT(0x11) +#define RPI_PICO_DMA_SLOT_SPI1_TX RPI_PICO_DMA_DREQ_TO_SLOT(0x12) +#define RPI_PICO_DMA_SLOT_SPI1_RX RPI_PICO_DMA_DREQ_TO_SLOT(0x13) +#define RPI_PICO_DMA_SLOT_UART0_TX RPI_PICO_DMA_DREQ_TO_SLOT(0x14) +#define RPI_PICO_DMA_SLOT_UART0_RX RPI_PICO_DMA_DREQ_TO_SLOT(0x15) +#define RPI_PICO_DMA_SLOT_UART1_TX RPI_PICO_DMA_DREQ_TO_SLOT(0x16) +#define RPI_PICO_DMA_SLOT_UART1_RX RPI_PICO_DMA_DREQ_TO_SLOT(0x17) +#define RPI_PICO_DMA_SLOT_PWM_WRAP0 RPI_PICO_DMA_DREQ_TO_SLOT(0x18) +#define RPI_PICO_DMA_SLOT_PWM_WRAP1 RPI_PICO_DMA_DREQ_TO_SLOT(0x19) +#define RPI_PICO_DMA_SLOT_PWM_WRAP2 RPI_PICO_DMA_DREQ_TO_SLOT(0x1A) +#define RPI_PICO_DMA_SLOT_PWM_WRAP3 RPI_PICO_DMA_DREQ_TO_SLOT(0x1B) +#define RPI_PICO_DMA_SLOT_PWM_WRAP4 RPI_PICO_DMA_DREQ_TO_SLOT(0x1C) +#define RPI_PICO_DMA_SLOT_PWM_WRAP5 RPI_PICO_DMA_DREQ_TO_SLOT(0x1D) +#define RPI_PICO_DMA_SLOT_PWM_WRAP6 RPI_PICO_DMA_DREQ_TO_SLOT(0x1E) +#define RPI_PICO_DMA_SLOT_PWM_WRAP7 RPI_PICO_DMA_DREQ_TO_SLOT(0x1F) +#define RPI_PICO_DMA_SLOT_I2C0_TX RPI_PICO_DMA_DREQ_TO_SLOT(0x30) +#define RPI_PICO_DMA_SLOT_I2C0_RX RPI_PICO_DMA_DREQ_TO_SLOT(0x31) +#define RPI_PICO_DMA_SLOT_I2C1_TX RPI_PICO_DMA_DREQ_TO_SLOT(0x32) +#define RPI_PICO_DMA_SLOT_I2C1_RX RPI_PICO_DMA_DREQ_TO_SLOT(0x33) +#define RPI_PICO_DMA_SLOT_ADC RPI_PICO_DMA_DREQ_TO_SLOT(0x34) +#define RPI_PICO_DMA_SLOT_XIP_STREAM RPI_PICO_DMA_DREQ_TO_SLOT(0x35) +#define RPI_PICO_DMA_SLOT_XIP_SSITX RPI_PICO_DMA_DREQ_TO_SLOT(0x36) +#define RPI_PICO_DMA_SLOT_XIP_SSIRX RPI_PICO_DMA_DREQ_TO_SLOT(0x37) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RPI_PICO_DMA_RP2040_H_ */ diff --git a/include/zephyr/dt-bindings/dma/rpi-pico-dma-rp2350.h b/include/zephyr/dt-bindings/dma/rpi-pico-dma-rp2350.h new file mode 100644 index 00000000000000..3a507328cf231e --- /dev/null +++ b/include/zephyr/dt-bindings/dma/rpi-pico-dma-rp2350.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2024 Manuel Aebischer + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RPI_PICO_DMA_RP2350_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_RPI_PICO_DMA_RP2350_H_ + +#include "rpi-pico-dma-common.h" + +#define RPI_PICO_DMA_SLOT_PIO2_TX0 RPI_PICO_DMA_DREQ_TO_SLOT(0x10) +#define RPI_PICO_DMA_SLOT_PIO2_TX1 RPI_PICO_DMA_DREQ_TO_SLOT(0x11) +#define RPI_PICO_DMA_SLOT_PIO2_TX2 RPI_PICO_DMA_DREQ_TO_SLOT(0x12) +#define RPI_PICO_DMA_SLOT_PIO2_TX3 RPI_PICO_DMA_DREQ_TO_SLOT(0x13) +#define RPI_PICO_DMA_SLOT_PIO2_RX0 RPI_PICO_DMA_DREQ_TO_SLOT(0x14) +#define RPI_PICO_DMA_SLOT_PIO2_RX1 RPI_PICO_DMA_DREQ_TO_SLOT(0x15) +#define RPI_PICO_DMA_SLOT_PIO2_RX2 RPI_PICO_DMA_DREQ_TO_SLOT(0x16) +#define RPI_PICO_DMA_SLOT_PIO2_RX3 RPI_PICO_DMA_DREQ_TO_SLOT(0x17) +#define RPI_PICO_DMA_SLOT_SPI0_TX RPI_PICO_DMA_DREQ_TO_SLOT(0x18) +#define RPI_PICO_DMA_SLOT_SPI0_RX RPI_PICO_DMA_DREQ_TO_SLOT(0x19) +#define RPI_PICO_DMA_SLOT_SPI1_TX RPI_PICO_DMA_DREQ_TO_SLOT(0x1A) +#define RPI_PICO_DMA_SLOT_SPI1_RX RPI_PICO_DMA_DREQ_TO_SLOT(0x1B) +#define RPI_PICO_DMA_SLOT_UART0_TX RPI_PICO_DMA_DREQ_TO_SLOT(0x1C) +#define RPI_PICO_DMA_SLOT_UART0_RX RPI_PICO_DMA_DREQ_TO_SLOT(0x1D) +#define RPI_PICO_DMA_SLOT_UART1_TX RPI_PICO_DMA_DREQ_TO_SLOT(0x1E) +#define RPI_PICO_DMA_SLOT_UART1_RX RPI_PICO_DMA_DREQ_TO_SLOT(0x1F) +#define RPI_PICO_DMA_SLOT_PWM_WRAP0 RPI_PICO_DMA_DREQ_TO_SLOT(0x20) +#define RPI_PICO_DMA_SLOT_PWM_WRAP1 RPI_PICO_DMA_DREQ_TO_SLOT(0x21) +#define RPI_PICO_DMA_SLOT_PWM_WRAP2 RPI_PICO_DMA_DREQ_TO_SLOT(0x22) +#define RPI_PICO_DMA_SLOT_PWM_WRAP3 RPI_PICO_DMA_DREQ_TO_SLOT(0x23) +#define RPI_PICO_DMA_SLOT_PWM_WRAP4 RPI_PICO_DMA_DREQ_TO_SLOT(0x24) +#define RPI_PICO_DMA_SLOT_PWM_WRAP5 RPI_PICO_DMA_DREQ_TO_SLOT(0x25) +#define RPI_PICO_DMA_SLOT_PWM_WRAP6 RPI_PICO_DMA_DREQ_TO_SLOT(0x26) +#define RPI_PICO_DMA_SLOT_PWM_WRAP7 RPI_PICO_DMA_DREQ_TO_SLOT(0x27) +#define RPI_PICO_DMA_SLOT_PWM_WRAP8 RPI_PICO_DMA_DREQ_TO_SLOT(0x28) +#define RPI_PICO_DMA_SLOT_PWM_WRAP9 RPI_PICO_DMA_DREQ_TO_SLOT(0x29) +#define RPI_PICO_DMA_SLOT_PWM_WRAP10 RPI_PICO_DMA_DREQ_TO_SLOT(0x2A) +#define RPI_PICO_DMA_SLOT_PWM_WRAP11 RPI_PICO_DMA_DREQ_TO_SLOT(0x2B) +#define RPI_PICO_DMA_SLOT_I2C0_TX RPI_PICO_DMA_DREQ_TO_SLOT(0x2C) +#define RPI_PICO_DMA_SLOT_I2C0_RX RPI_PICO_DMA_DREQ_TO_SLOT(0x2D) +#define RPI_PICO_DMA_SLOT_I2C1_TX RPI_PICO_DMA_DREQ_TO_SLOT(0x2E) +#define RPI_PICO_DMA_SLOT_I2C1_RX RPI_PICO_DMA_DREQ_TO_SLOT(0x2F) +#define RPI_PICO_DMA_SLOT_ADC RPI_PICO_DMA_DREQ_TO_SLOT(0x30) +#define RPI_PICO_DMA_SLOT_XIP_STREAM RPI_PICO_DMA_DREQ_TO_SLOT(0x31) +#define RPI_PICO_DMA_SLOT_XIP_QMITX RPI_PICO_DMA_DREQ_TO_SLOT(0x32) +#define RPI_PICO_DMA_SLOT_XIP_QMIRX RPI_PICO_DMA_DREQ_TO_SLOT(0x33) +#define RPI_PICO_DMA_SLOT_HSTX RPI_PICO_DMA_DREQ_TO_SLOT(0x34) +#define RPI_PICO_DMA_SLOT_CORESIGHT RPI_PICO_DMA_DREQ_TO_SLOT(0x35) +#define RPI_PICO_DMA_SLOT_SHA256 RPI_PICO_DMA_DREQ_TO_SLOT(0x36) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RPI_PICO_DMA_RP2350_H_ */ diff --git a/include/zephyr/dt-bindings/dma/rpi_pico_dma.h b/include/zephyr/dt-bindings/dma/rpi_pico_dma.h deleted file mode 100644 index f181a31beba90b..00000000000000 --- a/include/zephyr/dt-bindings/dma/rpi_pico_dma.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2023 TOKITA Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RPI_PICO_DMA_H_ -#define ZEPHYR_INCLUDE_DT_BINDINGS_RPI_PICO_DMA_H_ - -/* - * Use lower 6-bit of inverted DREQ value for `slot` cell. - * Need to be able to work for memory-to-memory transfer - * with zero, which is the default value. - */ -#define RPI_PICO_DMA_SLOT_TO_DREQ(s) (~(s)&0x3F) -#define RPI_PICO_DMA_DREQ_TO_SLOT RPI_PICO_DMA_SLOT_TO_DREQ - -#define RPI_PICO_DMA_SLOT_PIO0_TX0 RPI_PICO_DMA_DREQ_TO_SLOT(0x00) -#define RPI_PICO_DMA_SLOT_PIO0_TX1 RPI_PICO_DMA_DREQ_TO_SLOT(0x01) -#define RPI_PICO_DMA_SLOT_PIO0_TX2 RPI_PICO_DMA_DREQ_TO_SLOT(0x02) -#define RPI_PICO_DMA_SLOT_PIO0_TX3 RPI_PICO_DMA_DREQ_TO_SLOT(0x03) -#define RPI_PICO_DMA_SLOT_PIO0_RX0 RPI_PICO_DMA_DREQ_TO_SLOT(0x04) -#define RPI_PICO_DMA_SLOT_PIO0_RX1 RPI_PICO_DMA_DREQ_TO_SLOT(0x05) -#define RPI_PICO_DMA_SLOT_PIO0_RX2 RPI_PICO_DMA_DREQ_TO_SLOT(0x06) -#define RPI_PICO_DMA_SLOT_PIO0_RX3 RPI_PICO_DMA_DREQ_TO_SLOT(0x07) -#define RPI_PICO_DMA_SLOT_PIO1_TX0 RPI_PICO_DMA_DREQ_TO_SLOT(0x08) -#define RPI_PICO_DMA_SLOT_PIO1_TX1 RPI_PICO_DMA_DREQ_TO_SLOT(0x09) -#define RPI_PICO_DMA_SLOT_PIO1_TX2 RPI_PICO_DMA_DREQ_TO_SLOT(0x0A) -#define RPI_PICO_DMA_SLOT_PIO1_TX3 RPI_PICO_DMA_DREQ_TO_SLOT(0x0B) -#define RPI_PICO_DMA_SLOT_PIO1_RX0 RPI_PICO_DMA_DREQ_TO_SLOT(0x0C) -#define RPI_PICO_DMA_SLOT_PIO1_RX1 RPI_PICO_DMA_DREQ_TO_SLOT(0x0D) -#define RPI_PICO_DMA_SLOT_PIO1_RX2 RPI_PICO_DMA_DREQ_TO_SLOT(0x0E) -#define RPI_PICO_DMA_SLOT_PIO1_RX3 RPI_PICO_DMA_DREQ_TO_SLOT(0x0F) -#define RPI_PICO_DMA_SLOT_SPI0_TX RPI_PICO_DMA_DREQ_TO_SLOT(0x10) -#define RPI_PICO_DMA_SLOT_SPI0_RX RPI_PICO_DMA_DREQ_TO_SLOT(0x11) -#define RPI_PICO_DMA_SLOT_SPI1_TX RPI_PICO_DMA_DREQ_TO_SLOT(0x12) -#define RPI_PICO_DMA_SLOT_SPI1_RX RPI_PICO_DMA_DREQ_TO_SLOT(0x13) -#define RPI_PICO_DMA_SLOT_UART0_TX RPI_PICO_DMA_DREQ_TO_SLOT(0x14) -#define RPI_PICO_DMA_SLOT_UART0_RX RPI_PICO_DMA_DREQ_TO_SLOT(0x15) -#define RPI_PICO_DMA_SLOT_UART1_TX RPI_PICO_DMA_DREQ_TO_SLOT(0x16) -#define RPI_PICO_DMA_SLOT_UART1_RX RPI_PICO_DMA_DREQ_TO_SLOT(0x17) -#define RPI_PICO_DMA_SLOT_PWM_WRAP0 RPI_PICO_DMA_DREQ_TO_SLOT(0x18) -#define RPI_PICO_DMA_SLOT_PWM_WRAP1 RPI_PICO_DMA_DREQ_TO_SLOT(0x19) -#define RPI_PICO_DMA_SLOT_PWM_WRAP2 RPI_PICO_DMA_DREQ_TO_SLOT(0x1A) -#define RPI_PICO_DMA_SLOT_PWM_WRAP3 RPI_PICO_DMA_DREQ_TO_SLOT(0x1B) -#define RPI_PICO_DMA_SLOT_PWM_WRAP4 RPI_PICO_DMA_DREQ_TO_SLOT(0x1C) -#define RPI_PICO_DMA_SLOT_PWM_WRAP5 RPI_PICO_DMA_DREQ_TO_SLOT(0x1D) -#define RPI_PICO_DMA_SLOT_PWM_WRAP6 RPI_PICO_DMA_DREQ_TO_SLOT(0x1E) -#define RPI_PICO_DMA_SLOT_PWM_WRAP7 RPI_PICO_DMA_DREQ_TO_SLOT(0x1F) -#define RPI_PICO_DMA_SLOT_I2C0_TX RPI_PICO_DMA_DREQ_TO_SLOT(0x30) -#define RPI_PICO_DMA_SLOT_I2C0_RX RPI_PICO_DMA_DREQ_TO_SLOT(0x31) -#define RPI_PICO_DMA_SLOT_I2C1_TX RPI_PICO_DMA_DREQ_TO_SLOT(0x32) -#define RPI_PICO_DMA_SLOT_I2C1_RX RPI_PICO_DMA_DREQ_TO_SLOT(0x33) -#define RPI_PICO_DMA_SLOT_ADC RPI_PICO_DMA_DREQ_TO_SLOT(0x34) -#define RPI_PICO_DMA_SLOT_XIP_STREAM RPI_PICO_DMA_DREQ_TO_SLOT(0x35) -#define RPI_PICO_DMA_SLOT_XIP_SSITX RPI_PICO_DMA_DREQ_TO_SLOT(0x36) -#define RPI_PICO_DMA_SLOT_XIP_SSIRX RPI_PICO_DMA_DREQ_TO_SLOT(0x37) -#define RPI_PICO_DMA_SLOT_DMA_TIMER0 RPI_PICO_DMA_DREQ_TO_SLOT(0x3B) -#define RPI_PICO_DMA_SLOT_DMA_TIMER1 RPI_PICO_DMA_DREQ_TO_SLOT(0x3C) -#define RPI_PICO_DMA_SLOT_DMA_TIMER2 RPI_PICO_DMA_DREQ_TO_SLOT(0x3D) -#define RPI_PICO_DMA_SLOT_DMA_TIMER3 RPI_PICO_DMA_DREQ_TO_SLOT(0x3E) -#define RPI_PICO_DMA_SLOT_FORCE RPI_PICO_DMA_DREQ_TO_SLOT(0x3F) - -#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RPI_PICO_DMA_H_ */ diff --git a/include/zephyr/dt-bindings/pinctrl/rpi-pico-pinctrl-common.h b/include/zephyr/dt-bindings/pinctrl/rpi-pico-pinctrl-common.h new file mode 100644 index 00000000000000..3ac8340988b165 --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/rpi-pico-pinctrl-common.h @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2021, Yonatan Schachter + * Copyright (c) 2024, Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RPI_PICO_PINCTRL_COMMON_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RPI_PICO_PINCTRL_COMMON_H_ + +#define RP2_ALT_FUNC_POS 0 +#define RP2_ALT_FUNC_MASK 0xf + +#define RP2_PIN_NUM_POS 5 +#define RP2_PIN_NUM_MASK 0x1f + +#define RP2_GPIO_OVERRIDE_NORMAL 0 +#define RP2_GPIO_OVERRIDE_INVERT 1 +#define RP2_GPIO_OVERRIDE_LOW 2 +#define RP2_GPIO_OVERRIDE_HIGH 3 + +#define RP2XXX_PINMUX(pin_num, alt_func) (pin_num << RP2_PIN_NUM_POS | alt_func << RP2_ALT_FUNC_POS) + +/* These function are common. SoC-specific functions are defined in their + * respective header file. Refer to table 279 and 642 in the RP2040 and RP2350 + * datasheets for the source of these numbers. + */ +#define RP2_PINCTRL_GPIO_FUNC_SPI 1 +#define RP2_PINCTRL_GPIO_FUNC_UART 2 +#define RP2_PINCTRL_GPIO_FUNC_I2C 3 +#define RP2_PINCTRL_GPIO_FUNC_PWM 4 +#define RP2_PINCTRL_GPIO_FUNC_SIO 5 +#define RP2_PINCTRL_GPIO_FUNC_PIO0 6 +#define RP2_PINCTRL_GPIO_FUNC_PIO1 7 + +/* These pin assignments for each function are similarly common. */ +#define SPI0_RX_P0 RP2XXX_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_CSN_P1 RP2XXX_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_SCK_P2 RP2XXX_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_TX_P3 RP2XXX_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_RX_P4 RP2XXX_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_CSN_P5 RP2XXX_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_SCK_P6 RP2XXX_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_TX_P7 RP2XXX_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_RX_P8 RP2XXX_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_CSN_P9 RP2XXX_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_SCK_P10 RP2XXX_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_TX_P11 RP2XXX_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_RX_P12 RP2XXX_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_CSN_P13 RP2XXX_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_SCK_P14 RP2XXX_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_TX_P15 RP2XXX_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_RX_P16 RP2XXX_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_CSN_P17 RP2XXX_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_SCK_P18 RP2XXX_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_TX_P19 RP2XXX_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_RX_P20 RP2XXX_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_CSN_P21 RP2XXX_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_SCK_P22 RP2XXX_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_TX_P23 RP2XXX_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_RX_P24 RP2XXX_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_CSN_P25 RP2XXX_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_SCK_P26 RP2XXX_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_TX_P27 RP2XXX_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_RX_P28 RP2XXX_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_CSN_P29 RP2XXX_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_SPI) + +#define UART0_TX_P0 RP2XXX_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_RX_P1 RP2XXX_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_CTS_P2 RP2XXX_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_RTS_P3 RP2XXX_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_TX_P4 RP2XXX_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_RX_P5 RP2XXX_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_CTS_P6 RP2XXX_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_RTS_P7 RP2XXX_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_TX_P8 RP2XXX_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_RX_P9 RP2XXX_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_CTS_P10 RP2XXX_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_RTS_P11 RP2XXX_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_TX_P12 RP2XXX_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_RX_P13 RP2XXX_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_CTS_P14 RP2XXX_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_RTS_P15 RP2XXX_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_TX_P16 RP2XXX_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_RX_P17 RP2XXX_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_CTS_P18 RP2XXX_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_RTS_P19 RP2XXX_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_TX_P20 RP2XXX_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_RX_P21 RP2XXX_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_CTS_P22 RP2XXX_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_RTS_P23 RP2XXX_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_TX_P24 RP2XXX_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_RX_P25 RP2XXX_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_CTS_P26 RP2XXX_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_RTS_P27 RP2XXX_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_TX_P28 RP2XXX_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_RX_P29 RP2XXX_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_UART) + +#define I2C0_SDA_P0 RP2XXX_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SCL_P1 RP2XXX_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SDA_P2 RP2XXX_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SCL_P3 RP2XXX_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SDA_P4 RP2XXX_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SCL_P5 RP2XXX_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SDA_P6 RP2XXX_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SCL_P7 RP2XXX_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SDA_P8 RP2XXX_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SCL_P9 RP2XXX_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SDA_P10 RP2XXX_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SCL_P11 RP2XXX_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SDA_P12 RP2XXX_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SCL_P13 RP2XXX_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SDA_P14 RP2XXX_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SCL_P15 RP2XXX_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SDA_P16 RP2XXX_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SCL_P17 RP2XXX_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SDA_P18 RP2XXX_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SCL_P19 RP2XXX_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SDA_P20 RP2XXX_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SCL_P21 RP2XXX_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SDA_P22 RP2XXX_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SCL_P23 RP2XXX_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SDA_P24 RP2XXX_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SCL_P25 RP2XXX_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SDA_P26 RP2XXX_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SCL_P27 RP2XXX_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SDA_P28 RP2XXX_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SCL_P29 RP2XXX_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_I2C) + +#define PWM_0A_P0 RP2XXX_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_0B_P1 RP2XXX_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_1A_P2 RP2XXX_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_1B_P3 RP2XXX_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_2A_P4 RP2XXX_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_2B_P5 RP2XXX_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_3A_P6 RP2XXX_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_3B_P7 RP2XXX_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_4A_P8 RP2XXX_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_4B_P9 RP2XXX_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_5A_P10 RP2XXX_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_5B_P11 RP2XXX_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_6A_P12 RP2XXX_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_6B_P13 RP2XXX_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_7A_P14 RP2XXX_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_7B_P15 RP2XXX_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_0A_P16 RP2XXX_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_0B_P17 RP2XXX_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_1A_P18 RP2XXX_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_1B_P19 RP2XXX_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_2A_P20 RP2XXX_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_2B_P21 RP2XXX_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_3A_P22 RP2XXX_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_3B_P22 RP2XXX_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_4A_P24 RP2XXX_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_4B_P25 RP2XXX_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_5A_P26 RP2XXX_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_5B_P27 RP2XXX_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_6A_P28 RP2XXX_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_6B_P29 RP2XXX_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_PWM) + +#define PIO0_P0 RP2XXX_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P1 RP2XXX_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P2 RP2XXX_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P3 RP2XXX_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P4 RP2XXX_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P5 RP2XXX_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P6 RP2XXX_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P7 RP2XXX_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P8 RP2XXX_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P9 RP2XXX_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P10 RP2XXX_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P11 RP2XXX_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P12 RP2XXX_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P13 RP2XXX_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P14 RP2XXX_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P15 RP2XXX_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P16 RP2XXX_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P17 RP2XXX_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P18 RP2XXX_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P19 RP2XXX_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P20 RP2XXX_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P21 RP2XXX_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P22 RP2XXX_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P23 RP2XXX_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P24 RP2XXX_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P25 RP2XXX_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P26 RP2XXX_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P27 RP2XXX_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P28 RP2XXX_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P29 RP2XXX_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_PIO0) + +#define PIO1_P0 RP2XXX_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P1 RP2XXX_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P2 RP2XXX_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P3 RP2XXX_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P4 RP2XXX_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P5 RP2XXX_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P6 RP2XXX_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P7 RP2XXX_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P8 RP2XXX_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P9 RP2XXX_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P10 RP2XXX_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P11 RP2XXX_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P12 RP2XXX_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P13 RP2XXX_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P14 RP2XXX_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P15 RP2XXX_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P16 RP2XXX_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P17 RP2XXX_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P18 RP2XXX_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P19 RP2XXX_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P20 RP2XXX_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P21 RP2XXX_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P22 RP2XXX_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P23 RP2XXX_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P24 RP2XXX_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P25 RP2XXX_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P26 RP2XXX_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P27 RP2XXX_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P28 RP2XXX_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P29 RP2XXX_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_PIO1) + +#define GPIN0_P20 RP2XXX_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPIN1_P22 RP2XXX_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPOUT0_P21 RP2XXX_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPOUT1_P23 RP2XXX_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPOUT2_P24 RP2XXX_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPOUT3_P25 RP2XXX_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_GPCK) + +#define USB_VBUS_DET_P1 RP2XXX_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_USB) +#define USB_VBUS_DET_P4 RP2XXX_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_USB) +#define USB_VBUS_DET_P7 RP2XXX_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_USB) +#define USB_VBUS_DET_P10 RP2XXX_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_USB) +#define USB_VBUS_DET_P13 RP2XXX_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_USB) +#define USB_VBUS_DET_P16 RP2XXX_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_USB) +#define USB_VBUS_DET_P19 RP2XXX_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_USB) +#define USB_VBUS_DET_P22 RP2XXX_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_USB) +#define USB_VBUS_DET_P25 RP2XXX_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_USB) +#define USB_VBUS_DET_P28 RP2XXX_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_USB) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RPI_PICO_PINCTRL_COMMON_H_ */ diff --git a/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h index 64c3832d60e955..38d6e0420b422a 100644 --- a/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h +++ b/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h @@ -4,242 +4,19 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef __RP2040_PINCTRL_H__ -#define __RP2040_PINCTRL_H__ +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RPI_PICO_RP2040_PINCTRL_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RPI_PICO_RP2040_PINCTRL_H_ -#define RP2_PINCTRL_GPIO_FUNC_XIP 0 -#define RP2_PINCTRL_GPIO_FUNC_SPI 1 -#define RP2_PINCTRL_GPIO_FUNC_UART 2 -#define RP2_PINCTRL_GPIO_FUNC_I2C 3 -#define RP2_PINCTRL_GPIO_FUNC_PWM 4 -#define RP2_PINCTRL_GPIO_FUNC_SIO 5 -#define RP2_PINCTRL_GPIO_FUNC_PIO0 6 -#define RP2_PINCTRL_GPIO_FUNC_PIO1 7 +#define RP2_PINCTRL_GPIO_FUNC_XIP 0 #define RP2_PINCTRL_GPIO_FUNC_GPCK 8 -#define RP2_PINCTRL_GPIO_FUNC_USB 9 +#define RP2_PINCTRL_GPIO_FUNC_USB 9 #define RP2_PINCTRL_GPIO_FUNC_NULL 0xf -#define RP2_ALT_FUNC_POS 0 -#define RP2_ALT_FUNC_MASK 0xf +#include "rpi-pico-pinctrl-common.h" -#define RP2_PIN_NUM_POS 4 -#define RP2_PIN_NUM_MASK 0x1f +#define ADC_CH0_P26 RP2XXX_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_NULL) +#define ADC_CH1_P27 RP2XXX_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_NULL) +#define ADC_CH2_P28 RP2XXX_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_NULL) +#define ADC_CH3_P29 RP2XXX_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_NULL) -#define RP2_GPIO_OVERRIDE_NORMAL 0 -#define RP2_GPIO_OVERRIDE_INVERT 1 -#define RP2_GPIO_OVERRIDE_LOW 2 -#define RP2_GPIO_OVERRIDE_HIGH 3 - -#define RP2040_PINMUX(pin_num, alt_func) (pin_num << RP2_PIN_NUM_POS | \ - alt_func << RP2_ALT_FUNC_POS) - -#define UART0_TX_P0 RP2040_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART0_RX_P1 RP2040_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART0_CTS_P2 RP2040_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART0_RTS_P3 RP2040_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_TX_P4 RP2040_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_RX_P5 RP2040_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_CTS_P6 RP2040_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_RTS_P7 RP2040_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_TX_P8 RP2040_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_RX_P9 RP2040_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_CTS_P10 RP2040_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_RTS_P11 RP2040_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART0_TX_P12 RP2040_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART0_RX_P13 RP2040_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART0_CTS_P14 RP2040_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART0_RTS_P15 RP2040_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART0_TX_P16 RP2040_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART0_RX_P17 RP2040_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART0_CTS_P18 RP2040_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART0_RTS_P19 RP2040_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_TX_P20 RP2040_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_RX_P21 RP2040_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_CTS_P22 RP2040_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_RTS_P23 RP2040_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_TX_P24 RP2040_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_RX_P25 RP2040_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_CTS_P26 RP2040_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_RTS_P27 RP2040_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART0_TX_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART0_RX_P29 RP2040_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_UART) - -#define I2C0_SDA_P0 RP2040_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C0_SCL_P1 RP2040_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C1_SDA_P2 RP2040_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C1_SCL_P3 RP2040_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C0_SDA_P4 RP2040_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C0_SCL_P5 RP2040_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C1_SDA_P6 RP2040_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C1_SCL_P7 RP2040_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C0_SDA_P8 RP2040_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C0_SCL_P9 RP2040_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C1_SDA_P10 RP2040_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C1_SCL_P11 RP2040_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C0_SDA_P12 RP2040_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C0_SCL_P13 RP2040_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C1_SDA_P14 RP2040_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C1_SCL_P15 RP2040_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C0_SDA_P16 RP2040_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C0_SCL_P17 RP2040_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C1_SDA_P18 RP2040_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C1_SCL_P19 RP2040_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C0_SDA_P20 RP2040_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C0_SCL_P21 RP2040_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C1_SDA_P22 RP2040_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C1_SCL_P23 RP2040_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C0_SDA_P24 RP2040_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C0_SCL_P25 RP2040_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C1_SDA_P26 RP2040_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C1_SCL_P27 RP2040_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C0_SDA_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C0_SCL_P29 RP2040_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_I2C) - -#define PWM_0A_P0 RP2040_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_0B_P1 RP2040_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_1A_P2 RP2040_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_1B_P3 RP2040_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_2A_P4 RP2040_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_2B_P5 RP2040_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_3A_P6 RP2040_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_3B_P7 RP2040_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_4A_P8 RP2040_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_4B_P9 RP2040_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_5A_P10 RP2040_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_5B_P11 RP2040_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_6A_P12 RP2040_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_6B_P13 RP2040_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_7A_P14 RP2040_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_7B_P15 RP2040_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_0A_P16 RP2040_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_0B_P17 RP2040_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_1A_P18 RP2040_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_1B_P19 RP2040_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_2A_P20 RP2040_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_2B_P21 RP2040_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_3A_P22 RP2040_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_3B_P22 RP2040_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_4A_P24 RP2040_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_4B_P25 RP2040_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_5A_P26 RP2040_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_5B_P27 RP2040_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_6A_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_6B_P29 RP2040_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_PWM) - -#define SPI0_RX_P0 RP2040_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI0_CSN_P1 RP2040_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI0_SCK_P2 RP2040_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI0_TX_P3 RP2040_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI0_RX_P4 RP2040_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI0_CSN_P5 RP2040_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI0_SCK_P6 RP2040_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI0_TX_P7 RP2040_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI1_RX_P8 RP2040_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI1_CSN_P9 RP2040_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI1_SCK_P10 RP2040_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI1_TX_P11 RP2040_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI1_RX_P12 RP2040_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI1_CSN_P13 RP2040_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI1_SCK_P14 RP2040_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI1_TX_P15 RP2040_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI0_RX_P16 RP2040_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI0_CSN_P17 RP2040_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI0_SCK_P18 RP2040_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI0_TX_P19 RP2040_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI0_RX_P20 RP2040_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI0_CSN_P21 RP2040_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI0_SCK_P22 RP2040_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI0_TX_P23 RP2040_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI1_RX_P24 RP2040_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI1_CSN_P25 RP2040_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI1_SCK_P26 RP2040_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI1_TX_P27 RP2040_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI1_RX_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI1_CSN_P29 RP2040_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_SPI) - -#define ADC_CH0_P26 RP2040_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_NULL) -#define ADC_CH1_P27 RP2040_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_NULL) -#define ADC_CH2_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_NULL) -#define ADC_CH3_P29 RP2040_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_NULL) - -#define PIO0_P0 RP2040_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P1 RP2040_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P2 RP2040_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P3 RP2040_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P4 RP2040_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P5 RP2040_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P6 RP2040_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P7 RP2040_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P8 RP2040_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P9 RP2040_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P10 RP2040_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P11 RP2040_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P12 RP2040_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P13 RP2040_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P14 RP2040_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P15 RP2040_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P16 RP2040_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P17 RP2040_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P18 RP2040_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P19 RP2040_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P20 RP2040_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P21 RP2040_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P22 RP2040_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P23 RP2040_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P24 RP2040_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P25 RP2040_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P26 RP2040_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P27 RP2040_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P29 RP2040_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_PIO0) - -#define PIO1_P0 RP2040_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P1 RP2040_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P2 RP2040_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P3 RP2040_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P4 RP2040_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P5 RP2040_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P6 RP2040_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P7 RP2040_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P8 RP2040_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P9 RP2040_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P10 RP2040_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P11 RP2040_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P12 RP2040_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P13 RP2040_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P14 RP2040_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P15 RP2040_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P16 RP2040_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P17 RP2040_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P18 RP2040_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P19 RP2040_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P20 RP2040_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P21 RP2040_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P22 RP2040_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P23 RP2040_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P24 RP2040_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P25 RP2040_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P26 RP2040_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P27 RP2040_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P29 RP2040_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_PIO1) - -#define GPIN0_P20 RP2040_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_GPCK) -#define GPIN1_P22 RP2040_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_GPCK) -#define GPOUT0_P21 RP2040_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_GPCK) -#define GPOUT1_P23 RP2040_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_GPCK) -#define GPOUT2_P24 RP2040_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_GPCK) -#define GPOUT3_P25 RP2040_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_GPCK) - -#define USB_VBUS_DET_P1 RP2040_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_USB) -#define USB_VBUS_DET_P4 RP2040_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_USB) -#define USB_VBUS_DET_P7 RP2040_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_USB) -#define USB_VBUS_DET_P10 RP2040_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_USB) -#define USB_VBUS_DET_P13 RP2040_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_USB) -#define USB_VBUS_DET_P16 RP2040_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_USB) -#define USB_VBUS_DET_P19 RP2040_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_USB) -#define USB_VBUS_DET_P22 RP2040_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_USB) -#define USB_VBUS_DET_P25 RP2040_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_USB) -#define USB_VBUS_DET_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_USB) - -#endif /* __RP2040_PINCTRL_H__ */ +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RPI_PICO_RP2040_PINCTRL_H_ */ diff --git a/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2350-pinctrl-common.h b/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2350-pinctrl-common.h new file mode 100644 index 00000000000000..9899d55519421f --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2350-pinctrl-common.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2024, Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RPI_PICO_RP2350_PINCTRL_COMMON_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RPI_PICO_RP2350_PINCTRL_COMMON_H_ + +#define RP2_PINCTRL_GPIO_FUNC_HSTX 0 + +#define RP2_PINCTRL_GPIO_FUNC_PIO2 8 +#define RP2_PINCTRL_GPIO_FUNC_GPCK 9 +#define RP2_PINCTRL_GPIO_FUNC_USB 10 +#define RP2_PINCTRL_GPIO_FUNC_UART_AUX 11 +#define RP2_PINCTRL_GPIO_FUNC_NULL 0x1f + +#include "rpi-pico-pinctrl-common.h" + +#define PIO2_P0 RP2XXX_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P1 RP2XXX_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P2 RP2XXX_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P3 RP2XXX_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P4 RP2XXX_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P5 RP2XXX_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P6 RP2XXX_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P7 RP2XXX_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P8 RP2XXX_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P9 RP2XXX_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P10 RP2XXX_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P11 RP2XXX_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P12 RP2XXX_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P13 RP2XXX_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P14 RP2XXX_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P15 RP2XXX_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P16 RP2XXX_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P17 RP2XXX_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P18 RP2XXX_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P19 RP2XXX_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P20 RP2XXX_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P21 RP2XXX_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P22 RP2XXX_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P23 RP2XXX_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P24 RP2XXX_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P25 RP2XXX_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P26 RP2XXX_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P27 RP2XXX_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P28 RP2XXX_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P29 RP2XXX_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_PIO2) + +#define GPIN0_P12 RP2XXX_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPIN1_P14 RP2XXX_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPOUT0_P13 RP2XXX_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPOUT1_P15 RP2XXX_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_GPCK) + +#define UART0_TX_P2 RP2XXX_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART0_RX_P3 RP2XXX_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART1_TX_P6 RP2XXX_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART1_RX_P7 RP2XXX_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART1_TX_P10 RP2XXX_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART1_RX_P11 RP2XXX_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART0_TX_P14 RP2XXX_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART0_RX_P15 RP2XXX_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART0_TX_P18 RP2XXX_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART0_RX_P19 RP2XXX_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART1_TX_P22 RP2XXX_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART1_RX_P23 RP2XXX_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART1_TX_P26 RP2XXX_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART1_RX_P27 RP2XXX_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_UART_ALT) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RPI_PICO_RP2350_PINCTRL_COMMON_H_ */ diff --git a/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2350a-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2350a-pinctrl.h new file mode 100644 index 00000000000000..0c4f910a51b81b --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2350a-pinctrl.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2024, Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RPI_PICO_RP2350A_PINCTRL_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RPI_PICO_RP2350A_PINCTRL_H_ + +#include "rpi-pico-rp2350-pinctrl-common.h" + +/* ADC channel allocations differ between the RP2350A and RP2350B. + * Refer to Table 1115 in the datasheet. + */ +#define ADC_CH0_P26 RP2XXX_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_NULL) +#define ADC_CH1_P27 RP2XXX_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_NULL) +#define ADC_CH2_P28 RP2XXX_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_NULL) +#define ADC_CH3_P29 RP2XXX_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_NULL) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RPI_PICO_RP2350A_PINCTRL_H_ */ diff --git a/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2350b-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2350b-pinctrl.h new file mode 100644 index 00000000000000..7f53cf559fd62e --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2350b-pinctrl.h @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2024, Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RPI_PICO_RP2350B_PINCTRL_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RPI_PICO_RP2350B_PINCTRL_H_ + +#include "rpi-pico-rp2350-pinctrl-common.h" + +/* RP2350B is in a QFN-80 package, and extends the set of available pins + * accordingly. + */ +#define SPI1_SCK_P30 RP2XXX_PINMUX(30, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_TX_P31 RP2XXX_PINMUX(31, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_RX_P32 RP2XXX_PINMUX(32, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_CSN_P33 RP2XXX_PINMUX(33, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_SCK_P34 RP2XXX_PINMUX(34, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_TX_P35 RP2XXX_PINMUX(35, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_RX_P36 RP2XXX_PINMUX(36, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_CSN_P37 RP2XXX_PINMUX(37, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_SCK_P38 RP2XXX_PINMUX(38, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_TX_P39 RP2XXX_PINMUX(39, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_RX_P40 RP2XXX_PINMUX(40, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_CSN_P41 RP2XXX_PINMUX(41, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_SCK_P42 RP2XXX_PINMUX(42, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_TX_P43 RP2XXX_PINMUX(43, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_RX_P44 RP2XXX_PINMUX(44, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_CSN_P45 RP2XXX_PINMUX(45, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_SCK_P46 RP2XXX_PINMUX(46, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_TX_P47 RP2XXX_PINMUX(47, RP2_PINCTRL_GPIO_FUNC_SPI) + +#define UART1_TX_P30 RP2XXX_PINMUX(30, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_RX_P31 RP2XXX_PINMUX(31, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_TX_P32 RP2XXX_PINMUX(32, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_RX_P33 RP2XXX_PINMUX(33, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_TX_P34 RP2XXX_PINMUX(34, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_RX_P35 RP2XXX_PINMUX(35, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_TX_P36 RP2XXX_PINMUX(36, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_RX_P37 RP2XXX_PINMUX(37, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_TX_P38 RP2XXX_PINMUX(38, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_RX_P39 RP2XXX_PINMUX(39, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_TX_P40 RP2XXX_PINMUX(40, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_RX_P41 RP2XXX_PINMUX(41, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_TX_P42 RP2XXX_PINMUX(42, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_RX_P43 RP2XXX_PINMUX(43, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_TX_P44 RP2XXX_PINMUX(44, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_RX_P45 RP2XXX_PINMUX(45, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_TX_P46 RP2XXX_PINMUX(46, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_RX_P47 RP2XXX_PINMUX(47, RP2_PINCTRL_GPIO_FUNC_UART) + +#define I2C1_SDA_P30 RP2XXX_PINMUX(30, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SCL_P31 RP2XXX_PINMUX(31, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SDA_P32 RP2XXX_PINMUX(32, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SCL_P33 RP2XXX_PINMUX(33, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SDA_P34 RP2XXX_PINMUX(34, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SCL_P35 RP2XXX_PINMUX(35, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SDA_P36 RP2XXX_PINMUX(36, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SCL_P37 RP2XXX_PINMUX(37, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SDA_P38 RP2XXX_PINMUX(38, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SCL_P39 RP2XXX_PINMUX(39, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SDA_P40 RP2XXX_PINMUX(40, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SCL_P41 RP2XXX_PINMUX(41, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SDA_P42 RP2XXX_PINMUX(42, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SCL_P43 RP2XXX_PINMUX(43, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SDA_P44 RP2XXX_PINMUX(44, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SCL_P45 RP2XXX_PINMUX(45, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SDA_P46 RP2XXX_PINMUX(46, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SCL_P47 RP2XXX_PINMUX(47, RP2_PINCTRL_GPIO_FUNC_I2C) + +#define PWM_7A_P30 RP2XXX_PINMUX(30, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_7B_P31 RP2XXX_PINMUX(31, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_8A_P32 RP2XXX_PINMUX(32, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_8B_P33 RP2XXX_PINMUX(33, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_9A_P34 RP2XXX_PINMUX(34, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_9B_P35 RP2XXX_PINMUX(35, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_10A_P36 RP2XXX_PINMUX(36, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_10B_P37 RP2XXX_PINMUX(37, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_11A_P38 RP2XXX_PINMUX(38, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_11B_P39 RP2XXX_PINMUX(39, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_12A_P40 RP2XXX_PINMUX(40, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_12B_P41 RP2XXX_PINMUX(41, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_13A_P42 RP2XXX_PINMUX(42, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_13B_P43 RP2XXX_PINMUX(43, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_14A_P44 RP2XXX_PINMUX(44, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_14B_P45 RP2XXX_PINMUX(45, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_15A_P46 RP2XXX_PINMUX(46, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_15B_P47 RP2XXX_PINMUX(47, RP2_PINCTRL_GPIO_FUNC_PWM) + +#define PIO0_P30 RP2XXX_PINMUX(30, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P31 RP2XXX_PINMUX(31, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P32 RP2XXX_PINMUX(32, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P33 RP2XXX_PINMUX(33, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P34 RP2XXX_PINMUX(34, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P35 RP2XXX_PINMUX(35, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P36 RP2XXX_PINMUX(36, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P37 RP2XXX_PINMUX(37, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P38 RP2XXX_PINMUX(38, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P39 RP2XXX_PINMUX(39, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P40 RP2XXX_PINMUX(40, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P41 RP2XXX_PINMUX(41, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P42 RP2XXX_PINMUX(42, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P43 RP2XXX_PINMUX(43, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P44 RP2XXX_PINMUX(44, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P45 RP2XXX_PINMUX(45, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P46 RP2XXX_PINMUX(46, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P47 RP2XXX_PINMUX(47, RP2_PINCTRL_GPIO_FUNC_PIO0) + +#define PIO1_P30 RP2XXX_PINMUX(30, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P31 RP2XXX_PINMUX(31, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P32 RP2XXX_PINMUX(32, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P33 RP2XXX_PINMUX(33, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P34 RP2XXX_PINMUX(34, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P35 RP2XXX_PINMUX(35, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P36 RP2XXX_PINMUX(36, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P37 RP2XXX_PINMUX(37, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P38 RP2XXX_PINMUX(38, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P39 RP2XXX_PINMUX(39, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P40 RP2XXX_PINMUX(40, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P41 RP2XXX_PINMUX(41, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P42 RP2XXX_PINMUX(42, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P43 RP2XXX_PINMUX(43, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P44 RP2XXX_PINMUX(44, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P45 RP2XXX_PINMUX(45, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P46 RP2XXX_PINMUX(46, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P47 RP2XXX_PINMUX(47, RP2_PINCTRL_GPIO_FUNC_PIO1) + +#define PIO2_P30 RP2XXX_PINMUX(30, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P31 RP2XXX_PINMUX(31, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P32 RP2XXX_PINMUX(32, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P33 RP2XXX_PINMUX(33, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P34 RP2XXX_PINMUX(34, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P35 RP2XXX_PINMUX(35, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P36 RP2XXX_PINMUX(36, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P37 RP2XXX_PINMUX(37, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P38 RP2XXX_PINMUX(38, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P39 RP2XXX_PINMUX(39, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P40 RP2XXX_PINMUX(40, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P41 RP2XXX_PINMUX(41, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P42 RP2XXX_PINMUX(42, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P43 RP2XXX_PINMUX(43, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P44 RP2XXX_PINMUX(44, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P45 RP2XXX_PINMUX(45, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P46 RP2XXX_PINMUX(46, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P47 RP2XXX_PINMUX(47, RP2_PINCTRL_GPIO_FUNC_PIO2) + +#define GPIN0_P12 RP2XXX_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPIN1_P14 RP2XXX_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPIN0_P20 RP2XXX_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPIN1_P22 RP2XXX_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPOUT0_P13 RP2XXX_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPOUT1_P15 RP2XXX_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPOUT0_P21 RP2XXX_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPOUT1_P23 RP2XXX_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPOUT2_P24 RP2XXX_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPOUT3_P25 RP2XXX_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_GPCK) + +#define USB_VBUS_DET_P31 RP2XXX_PINMUX(31, RP2_PINCTRL_GPIO_FUNC_USB) +#define USB_VBUS_DET_P34 RP2XXX_PINMUX(34, RP2_PINCTRL_GPIO_FUNC_USB) +#define USB_VBUS_DET_P37 RP2XXX_PINMUX(37, RP2_PINCTRL_GPIO_FUNC_USB) +#define USB_VBUS_DET_P40 RP2XXX_PINMUX(40, RP2_PINCTRL_GPIO_FUNC_USB) +#define USB_VBUS_DET_P43 RP2XXX_PINMUX(43, RP2_PINCTRL_GPIO_FUNC_USB) +#define USB_VBUS_DET_P46 RP2XXX_PINMUX(46, RP2_PINCTRL_GPIO_FUNC_USB) + +#define UART0_TX_P30 RP2XXX_PINMUX(30, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART0_RX_P31 RP2XXX_PINMUX(31, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART0_TX_P34 RP2XXX_PINMUX(34, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART0_RX_P35 RP2XXX_PINMUX(35, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART1_TX_P38 RP2XXX_PINMUX(38, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART1_RX_P39 RP2XXX_PINMUX(39, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART1_TX_P42 RP2XXX_PINMUX(42, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART1_RX_P43 RP2XXX_PINMUX(43, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART0_TX_P46 RP2XXX_PINMUX(46, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART0_RX_P47 RP2XXX_PINMUX(47, RP2_PINCTRL_GPIO_FUNC_UART_ALT) + +/* ADC channel allocations differ between the RP2350A and RP2350B. + * Refer to Table 1116 in the datasheet. + */ +#define ADC_CH0_P40 RP2XXX_PINMUX(40, RP2_PINCTRL_GPIO_FUNC_NULL) +#define ADC_CH1_P41 RP2XXX_PINMUX(41, RP2_PINCTRL_GPIO_FUNC_NULL) +#define ADC_CH2_P42 RP2XXX_PINMUX(42, RP2_PINCTRL_GPIO_FUNC_NULL) +#define ADC_CH3_P43 RP2XXX_PINMUX(43, RP2_PINCTRL_GPIO_FUNC_NULL) +#define ADC_CH4_P44 RP2XXX_PINMUX(44, RP2_PINCTRL_GPIO_FUNC_NULL) +#define ADC_CH5_P45 RP2XXX_PINMUX(45, RP2_PINCTRL_GPIO_FUNC_NULL) +#define ADC_CH6_P46 RP2XXX_PINMUX(46, RP2_PINCTRL_GPIO_FUNC_NULL) +#define ADC_CH7_P47 RP2XXX_PINMUX(47, RP2_PINCTRL_GPIO_FUNC_NULL) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RPI_PICO_RP2350B_PINCTRL_H_ */ diff --git a/include/zephyr/dt-bindings/reset/rp2040_reset.h b/include/zephyr/dt-bindings/reset/rp2040_reset.h new file mode 100644 index 00000000000000..eeb253c3839434 --- /dev/null +++ b/include/zephyr/dt-bindings/reset/rp2040_reset.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2021 Yonatan Schachter + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_RP2040_RESET_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_RP2040_RESET_H_ + +#define RPI_PICO_RESETS_RESET_ADC 0 +#define RPI_PICO_RESETS_RESET_BUSCTRL 1 +#define RPI_PICO_RESETS_RESET_DMA 2 +#define RPI_PICO_RESETS_RESET_I2C0 3 +#define RPI_PICO_RESETS_RESET_I2C1 4 +#define RPI_PICO_RESETS_RESET_IO_BANK0 5 +#define RPI_PICO_RESETS_RESET_IO_QSPI 6 +#define RPI_PICO_RESETS_RESET_JTAG 7 +#define RPI_PICO_RESETS_RESET_PADS_BANK0 8 +#define RPI_PICO_RESETS_RESET_PADS_QSPI 9 +#define RPI_PICO_RESETS_RESET_PIO0 10 +#define RPI_PICO_RESETS_RESET_PIO1 11 +#define RPI_PICO_RESETS_RESET_PLL_SYS 12 +#define RPI_PICO_RESETS_RESET_PLL_USB 13 +#define RPI_PICO_RESETS_RESET_PWM 14 +#define RPI_PICO_RESETS_RESET_RTC 15 +#define RPI_PICO_RESETS_RESET_SPI0 16 +#define RPI_PICO_RESETS_RESET_SPI1 17 +#define RPI_PICO_RESETS_RESET_SYSCFG 18 +#define RPI_PICO_RESETS_RESET_SYSINFO 19 +#define RPI_PICO_RESETS_RESET_TBMAN 20 +#define RPI_PICO_RESETS_RESET_TIMER 21 +#define RPI_PICO_RESETS_RESET_UART0 22 +#define RPI_PICO_RESETS_RESET_UART1 23 +#define RPI_PICO_RESETS_RESET_USBCTRL 24 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_RP2040_RESET_H_ */ diff --git a/include/zephyr/dt-bindings/reset/rp2350_reset.h b/include/zephyr/dt-bindings/reset/rp2350_reset.h new file mode 100644 index 00000000000000..81fcfa9ff31d14 --- /dev/null +++ b/include/zephyr/dt-bindings/reset/rp2350_reset.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2024 Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_RP2350_RESET_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_RP2350_RESET_H_ + +#define RPI_PICO_RESETS_RESET_ADC 0 +#define RPI_PICO_RESETS_RESET_BUSCTRL 1 +#define RPI_PICO_RESETS_RESET_DMA 2 +#define RPI_PICO_RESETS_RESET_HSTX 3 +#define RPI_PICO_RESETS_RESET_I2C0 4 +#define RPI_PICO_RESETS_RESET_I2C1 5 +#define RPI_PICO_RESETS_RESET_IO_BANK0 6 +#define RPI_PICO_RESETS_RESET_IO_QSPI 7 +#define RPI_PICO_RESETS_RESET_JTAG 8 +#define RPI_PICO_RESETS_RESET_PADS_BANK0 9 +#define RPI_PICO_RESETS_RESET_PADS_QSPI 10 +#define RPI_PICO_RESETS_RESET_PIO0 11 +#define RPI_PICO_RESETS_RESET_PIO1 12 +#define RPI_PICO_RESETS_RESET_PIO2 13 +#define RPI_PICO_RESETS_RESET_PLL_SYS 14 +#define RPI_PICO_RESETS_RESET_PLL_USB 15 +#define RPI_PICO_RESETS_RESET_PWM 16 +#define RPI_PICO_RESETS_RESET_SHA256 17 +#define RPI_PICO_RESETS_RESET_SPI0 18 +#define RPI_PICO_RESETS_RESET_SPI1 19 +#define RPI_PICO_RESETS_RESET_SYSCFG 20 +#define RPI_PICO_RESETS_RESET_SYSINFO 21 +#define RPI_PICO_RESETS_RESET_TBMAN 22 +#define RPI_PICO_RESETS_RESET_TIMER0 23 +#define RPI_PICO_RESETS_RESET_TIMER1 24 +#define RPI_PICO_RESETS_RESET_TRNG 25 +#define RPI_PICO_RESETS_RESET_UART0 26 +#define RPI_PICO_RESETS_RESET_UART1 27 +#define RPI_PICO_RESETS_RESET_USBCTRL 28 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_RP2350_RESET_H_ */ diff --git a/modules/hal_rpi_pico/CMakeLists.txt b/modules/hal_rpi_pico/CMakeLists.txt index c91e6467992530..0898795a86d64f 100644 --- a/modules/hal_rpi_pico/CMakeLists.txt +++ b/modules/hal_rpi_pico/CMakeLists.txt @@ -6,9 +6,9 @@ if(CONFIG_HAS_RPI_PICO) zephyr_library() set(rp2_common_dir ${ZEPHYR_HAL_RPI_PICO_MODULE_DIR}/src/rp2_common) - set(rp2040_dir ${ZEPHYR_HAL_RPI_PICO_MODULE_DIR}/src/rp2040) + set(rp2xxx_dir ${ZEPHYR_HAL_RPI_PICO_MODULE_DIR}/src/${CONFIG_SOC_SERIES}) set(common_dir ${ZEPHYR_HAL_RPI_PICO_MODULE_DIR}/src/common) - set(boot_stage_dir ${rp2040_dir}/boot_stage2) + set(boot_stage_dir ${rp2xxx_dir}/boot_stage2) # The Second Stage Bootloader is only linked to the app that resides # at 0x100. Therefore, only if the app's offset is 0x100, the second @@ -46,7 +46,11 @@ if(CONFIG_HAS_RPI_PICO) zephyr_library_sources(${rp2_bootloader_asm}) endif() - zephyr_compile_definitions(PICO_RP2040) + if(CONFIG_SOC_SERIES_RP2040) + zephyr_compile_definitions(PICO_RP2040) + elseif(CONFIG_SOC_SERIES_RP2350) + zephyr_compile_definitions(PICO_RP2350) + endif() # Pico sources and headers necessary for every build. # These contain definitions and implementation used mostly for @@ -57,8 +61,10 @@ if(CONFIG_HAS_RPI_PICO) ${rp2_common_dir}/hardware_pll/pll.c ${rp2_common_dir}/hardware_xosc/xosc.c ${rp2_common_dir}/hardware_watchdog/watchdog.c + ${rp2_common_dir}/hardware_sync_spin_lock/sync_spin_lock.c + ${rp2_common_dir}/hardware_ticks/ticks.c ${rp2_common_dir}/pico_bootrom/bootrom.c - ${rp2040_dir}/pico_platform/platform.c + ${rp2xxx_dir}/pico_platform/platform.c ) zephyr_include_directories( @@ -81,9 +87,9 @@ if(CONFIG_HAS_RPI_PICO) ${rp2_common_dir}/pico_platform_panic/include ${common_dir}/boot_picoboot_headers/include ${common_dir}/boot_picobin_headers/include - ${rp2040_dir}/hardware_regs/include - ${rp2040_dir}/hardware_structs/include - ${rp2040_dir}/pico_platform/include + ${rp2xxx_dir}/hardware_regs/include + ${rp2xxx_dir}/hardware_structs/include + ${rp2xxx_dir}/pico_platform/include ${CMAKE_CURRENT_LIST_DIR} ) @@ -145,4 +151,10 @@ if(CONFIG_HAS_RPI_PICO) zephyr_include_directories_ifdef(CONFIG_PICOSDK_USE_CLAIM ${common_dir}/hardware_claim/include) + zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_RP2350 + ${rp2_common_dir}/pico_runtime_init/runtime_init.c) + zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_RP2350 + ${rp2_common_dir}/pico_runtime/include + ${rp2_common_dir}/pico_runtime_init/include) + endif() diff --git a/samples/boards/raspberrypi/rpi_pico/uart_pio/boards/rpi_pico2_rp2350a_m33.overlay b/samples/boards/raspberrypi/rpi_pico/uart_pio/boards/rpi_pico2_rp2350a_m33.overlay new file mode 100644 index 00000000000000..8b83efe6ea08f2 --- /dev/null +++ b/samples/boards/raspberrypi/rpi_pico/uart_pio/boards/rpi_pico2_rp2350a_m33.overlay @@ -0,0 +1,8 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Andrew Featherstone + */ + +/* Pico 2 is compatible with the Pico 1, so reuse. */ +#include "rpi_pico.overlay" diff --git a/samples/drivers/adc/adc_dt/boards/rpi_pico2_rp2350a_m33.overlay b/samples/drivers/adc/adc_dt/boards/rpi_pico2_rp2350a_m33.overlay new file mode 100644 index 00000000000000..8b83efe6ea08f2 --- /dev/null +++ b/samples/drivers/adc/adc_dt/boards/rpi_pico2_rp2350a_m33.overlay @@ -0,0 +1,8 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Andrew Featherstone + */ + +/* Pico 2 is compatible with the Pico 1, so reuse. */ +#include "rpi_pico.overlay" diff --git a/samples/drivers/led/pwm/boards/rpi_pico2_rp2350a_m33.conf b/samples/drivers/led/pwm/boards/rpi_pico2_rp2350a_m33.conf new file mode 100644 index 00000000000000..64a21d23f2715f --- /dev/null +++ b/samples/drivers/led/pwm/boards/rpi_pico2_rp2350a_m33.conf @@ -0,0 +1,3 @@ +CONFIG_BLINK_DELAY_SHORT=20 +CONFIG_BLINK_DELAY_LONG=50 +CONFIG_FADE_DELAY=15 diff --git a/samples/drivers/led/pwm/boards/rpi_pico2_rp2350a_m33.overlay b/samples/drivers/led/pwm/boards/rpi_pico2_rp2350a_m33.overlay new file mode 100644 index 00000000000000..8b83efe6ea08f2 --- /dev/null +++ b/samples/drivers/led/pwm/boards/rpi_pico2_rp2350a_m33.overlay @@ -0,0 +1,8 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Andrew Featherstone + */ + +/* Pico 2 is compatible with the Pico 1, so reuse. */ +#include "rpi_pico.overlay" diff --git a/samples/sensor/die_temp_polling/boards/rpi_pico2_rp2350a_m33.overlay b/samples/sensor/die_temp_polling/boards/rpi_pico2_rp2350a_m33.overlay new file mode 100644 index 00000000000000..0c8a120437bb5b --- /dev/null +++ b/samples/sensor/die_temp_polling/boards/rpi_pico2_rp2350a_m33.overlay @@ -0,0 +1,8 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Andrew Featherstone + */ + +/* Pico 2 is compatible with the Pico 1, so reuse. */ +#include "rpi_pico.overlay" diff --git a/scripts/build/uf2families.json b/scripts/build/uf2families.json index 14c8e5d043cb65..10a8e4038c118e 100644 --- a/scripts/build/uf2families.json +++ b/scripts/build/uf2families.json @@ -189,6 +189,11 @@ "short_name": "RP2040", "description": "Raspberry Pi RP2040" }, + { + "id": "0xe48bff57", + "short_name": "RP2350", + "description": "Raspberry Pi RP2350" + }, { "id": "0x00ff6919", "short_name": "STM32L4", diff --git a/soc/raspberrypi/CMakeLists.txt b/soc/raspberrypi/rpi_pico/CMakeLists.txt similarity index 73% rename from soc/raspberrypi/CMakeLists.txt rename to soc/raspberrypi/rpi_pico/CMakeLists.txt index 226f3bd626f611..c5f97039eb75b4 100644 --- a/soc/raspberrypi/CMakeLists.txt +++ b/soc/raspberrypi/rpi_pico/CMakeLists.txt @@ -1,3 +1,4 @@ # SPDX-License-Identifier: Apache-2.0 +add_subdirectory(common) add_subdirectory(${SOC_SERIES}) diff --git a/soc/raspberrypi/Kconfig b/soc/raspberrypi/rpi_pico/Kconfig similarity index 100% rename from soc/raspberrypi/Kconfig rename to soc/raspberrypi/rpi_pico/Kconfig diff --git a/soc/raspberrypi/Kconfig.defconfig b/soc/raspberrypi/rpi_pico/Kconfig.defconfig similarity index 100% rename from soc/raspberrypi/Kconfig.defconfig rename to soc/raspberrypi/rpi_pico/Kconfig.defconfig diff --git a/soc/raspberrypi/Kconfig.soc b/soc/raspberrypi/rpi_pico/Kconfig.soc similarity index 100% rename from soc/raspberrypi/Kconfig.soc rename to soc/raspberrypi/rpi_pico/Kconfig.soc diff --git a/soc/raspberrypi/rpi_pico/common/CMakeLists.txt b/soc/raspberrypi/rpi_pico/common/CMakeLists.txt new file mode 100644 index 00000000000000..d87ecff49c08db --- /dev/null +++ b/soc/raspberrypi/rpi_pico/common/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Andrew Featherstone +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c +) diff --git a/soc/raspberrypi/rp2xxx/pinctrl_soc.h b/soc/raspberrypi/rpi_pico/common/pinctrl_soc.h similarity index 96% rename from soc/raspberrypi/rp2xxx/pinctrl_soc.h rename to soc/raspberrypi/rpi_pico/common/pinctrl_soc.h index 8ee56c005e1b78..43cafe1cff9920 100644 --- a/soc/raspberrypi/rp2xxx/pinctrl_soc.h +++ b/soc/raspberrypi/rpi_pico/common/pinctrl_soc.h @@ -7,7 +7,7 @@ #ifndef ZEPHYR_SOC_ARM_RPI_PICO_RP2_PINCTRL_SOC_H_ #define ZEPHYR_SOC_ARM_RPI_PICO_RP2_PINCTRL_SOC_H_ -#include +#include /** * @brief Type to hold a pin's pinctrl configuration. @@ -16,7 +16,7 @@ struct rpi_pinctrl_soc_pin { /** Pin number 0..29 */ uint32_t pin_num : 5; /** Alternative function (UART, SPI, etc.) */ - uint32_t alt_func : 4; + uint32_t alt_func : 5; /** Maximum current used by a pin, in mA */ uint32_t drive_strength : 4; /** Slew rate, may be either false (slow) or true (fast) */ diff --git a/soc/raspberrypi/rp2xxx/soc.c b/soc/raspberrypi/rpi_pico/common/soc.c similarity index 71% rename from soc/raspberrypi/rp2xxx/soc.c rename to soc/raspberrypi/rpi_pico/common/soc.c index 012f5431283b87..37e98105fa14cd 100644 --- a/soc/raspberrypi/rp2xxx/soc.c +++ b/soc/raspberrypi/rpi_pico/common/soc.c @@ -1,28 +1,23 @@ /* * Copyright (c) 2021 Nordic Semiconductor ASA * Copyright (c) 2021 Yonatan Schachter + * Copyright (c) 2024 Andrew Featherstone * * SPDX-License-Identifier: Apache-2.0 */ /** * @file - * @brief System/hardware module for Raspberry Pi RP2040 family processor + * @brief System/hardware module for Raspberry Pi RP2xxx family of processors * * This module provides routines to initialize and support board-level hardware - * for the Raspberry Pi RP2040 family processor. + * for the Raspberry Pi RP2xxx family of processors (RP2040, RP235x). */ #include -#include -#include -#include #include - -#include -#include -#include +#include LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); diff --git a/soc/raspberrypi/rp2xxx/soc.h b/soc/raspberrypi/rpi_pico/common/soc.h similarity index 71% rename from soc/raspberrypi/rp2xxx/soc.h rename to soc/raspberrypi/rpi_pico/common/soc.h index 0eef4cf92a2477..c3d669ec99beb0 100644 --- a/soc/raspberrypi/rp2xxx/soc.h +++ b/soc/raspberrypi/rpi_pico/common/soc.h @@ -9,9 +9,9 @@ * @file SoC configuration macros for the Raspberry Pi RP2040 family processors */ -#ifndef _RPI_PICO_RP2040_SOC_H_ -#define _RPI_PICO_RP2040_SOC_H_ +#ifndef _RPI_PICO_COMMON_SOC_H_ +#define _RPI_PICO_COMMON_SOC_H_ #include -#endif /* _RPI_PICO_RP2040_SOC_H_ */ +#endif /* _RPI_PICO_COMMON_SOC_H_ */ diff --git a/soc/raspberrypi/rpi_pico/rp2040/CMakeLists.txt b/soc/raspberrypi/rpi_pico/rp2040/CMakeLists.txt new file mode 100644 index 00000000000000..4c53cf10d0fd4a --- /dev/null +++ b/soc/raspberrypi/rpi_pico/rp2040/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright (c) 2021 Yonatan Schachter +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/raspberrypi/rp2xxx/Kconfig b/soc/raspberrypi/rpi_pico/rp2040/Kconfig similarity index 92% rename from soc/raspberrypi/rp2xxx/Kconfig rename to soc/raspberrypi/rpi_pico/rp2040/Kconfig index 1abc32af2ceee4..818482b9952383 100644 --- a/soc/raspberrypi/rp2xxx/Kconfig +++ b/soc/raspberrypi/rpi_pico/rp2040/Kconfig @@ -4,7 +4,7 @@ # Copyright (c) 2021 Yonatan Schachter # SPDX-License-Identifier: Apache-2.0 -config SOC_SERIES_RP2XXX +config SOC_SERIES_RP2040 select ARM select CPU_CORTEX_M0PLUS select CPU_CORTEX_M_HAS_SYSTICK @@ -14,7 +14,9 @@ config SOC_SERIES_RP2XXX select XIP select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE help - Enable support for Raspberry Pi RP2 MCU series + Enable support for Raspberry Pi RP2040 MCU series + +if SOC_SERIES_RP2040 config RP2_REQUIRES_SECOND_STAGE_BOOT bool @@ -51,3 +53,5 @@ config RP2_FLASH_AT25SF128A help Configure RP2 to use a AT25SF128A flash chip, or similar. Should be selected by the board definition, not the user. + +endif diff --git a/soc/raspberrypi/rp2xxx/Kconfig.defconfig b/soc/raspberrypi/rpi_pico/rp2040/Kconfig.defconfig similarity index 70% rename from soc/raspberrypi/rp2xxx/Kconfig.defconfig rename to soc/raspberrypi/rpi_pico/rp2040/Kconfig.defconfig index 82256e806d0532..adaa1e691011f0 100644 --- a/soc/raspberrypi/rp2xxx/Kconfig.defconfig +++ b/soc/raspberrypi/rpi_pico/rp2040/Kconfig.defconfig @@ -1,14 +1,14 @@ -# Raspberry Pi RP2XXX MCU line +# Raspberry Pi RP2040 MCU line # Copyright (c) 2021 Nordic Semiconductor ASA # Copyright (c) 2021 Yonatan Schachter # SPDX-License-Identifier: Apache-2.0 -if SOC_SERIES_RP2XXX +if SOC_SERIES_RP2040 rsource "Kconfig.defconfig.rp2*" config NUM_IRQS default 26 -endif # SOC_SERIES_RP2XXX +endif # SOC_SERIES_RP2040 diff --git a/soc/raspberrypi/rp2xxx/Kconfig.defconfig.rp2040 b/soc/raspberrypi/rpi_pico/rp2040/Kconfig.defconfig.rp2040 similarity index 100% rename from soc/raspberrypi/rp2xxx/Kconfig.defconfig.rp2040 rename to soc/raspberrypi/rpi_pico/rp2040/Kconfig.defconfig.rp2040 diff --git a/soc/raspberrypi/rp2xxx/Kconfig.soc b/soc/raspberrypi/rpi_pico/rp2040/Kconfig.soc similarity index 67% rename from soc/raspberrypi/rp2xxx/Kconfig.soc rename to soc/raspberrypi/rpi_pico/rp2040/Kconfig.soc index 045061697fe3ed..c5b99567a7e399 100644 --- a/soc/raspberrypi/rp2xxx/Kconfig.soc +++ b/soc/raspberrypi/rpi_pico/rp2040/Kconfig.soc @@ -1,19 +1,19 @@ -# Raspberry Pi RP2XXX MCU line +# Raspberry Pi RP2040 MCU line # Copyright (c) 2021 Nordic Semiconductor ASA # Copyright (c) 2021 Yonatan Schachter # SPDX-License-Identifier: Apache-2.0 -config SOC_RP2040 - bool - select SOC_SERIES_RP2XXX +config SOC_SERIES + default "rp2040" if SOC_SERIES_RP2040 -config SOC_SERIES_RP2XXX +config SOC_SERIES_RP2040 bool select SOC_FAMILY_RPI_PICO -config SOC_SERIES - default "rp2xxx" if SOC_SERIES_RP2XXX +config SOC_RP2040 + bool + select SOC_SERIES_RP2040 config SOC default "rp2040" if SOC_RP2040 diff --git a/soc/raspberrypi/rp2xxx/linker.ld b/soc/raspberrypi/rpi_pico/rp2040/linker.ld similarity index 100% rename from soc/raspberrypi/rp2xxx/linker.ld rename to soc/raspberrypi/rpi_pico/rp2040/linker.ld diff --git a/soc/raspberrypi/rp2xxx/CMakeLists.txt b/soc/raspberrypi/rpi_pico/rp2350/CMakeLists.txt similarity index 100% rename from soc/raspberrypi/rp2xxx/CMakeLists.txt rename to soc/raspberrypi/rpi_pico/rp2350/CMakeLists.txt diff --git a/soc/raspberrypi/rpi_pico/rp2350/Kconfig b/soc/raspberrypi/rpi_pico/rp2350/Kconfig new file mode 100644 index 00000000000000..2de28a5dd56f27 --- /dev/null +++ b/soc/raspberrypi/rpi_pico/rp2350/Kconfig @@ -0,0 +1,29 @@ +# Raspberry Pi RP235XX MCU line + +# Copyright (c) 2024 Andrew Featherstone +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RP2350 + select HAS_RPI_PICO + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + select SOC_RESET_HOOK + select XIP + +config SOC_RP2350A_M33 + select ARM + select ARM_TRUSTZONE_M + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select CPU_CORTEX_M33 + select CPU_HAS_ARM_MPU + select CPU_HAS_ARM_SAU + +config RP2_REQUIRES_IMAGE_DEFINITION_BLOCK + bool + default y + # Currently the IDF only supports using the Cortex-M33 cores. Enforce + # this at build configuration time. + depends on SOC_SERIES_RP2350 && CPU_CORTEX_M33 + help + Include an Image Definition Block (IMAGE_DEF) to enable the bootroom in + RP23XX devices to consider this a valid image in flash. diff --git a/soc/raspberrypi/rpi_pico/rp2350/Kconfig.defconfig b/soc/raspberrypi/rpi_pico/rp2350/Kconfig.defconfig new file mode 100644 index 00000000000000..46b05749045960 --- /dev/null +++ b/soc/raspberrypi/rpi_pico/rp2350/Kconfig.defconfig @@ -0,0 +1,14 @@ +# Raspberry Pi RP2350 MCU line + +# Copyright (c) 2024 Andrew Featherstone +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RP2350 + +config BUILD_OUTPUT_UF2_USE_FLASH_BASE + default y if BUILD_OUTPUT_UF2 + +config NUM_IRQS + default 52 + +endif # SOC_SERIES_RP2350 diff --git a/soc/raspberrypi/rpi_pico/rp2350/Kconfig.soc b/soc/raspberrypi/rpi_pico/rp2350/Kconfig.soc new file mode 100644 index 00000000000000..19012bb5648ab2 --- /dev/null +++ b/soc/raspberrypi/rpi_pico/rp2350/Kconfig.soc @@ -0,0 +1,24 @@ +# Raspberry Pi RP2350 MCU line + +# Copyright (c) 2024 Andrew Featherstone +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RP2350 + bool + select SOC_FAMILY_RPI_PICO + +config SOC_SERIES + default "rp2350" if SOC_SERIES_RP2350 + +config SOC_RP2350A + bool + select SOC_SERIES_RP2350 + +config SOC_RP2350A_M33 + bool + select SOC_RP2350A + help + Use the RP2350A with a Cortex-M33 core in both 'sockets'. + +config SOC + default "rp2350a" if SOC_RP2350A diff --git a/soc/raspberrypi/rpi_pico/rp2350/linker.ld b/soc/raspberrypi/rpi_pico/rp2350/linker.ld new file mode 100644 index 00000000000000..6368409c9e2739 --- /dev/null +++ b/soc/raspberrypi/rpi_pico/rp2350/linker.ld @@ -0,0 +1,27 @@ +/* linker.ld - Linker command/script file */ + +/* + * Copyright (c) 2024 Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ + +MEMORY +{ + IMAGE_DEF_FLASH (r) : ORIGIN = 0x10000000, LENGTH = 128 +} + +SECTIONS +{ + .image_def : { + LONG(0xffffded3) /* PICOBIN_BLOCK_MARKER_START */ + LONG(0x10210142) /* IMAGE_DEF Item */ + LONG(0x00000203) /* VECTOR_TABLE Item */ + LONG(ABSOLUTE(_vector_start)) /* - Address of the vector table in flash */ + LONG(0x000003ff) /* Last Item in Block */ + LONG(0x00000000) /* End of block loop */ + LONG(0xab123579) /* PICOBIN_BLOCK_MARKER_END */ + } > IMAGE_DEF_FLASH +} + +#include diff --git a/soc/raspberrypi/rpi_pico/rp2350/soc.c b/soc/raspberrypi/rpi_pico/rp2350/soc.c new file mode 100644 index 00000000000000..84bcbffc7d97f7 --- /dev/null +++ b/soc/raspberrypi/rpi_pico/rp2350/soc.c @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2024 Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for Raspberry Pi RP235xx MCUs + * + * This module provides routines to initialize and support board-level hardware + * for the Raspberry Pi RP235xx (RP2350A, RP2350B, RP2354A, RP2354B). + */ + +#if CONFIG_SOC_RESET_HOOK +#include + + +void soc_reset_hook(void) +{ + runtime_init_per_core_enable_coprocessors(); +} + +#endif /* CONFIG_SOC_RESET_HOOK */ diff --git a/soc/raspberrypi/rpi_pico/soc.yml b/soc/raspberrypi/rpi_pico/soc.yml new file mode 100644 index 00000000000000..32039c20944012 --- /dev/null +++ b/soc/raspberrypi/rpi_pico/soc.yml @@ -0,0 +1,11 @@ +family: +- name: rpi_pico + series: + - name: rp2040 + socs: + - name: rp2040 + - name: rp2350 + socs: + - name: rp2350a + cpuclusters: + - name: m33 diff --git a/soc/raspberrypi/soc.yml b/soc/raspberrypi/soc.yml deleted file mode 100644 index 192d7a947f265b..00000000000000 --- a/soc/raspberrypi/soc.yml +++ /dev/null @@ -1,6 +0,0 @@ -family: -- name: rpi_pico - series: - - name: rp2xxx - socs: - - name: rp2040 diff --git a/tests/drivers/adc/adc_api/boards/rpi_pico2_rp2350a_m33.overlay b/tests/drivers/adc/adc_api/boards/rpi_pico2_rp2350a_m33.overlay new file mode 100644 index 00000000000000..1448e15035db9c --- /dev/null +++ b/tests/drivers/adc/adc_api/boards/rpi_pico2_rp2350a_m33.overlay @@ -0,0 +1,12 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Andrew Featherstone + */ + +/* Pico 2 is compatible with the Pico 1, so reuse. */ +#include "rpi_pico.overlay" + +&adc { + status = "okay"; +}; diff --git a/tests/drivers/dma/chan_blen_transfer/socs/rp2040.overlay b/tests/drivers/dma/chan_blen_transfer/socs/rp2040.overlay new file mode 100644 index 00000000000000..ed3236a449c20e --- /dev/null +++ b/tests/drivers/dma/chan_blen_transfer/socs/rp2040.overlay @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2024 Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ + +tst_dma0: &dma { + status = "okay"; +}; diff --git a/tests/drivers/dma/chan_blen_transfer/socs/rp2350a_m33.overlay b/tests/drivers/dma/chan_blen_transfer/socs/rp2350a_m33.overlay new file mode 100644 index 00000000000000..9cf49bb6cd3f9f --- /dev/null +++ b/tests/drivers/dma/chan_blen_transfer/socs/rp2350a_m33.overlay @@ -0,0 +1,8 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Andrew Featherstone + */ + +/* RP2350A is compatible with the RP2040, so reuse. */ +#include "rp2040.overlay" diff --git a/tests/drivers/dma/loop_transfer/boards/rpi_pico2_rp2350a_m33.overlay b/tests/drivers/dma/loop_transfer/boards/rpi_pico2_rp2350a_m33.overlay new file mode 100644 index 00000000000000..8b83efe6ea08f2 --- /dev/null +++ b/tests/drivers/dma/loop_transfer/boards/rpi_pico2_rp2350a_m33.overlay @@ -0,0 +1,8 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Andrew Featherstone + */ + +/* Pico 2 is compatible with the Pico 1, so reuse. */ +#include "rpi_pico.overlay" diff --git a/tests/drivers/gpio/gpio_api_1pin/boards/rpi_pico2_rp2350a_m33.overlay b/tests/drivers/gpio/gpio_api_1pin/boards/rpi_pico2_rp2350a_m33.overlay new file mode 100644 index 00000000000000..6bfb9f711f759f --- /dev/null +++ b/tests/drivers/gpio/gpio_api_1pin/boards/rpi_pico2_rp2350a_m33.overlay @@ -0,0 +1,13 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Andrew Featherstone + */ + +/ { + resources { + compatible = "test-gpio-external-pulldown"; + /* Choice of pin on the header is arbitrary. */ + gpios = <&pico_header 15 GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/tests/drivers/gpio/gpio_api_1pin/dts/bindings/test-gpio-external-pulldown.yaml b/tests/drivers/gpio/gpio_api_1pin/dts/bindings/test-gpio-external-pulldown.yaml new file mode 100644 index 00000000000000..4534b20f7e2501 --- /dev/null +++ b/tests/drivers/gpio/gpio_api_1pin/dts/bindings/test-gpio-external-pulldown.yaml @@ -0,0 +1,18 @@ +# +# Copyright (c) 2024 Andrew Featherstone +# +# SPDX-License-Identifier: Apache-2.0 +# + +description: | + This binding provides resources required to build and run the + tests/drivers/gpio/gpio_api_1pin test in Zephyr on certain hardware. + +compatible: "test-gpio-external-pulldown" + +properties: + gpios: + type: phandle-array + required: true + description: | + Identity of a GPIO that will be configured as both an output and input. diff --git a/tests/drivers/gpio/gpio_api_1pin/src/test_gpio_api.h b/tests/drivers/gpio/gpio_api_1pin/src/test_gpio_api.h index 024c9d1a9db28a..c001c2026bcd7a 100644 --- a/tests/drivers/gpio/gpio_api_1pin/src/test_gpio_api.h +++ b/tests/drivers/gpio/gpio_api_1pin/src/test_gpio_api.h @@ -11,10 +11,18 @@ #include #include -#if DT_NODE_HAS_PROP(DT_ALIAS(led0), gpios) -#define TEST_NODE DT_GPIO_CTLR(DT_ALIAS(led0), gpios) -#define TEST_PIN DT_GPIO_PIN(DT_ALIAS(led0), gpios) -#define TEST_PIN_DTS_FLAGS DT_GPIO_FLAGS(DT_ALIAS(led0), gpios) +/* If possible, use a dedicated GPIO with an external pulldown resistor. + * Otherwise, fallback to repurposing led0 as a GPIO. The latter won't always + * work as expected when reconfigured as an input. + */ +#if DT_NODE_HAS_STATUS(DT_INST(0, test_gpio_external_pulldown), okay) +#define TEST_NODE DT_GPIO_CTLR(DT_INST(0, test_gpio_external_pulldown), gpios) +#define TEST_PIN DT_GPIO_PIN(DT_INST(0, test_gpio_external_pulldown), gpios) +#define TEST_PIN_DTS_FLAGS DT_GPIO_FLAGS(DT_INST(0, test_gpio_external_pulldown), gpios) +#elif DT_NODE_HAS_PROP(DT_ALIAS(led0), gpios) +#define TEST_NODE DT_GPIO_CTLR(DT_ALIAS(led0), gpios) +#define TEST_PIN DT_GPIO_PIN(DT_ALIAS(led0), gpios) +#define TEST_PIN_DTS_FLAGS DT_GPIO_FLAGS(DT_ALIAS(led0), gpios) #else #error Unsupported board #endif diff --git a/tests/drivers/gpio/gpio_api_1pin/testcase.yaml b/tests/drivers/gpio/gpio_api_1pin/testcase.yaml index 1c5c6f9eb7f9fc..0380ed1eafff8a 100644 --- a/tests/drivers/gpio/gpio_api_1pin/testcase.yaml +++ b/tests/drivers/gpio/gpio_api_1pin/testcase.yaml @@ -1,13 +1,22 @@ +common: + tags: + - drivers + - gpio + depends_on: gpio + min_flash: 48 tests: drivers.gpio.1pin: - tags: - - drivers - - gpio - depends_on: gpio - min_flash: 48 + filter: > + dt_enabled_alias_with_parent_compat("led0", "gpio-leds") + and not dt_compat_enabled("test-gpio-external-pulldown") # Fix exclude when we can exclude just sim run platform_exclude: - mps2/an385 - mps2/an521/cpu0 - neorv32 - filter: dt_enabled_alias_with_parent_compat("led0", "gpio-leds") + drivers.gpio.1pin.external_pull_down: + # For testing boards that require a test fixture that provides a pulldown + # resistor on the GPIO used for the test. + filter: dt_compat_enabled("test-gpio-external-pulldown") + harness_config: + fixture: gpio_external_pull_down diff --git a/tests/drivers/spi/spi_loopback/boards/rpi_pico.overlay b/tests/drivers/spi/spi_loopback/boards/rpi_pico.overlay index c6f4ecb40b6188..221f06e43ece6e 100644 --- a/tests/drivers/spi/spi_loopback/boards/rpi_pico.overlay +++ b/tests/drivers/spi/spi_loopback/boards/rpi_pico.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include &dma { status = "okay";