not throwing error when pte.u bit is low in second stage translation

[mhayat-10xe]

Risc-V privileged spec states that:

For G-stage address translation, all memory accesses (including those made to access data structures for VS-stage address translation) are considered to be user-level accesses, as though executed in U-mode.

I wrote an assertion that states:

If there is G-stage translation and the pte.u bit is low then in the next cycle trans_error must be high.

Here is the counter example of the assertion failure. In the 11th cycle, there is leaf pte for translation of iosatp, then in the 15th cycle there is another leaf pte for 1st stage translation and in the 17th cycle there is another leaf pte for second stage translation where pte.u bit is low. Now in the next cycle trans_error must be high but it is low which is wrong.