From d6f997259487fc01b1aa6d24bdc7b960c4aaec46 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Tue, 6 Aug 2024 22:34:20 +0200 Subject: [PATCH] all: Handle spirv in addition to spirv(32,64) where applicable. Some of this is arbitrary since spirv (as opposed to spirv32/spirv64) refers to the version with logical memory layout, i.e. no 'real' pointers. This change at least matches what clang does. --- lib/std/Target.zig | 14 +++++++------- src/Compilation.zig | 4 ++-- src/Sema.zig | 10 +++++----- src/Zcu.zig | 3 +-- src/link/SpirV.zig | 2 +- src/target.zig | 6 +++--- 6 files changed, 19 insertions(+), 20 deletions(-) diff --git a/lib/std/Target.zig b/lib/std/Target.zig index 3471dc2c1efd..1d08e7faf324 100644 --- a/lib/std/Target.zig +++ b/lib/std/Target.zig @@ -1163,7 +1163,7 @@ pub const Cpu = struct { pub inline fn isSpirV(arch: Arch) bool { return switch (arch) { - .spirv32, .spirv64 => true, + .spirv, .spirv32, .spirv64 => true, else => false, }; } @@ -1348,8 +1348,8 @@ pub const Cpu = struct { /// Returns whether this architecture supports the address space pub fn supportsAddressSpace(arch: Arch, address_space: std.builtin.AddressSpace) bool { - const is_nvptx = arch == .nvptx or arch == .nvptx64; - const is_spirv = arch == .spirv32 or arch == .spirv64; + const is_nvptx = arch.isNvptx(); + const is_spirv = arch.isSpirV(); const is_gpu = is_nvptx or is_spirv or arch == .amdgcn; return switch (address_space) { .generic => true, @@ -1378,7 +1378,7 @@ pub const Cpu = struct { .x86, .x86_64 => "x86", .nvptx, .nvptx64 => "nvptx", .wasm32, .wasm64 => "wasm", - .spirv32, .spirv64 => "spirv", + .spirv, .spirv32, .spirv64 => "spirv", else => @tagName(arch), }; } @@ -1401,7 +1401,7 @@ pub const Cpu = struct { .amdgcn => &amdgpu.all_features, .riscv32, .riscv64 => &riscv.all_features, .sparc, .sparc64 => &sparc.all_features, - .spirv32, .spirv64 => &spirv.all_features, + .spirv, .spirv32, .spirv64 => &spirv.all_features, .s390x => &s390x.all_features, .x86, .x86_64 => &x86.all_features, .xtensa => &xtensa.all_features, @@ -1431,7 +1431,7 @@ pub const Cpu = struct { .amdgcn => comptime allCpusFromDecls(amdgpu.cpu), .riscv32, .riscv64 => comptime allCpusFromDecls(riscv.cpu), .sparc, .sparc64 => comptime allCpusFromDecls(sparc.cpu), - .spirv32, .spirv64 => comptime allCpusFromDecls(spirv.cpu), + .spirv, .spirv32, .spirv64 => comptime allCpusFromDecls(spirv.cpu), .s390x => comptime allCpusFromDecls(s390x.cpu), .x86, .x86_64 => comptime allCpusFromDecls(x86.cpu), .xtensa => comptime allCpusFromDecls(xtensa.cpu), @@ -1521,7 +1521,7 @@ pub const Cpu = struct { .amdgcn => &amdgpu.cpu.generic, .riscv32 => &riscv.cpu.generic_rv32, .riscv64 => &riscv.cpu.generic_rv64, - .spirv32, .spirv64 => &spirv.cpu.generic, + .spirv, .spirv32, .spirv64 => &spirv.cpu.generic, .sparc => &sparc.cpu.generic, .sparc64 => &sparc.cpu.v9, // 64-bit SPARC needs v9 as the baseline .s390x => &s390x.cpu.generic, diff --git a/src/Compilation.zig b/src/Compilation.zig index 01a5772e231d..d7dabd51640e 100644 --- a/src/Compilation.zig +++ b/src/Compilation.zig @@ -6266,7 +6266,7 @@ fn canBuildLibCompilerRt(target: std.Target, use_llvm: bool) bool { else => {}, } switch (target.cpu.arch) { - .spirv32, .spirv64 => return false, + .spirv, .spirv32, .spirv64 => return false, else => {}, } return switch (target_util.zigBackend(target, use_llvm)) { @@ -6284,7 +6284,7 @@ fn canBuildZigLibC(target: std.Target, use_llvm: bool) bool { else => {}, } switch (target.cpu.arch) { - .spirv32, .spirv64 => return false, + .spirv, .spirv32, .spirv64 => return false, else => {}, } return switch (target_util.zigBackend(target, use_llvm)) { diff --git a/src/Sema.zig b/src/Sema.zig index 20daa78e9a3f..4fcb9c98c860 100644 --- a/src/Sema.zig +++ b/src/Sema.zig @@ -10038,11 +10038,11 @@ fn finishFunc( else => "x86_64", }, .Kernel => switch (arch) { - .nvptx, .nvptx64, .amdgcn, .spirv32, .spirv64 => null, + .nvptx, .nvptx64, .amdgcn, .spirv, .spirv32, .spirv64 => null, else => "nvptx, amdgcn and SPIR-V", }, .Fragment, .Vertex => switch (arch) { - .spirv32, .spirv64 => null, + .spirv, .spirv32, .spirv64 => null, else => "SPIR-V", }, })) |allowed_platform| { @@ -26703,7 +26703,7 @@ fn zirWorkItem( switch (target.cpu.arch) { // TODO: Allow for other GPU targets. - .amdgcn, .spirv64, .spirv32 => {}, + .amdgcn, .spirv, .spirv64, .spirv32 => {}, else => { return sema.fail(block, builtin_src, "builtin only available on GPU targets; targeted architecture is {s}", .{@tagName(target.cpu.arch)}); }, @@ -37323,9 +37323,9 @@ pub fn analyzeAsAddressSpace( const target = pt.zcu.getTarget(); const arch = target.cpu.arch; - const is_nv = arch == .nvptx or arch == .nvptx64; + const is_nv = arch.isNvptx(); const is_amd = arch == .amdgcn; - const is_spirv = arch == .spirv32 or arch == .spirv64; + const is_spirv = arch.isSpirV(); const is_gpu = is_nv or is_amd or is_spirv; const supported = switch (address_space) { diff --git a/src/Zcu.zig b/src/Zcu.zig index bcb331b59755..10fa45a62bda 100644 --- a/src/Zcu.zig +++ b/src/Zcu.zig @@ -2910,6 +2910,7 @@ pub fn atomicPtrAlignment( .s390x, .wasm64, .ve, + .spirv, .spirv64, .loongarch64, => 64, @@ -2919,8 +2920,6 @@ pub fn atomicPtrAlignment( => 128, .x86_64 => if (std.Target.x86.featureSetHas(target.cpu.features, .cx16)) 128 else 64, - - .spirv => @panic("TODO what should this value be?"), }; if (ty.toIntern() == .bool_type) return .none; diff --git a/src/link/SpirV.zig b/src/link/SpirV.zig index 57e69ed860e2..f76ceec2f5ff 100644 --- a/src/link/SpirV.zig +++ b/src/link/SpirV.zig @@ -80,7 +80,7 @@ pub fn createEmpty( errdefer self.deinit(); switch (target.cpu.arch) { - .spirv32, .spirv64 => {}, + .spirv, .spirv32, .spirv64 => {}, else => unreachable, // Caught by Compilation.Config.resolve. } diff --git a/src/target.zig b/src/target.zig index eb48b7b2e6ac..6246656fdcfd 100644 --- a/src/target.zig +++ b/src/target.zig @@ -196,7 +196,7 @@ pub fn supportsStackProtector(target: std.Target, backend: std.builtin.CompilerB else => {}, } switch (target.cpu.arch) { - .spirv32, .spirv64 => return false, + .spirv, .spirv32, .spirv64 => return false, else => {}, } return switch (backend) { @@ -207,7 +207,7 @@ pub fn supportsStackProtector(target: std.Target, backend: std.builtin.CompilerB pub fn clangSupportsStackProtector(target: std.Target) bool { return switch (target.cpu.arch) { - .spirv32, .spirv64 => return false, + .spirv, .spirv32, .spirv64 => return false, else => true, }; } @@ -220,7 +220,7 @@ pub fn supportsReturnAddress(target: std.Target) bool { return switch (target.cpu.arch) { .wasm32, .wasm64 => target.os.tag == .emscripten, .bpfel, .bpfeb => false, - .spirv32, .spirv64 => false, + .spirv, .spirv32, .spirv64 => false, else => true, }; }