[verible-verilog-format] reported by reviewdog 🐶 Raw Output: core/decoder.sv:860:- {7'b000_0100, 3'b100}: core/decoder.sv:861:- begin core/decoder.sv:862:- if (instr.instr[24:20] == 5'b00000) core/decoder.sv:863:- instruction_o.op = ariane_pkg::ZEXTH; core/decoder.sv:864:- else core/decoder.sv:865:- illegal_instr_bm = 1'b1; core/decoder.sv:872:+ { core/decoder.sv:873:+ 7'b000_0100, 3'b100 core/decoder.sv:874:+ } : begin core/decoder.sv:875:+ if (instr.instr[24:20] == 5'b00000) instruction_o.op = ariane_pkg::ZEXTH; core/decoder.sv:876:+ else illegal_instr_bm = 1'b1;