gate reduction changes

10x-Engineers · Dec 11, 2024 · 1186002 · 1186002
1 parent 645d24f
commit 1186002
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Showing 3 changed files with 28 additions and 12 deletions.
diff --git a/core/branch_unit.sv b/core/branch_unit.sv
@@ -83,12 +83,16 @@ module branch_unit #(
     // 3. Zcmt instructions
     if (branch_valid_i) begin
       // write target address which goes to PC Gen or select target address if zcmt
-      resolved_branch_o.target_address = (branch_comp_res_i) | is_zcmt_i ? target_address : next_pc;
-      resolved_branch_o.is_taken = is_zcmt_i ? 1'b1 : branch_comp_res_i;
-      if (is_zcmt_i) begin
-        // Unconditional jump handling
-        resolved_branch_o.is_mispredict = 1'b1;  // miss prediction for ZCMT 
-        resolved_branch_o.cf_type = ariane_pkg::Jump;
+      resolved_branch_o.target_address = (branch_comp_res_i) ? target_address : next_pc;
+      resolved_branch_o.is_taken = branch_comp_res_i;
+      if (CVA6Cfg.RVZCMT) begin
+        if (is_zcmt_i) begin
+          // Unconditional jump handling
+          resolved_branch_o.target_address = target_address;
+          resolved_branch_o.is_taken = 1'b1;
+          resolved_branch_o.is_mispredict = 1'b1;  // miss prediction for ZCMT 
+          resolved_branch_o.cf_type = ariane_pkg::Jump;
+        end
       end
       // check the outcome of the branch speculation
       if (ariane_pkg::op_is_branch(fu_data_i.operation)) begin

diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv
@@ -919,7 +919,9 @@ module csr_regfile
 
     perf_we_o                       = 1'b0;
     perf_data_o                     = 'b0;
-    jvt_d                           = jvt_q;
+    if (CVA6Cfg.RVZCMT) begin
+      jvt_d                         = jvt_q;
+    end
     fcsr_d                          = fcsr_q;
 
     priv_lvl_d                      = priv_lvl_q;
@@ -2472,8 +2474,13 @@ module csr_regfile
   assign frm_o = fcsr_q.frm;
   assign fprec_o = fcsr_q.fprec;
   //JVT outputs
-  assign jvt_o.base = jvt_q.base;
-  assign jvt_o.mode = jvt_q.mode;
+  if (CVA6Cfg.RVZCMT) begin
+    assign jvt_o.base = jvt_q.base;
+    assign jvt_o.mode = jvt_q.mode;
+  end else begin
+    assign jvt_o.base = '0;
+    assign jvt_o.mode = '0;
+  end
   // MMU outputs
   assign satp_ppn_o = CVA6Cfg.RVS ? satp_q.ppn : '0;
   assign vsatp_ppn_o = CVA6Cfg.RVH ? vsatp_q.ppn : '0;
@@ -2540,7 +2547,9 @@ module csr_regfile
       priv_lvl_q   <= riscv::PRIV_LVL_M;
       // floating-point registers
       fcsr_q       <= '0;
-      jvt_q        <= '0;
+      if (CVA6Cfg.RVZCMT) begin
+        jvt_q      <= '0;
+      end
       // debug signals
       debug_mode_q <= 1'b0;
       if (CVA6Cfg.DebugEn) begin
@@ -2624,7 +2633,9 @@ module csr_regfile
       priv_lvl_q <= priv_lvl_d;
       // floating-point registers
       fcsr_q     <= fcsr_d;
-      jvt_q      <= jvt_d;
+      if (CVA6Cfg.RVZCMT) begin
+        jvt_q    <= jvt_d;
+      end
       // debug signals
       if (CVA6Cfg.DebugEn) begin
         debug_mode_q <= debug_mode_d;

diff --git a/core/issue_read_operands.sv b/core/issue_read_operands.sv
@@ -1108,7 +1108,6 @@ module issue_read_operands
       x_transaction_rejected_o <= 1'b0;
     end else begin
       fu_data_q <= fu_data_n;
-      is_zcmt_o <= issue_instr_i[0].is_zcmt;
       if (CVA6Cfg.RVH) begin
         tinst_q <= tinst_n;
       end
@@ -1123,6 +1122,8 @@ module issue_read_operands
         pc_o                  <= issue_instr_i[0].pc;
         is_compressed_instr_o <= issue_instr_i[0].is_compressed;
         branch_predict_o      <= issue_instr_i[0].bp;
+        if (CVA6Cfg.RVZCMT)  is_zcmt_o <= issue_instr_i[0].is_zcmt;
+        else is_zcmt_o                 <= '0;
       end
       x_transaction_rejected_o <= 1'b0;
       if (issue_instr_i[0].fu == CVXIF) begin