wt cache cond update

10x-Engineers · Dec 9, 2024 · 6af27de · 6af27de
1 parent 35515b6
commit 6af27de
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Showing 2 changed files with 2 additions and 3 deletions.
diff --git a/core/cache_subsystem/wt_dcache.sv b/core/cache_subsystem/wt_dcache.sv
@@ -188,10 +188,10 @@ module wt_dcache
   // read controllers (LD unit and PTW/MMU)
   ///////////////////////////////////////////////////////
 
-  // 0 is used by MMU, 1 by READ access requests
+  // 0 is used by MMU or implicit read by zcmt, 1 by READ access requests
   for (genvar k = 0; k < NumPorts - 1; k++) begin : gen_rd_ports
     // set these to high prio ports
-    if ((k == 0 && CVA6Cfg.MmuPresent) || (k == 1) || (k == 2 && CVA6Cfg.EnableAccelerator)) begin
+    if ((k == 0 && CVA6Cfg.MmuPresent) || (k == 0 && CVA6Cfg.RVZCMT ) || (k == 1) || (k == 2 && CVA6Cfg.EnableAccelerator)) begin
       assign rd_prio[k] = 1'b1;
       wt_dcache_ctrl #(
           .CVA6Cfg(CVA6Cfg),

diff --git a/core/zcmt_decoder.sv b/core/zcmt_decoder.sv
@@ -38,7 +38,6 @@ module zcmt_decoder #(
   logic [7:0] index;  //index of instruction
   //Physical address: jvt + (index <<2)
   logic [CVA6Cfg.XLEN+1:0] table_address;  //Virtual  address: {00,Physical address}
-  logic [CVA6Cfg.XLEN-1:0] data_rdata;  //data received from instruction memory
   logic [20:0] jump_addr;  //jump address immidiate
 
   always_comb begin