Wait-for-shared-TLB state addition in lu-fsm

10x-Engineers · Dec 18, 2023 · 71dffb3 · 71dffb3
1 parent 0d4ea5e
commit 71dffb3
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Showing 8 changed files with 755 additions and 1,143 deletions.
diff --git a/Makefile b/Makefile
@@ -89,7 +89,7 @@ endif
 # target takes one of the following cva6 hardware configuration:
 # cv64a6_imafdc_sv39, cv32a6_imac_sv0, cv32a6_imac_sv32, cv32a6_imafc_sv32, cv32a6_ima_sv32_fpga
 # Changing the default target to cv32a60x for Step1 verification
-target     ?= cv64a6_imafdc_sv39
+target     ?= cv32a60x
 ifndef TARGET_CFG
 	export TARGET_CFG = $(target)
 endif

diff --git a/core/Flist.cva6 b/core/Flist.cva6
@@ -180,7 +180,6 @@ ${CVA6_REPO_DIR}/common/local/util/sram.sv
 ${CVA6_REPO_DIR}/core/mmu_sv39/mmu.sv
 ${CVA6_REPO_DIR}/core/mmu_sv39/ptw.sv
 ${CVA6_REPO_DIR}/core/mmu_sv39/tlb.sv
-${CVA6_REPO_DIR}/core/mmu_sv39/shared_tlb.sv
 
 // MMU Sv32
 ${CVA6_REPO_DIR}/core/mmu_sv32/cva6_mmu_sv32.sv

diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv
@@ -758,7 +758,7 @@ package ariane_pkg;
     logic                  is_1G;    //
     logic [27-1:0]         vpn;      // VPN (39bits) = 27bits + 12bits offset
     logic [ASID_WIDTH-1:0] asid;
-    riscv::pte_sv39_t      content;
+    riscv::pte_t      content;
   } tlb_update_t;
 
   // Bits required for representation of physical address space as 4K pages

diff --git a/core/include/riscv_pkg.sv b/core/include/riscv_pkg.sv
@@ -305,7 +305,7 @@ package riscv;
     logic w;
     logic r;
     logic v;
-  } pte_sv39_t;
+  } pte_t;
 
   // memory management, pte for sv32
   typedef struct packed {