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| [#zba,reftext=Address generation instructions] | ||
| === Zba extension | ||
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| [NOTE,caption=Frozen] | ||
| ==== | ||
| The Zba extension is frozen. | ||
| ==== | ||
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| The Zba instructions can be used to accelerate the generation of addresses that index into arrays of basic types (halfword, word, doubleword) using both unsigned word-sized and XLEN-sized indices: a shifted index is added to a base address. | ||
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| The shift and add instructions do a left shift of 1, 2, or 3 because these are commonly found in real-world code and because they can be implemented with a minimal amount of additional hardware beyond that of the simple adder. This avoids lengthening the critical path in implementations. | ||
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| While the shift and add instructions are limited to a maximum left shift of 3, the slli instruction (from the base ISA) can be used to perform similar shifts for indexing into arrays of wider elements. The slli.uw -- added in this extension -- can be used when the index is to be interpreted as an unsigned word. | ||
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| The following instructions (and pseudoinstructions) comprise the Zba extension: | ||
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| .. list-table:: Zba Extension Instructions | ||
| :header-rows: 1 | ||
| :widths: 1 1 4 8 | ||
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| * - RV32 | ||
| - RV64 | ||
| - Mnemonic | ||
| - Instruction | ||
| * - | ||
| - ✓ | ||
| - add.uw _rd_, _rs1_, _rs2_ | ||
| - <<#insns-add_uw>> | ||
| * - | ||
| - ✓ | ||
| - ✓ | ||
| - sh1add _rd_, _rs1_, _rs2_ | ||
| - <<#insns-sh1add>> | ||
| * - | ||
| - ✓ | ||
| - sh1add.uw _rd_, _rs1_, _rs2_ | ||
| - <<#insns-sh1add_uw>> | ||
| * - | ||
| - ✓ | ||
| - ✓ | ||
| - sh2add _rd_, _rs1_, _rs2_ | ||
| - <<#insns-sh2add>> | ||
| * - | ||
| - ✓ | ||
| - sh2add.uw _rd_, _rs1_, _rs2_ | ||
| - <<#insns-sh2add_uw>> | ||
| * - | ||
| - ✓ | ||
| - ✓ | ||
| - sh3add _rd_, _rs1_, _rs2_ | ||
| - <<#insns-sh3add>> | ||
| * - | ||
| - ✓ | ||
| - sh3add.uw _rd_, _rs1_, _rs2_ | ||
| - <<#insns-sh3add_uw>> | ||
| * - | ||
| - ✓ | ||
| - slli.uw _rd_, _rs1_, _imm_ | ||
| - <<#insns-slli_uw>> | ||
| * - | ||
| - ✓ | ||
| - zext.w _rd_, _rs_ | ||
| - <<#insns-add_uw>> | ||
| ============= | ||
| Bitmanip Extension Collection | ||
| ============= | ||
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| The bit-manipulation (bitmanip) extension collection is comprised of several component extensions to the base RISC-V architecture. These extensions aim to provide a combination of code size reduction, performance improvement, and energy reduction. The instructions are designed for general use, with some being more useful in specific domains. The bitmanip extensions are organized into smaller extensions, each with its own Zb*-extension name, focusing on common function and use cases. | ||
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| Each bitmanip extension includes a group of instructions that share similar purposes and can often share the same logic. While some instructions are specific to one extension, others are available in multiple extensions. The mnemonics and encodings of instructions are independent of the extensions, eliminating redundancy in logic or encoding when implementing extensions with overlapping instructions. | ||
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| The bitmanip extensions are defined for RV32 and RV64, with most instructions expected to be forward-compatible with RV128. Although shift-immediate instructions are limited to a 6-bit immediate field, a 7th bit is available in the encoding space for potential use in RV128. | ||
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| Word Instructions | ||
| ---------------- | ||
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| The bitmanip extension follows the RV64 convention that w-suffixed instructions (without a dot before the w) ignore the upper 32 bits of their inputs. These instructions operate on the least-significant 32 bits as signed values and produce a 32-bit signed result that is sign-extended to XLEN. | ||
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| Bitmanip instructions with the suffix .uw have one operand that is an unsigned 32-bit value extracted from the least significant 32 bits of the specified register. Other than that, they perform full XLEN operations. | ||
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| Instructions with the suffix .b, .h, and .w only consider the least significant 8-bits, 16-bits, and 32-bits of the input, respectively. They produce an XLEN-wide result that is sign-extended or zero-extended based on the specific instruction. | ||
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| Pseudocode for Instruction Semantics | ||
| -------------------------------------- | ||
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| The semantics of each instruction in [insns] are expressed in a SAIL-like syntax. | ||
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| Extensions | ||
| ---------- | ||
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| The first group of bitmanip extensions to be released for Public Review are: | ||
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| [zba] | ||
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| [zbb] | ||
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| [zbc] | ||
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| [zbs] | ||
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| Below is a list of all the instructions (and pseudoinstructions) included in these extensions along with their specific mapping: | ||
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| | RV32 | RV64 | Mnemonic | Instruction | Zba | Zbb | Zbc | Zbs | | ||
| |------|------|----------|-------------|-----|-----|-----|-----| | ||
| | :check: | | add.uw rd, rs1, rs2 | [insns-add_uw] | :check: | | :check: | :check: | | ||
| | :check: | :check: | andn rd, rs1, rs2 | [insns-andn] | :check: | :check: | :check: | :check: | | ||
| | :check: | :check: | clmul rd, rs1, rs2 | [insns-clmul] | :check: | :check: | :check: | :check: | | ||
| | :check: | :check: | clmulh rd, rs1, rs2 | [insns-clmulh] | :check: | :check: | :check: | :check: | | ||
| | :check: | :check: | clmulr rd, rs1, rs2 | [insns-clmulr] | :check: | :check: | :check: | :check: | | ||
| | :check: | :check: | clz rd, rs | [insns-clz] | :check: | :check: | | :check: | | ||
| | :check: | :check: | clzw rd, rs | [insns-clzw] | :check: | :check: | | :check: | | ||
| | :check: | :check: | cpop rd, rs | [insns-cpop] | :check: | :check: | | :check: | | ||
| | :check: | :check: | cpopw rd, rs | [insns-cpopw] | :check: | :check: | | :check: | | ||
| | :check: | :check: | ctz rd, rs | [insns-ctz] | :check: | :check: | | :check: | | ||
| | :check: | :check: | ctzw rd, rs | [insns-ctzw] | :check: | :check: | | :check: | | ||
| | :check: | :check: | max rd, rs1, rs2 | [insns-max] | :check: | :check: | | :check: | | ||
| | :check: | :check: | maxu rd, rs1, rs2 | [insns-maxu] | :check: | :check: | | :check: | | ||
| | :check: | :check: | min rd, rs1, rs2 | [insns-min] | :check: | :check: | | :check: | | ||
| | :check: | :check: | minu rd, rs1, rs2 | [insns-minu] | :check: | :check: | | :check: | | ||
| | :check: | | orc.b rd, rs1, rs2 | [insns-orc_b] | :check: | :check: | | :check: | | ||
| | :check: | :check: | orn rd, rs1, rs2 | [insns-orn] | :check: | :check: | | :check: | | ||
| | :check: | :check: | rev8 rd, rs | [insns-rev8] | :check: | :check: | | :check: | | ||
| | :check: | :check: | rol rd, rs1, rs2 | [insns-rol] | :check: | :check: | | :check: | | ||
| | :check: | :check: | rolw rd, rs1, rs2 | [insns-rolw] | :check: | :check: | | :check: | | ||
| | :check: | :check: | ror rd, rs1, rs2 | [insns-ror] | :check: | :check: | | :check: | | ||
| | :check: | :check: | rori rd, rs1, shamt | [insns-rori] | :check: | :check: | | :check: | | ||
| | :check: | :check: | roriw rd, rs1, shamt | [insns-roriw] | :check: | :check: | | :check: | | ||
| | :check: | :check: | rorw rd, rs1, rs2 | [insns-rorw] | :check: | :check: | | :check: | | ||
| | :check: | :check: | bclr rd, rs1, rs2 | [insns-bclr] | :check: | :check: | | :check: | | ||
| | :check: | :check: | bclri rd, rs1, imm | [insns-bclri] | :check: | :check: | | :check: | | ||
| | :check: | :check: | bext rd, rs1, rs2 | [insns-bext] | :check: | :check: | | :check: | | ||
| | :check: | :check: | bexti rd, rs1, imm | [insns-bexti] | :check: | :check: | | :check: | | ||
| | :check: | :check: | binv rd, rs1, rs2 | [insns-binv] | :check: | :check: | | :check: | | ||
| | :check: | :check: | binvi rd, rs1, imm | [insns-binvi] | :check: | :check: | | :check: | | ||
| | :check: | :check: | bset rd, rs1, rs2 | [insns-bset] | :check: | :check: | | :check: | | ||
| | :check: | :check: | bseti rd, rs1, imm | [insns-bseti] | :check: | :check: | | :check: | | ||
| | :check: | :check: | sext.b rd, rs | [insns-sext_b] | :check: | :check: | | :check: | | ||
| | :check: | :check: | sext.h rd, rs | [insns-sext_h] | :check: | :check: | | :check: | | ||
| | :check: | | sh1add rd, rs1, rs2 | [insns-sh1add] | :check: | | | :check: | | ||
| | :check: | :check: | sh1add.uw rd, rs1, rs2 | [insns-sh1add_uw] | :check: | :check: | :check: | :check: | | ||
| | :check: | | sh2add rd, rs1, rs2 | [insns-sh2add] | :check: | | | :check: | | ||
| | :check: | :check: | sh2add.uw rd, rs1, rs2 | [insns-sh2add_uw] | :check: | :check: | :check: | :check: | | ||
| | :check: | | sh3add rd, rs1, rs2 | [insns-sh3add] | :check: | | | :check: | | ||
| | :check: | :check: | sh3add.uw rd, rs1, rs2 | [insns-sh3add_uw] | :check: | :check: | :check: | :check: | | ||
| | :check: | :check: | slli.uw rd, rs1, imm | [insns-slli_uw] | :check: | :check: | :check: | :check: | | ||
| | :check: | :check: | xnor rd, rs1, rs2 | [insns-xnor] | :check: | :check: | :check: | :check: | | ||
| | :check: | :check: | zext.h rd, rs | [insns-zext_h] | :check: | :check: | | :check: | | ||
| | :check: | :check: | zext.w rd, rs | [insns-add_uw] | :check: | :check: | :check: | :check: | | ||