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zcmt update and fix
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@farhan-108
farhan-108 committed Nov 25, 2024
1 parent a99a9f5 commit a19c82a
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Showing 3 changed files with 41 additions and 78 deletions.
60 changes: 19 additions & 41 deletions core/id_stage.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -85,7 +85,7 @@ module id_stage #(
input logic [CVA6Cfg.XLEN-1:0] hart_id_i,
input logic compressed_ready_i,
//JVT base
input logic [CVA6Cfg.XLEN-1:6] jvt_base_i,
input logic [CVA6Cfg.XLEN-6:0] jvt_base_i,
input logic [5:0] jvt_mode_i,
output logic is_zcmt_o,
input x_compressed_resp_t compressed_resp_i,
Expand All @@ -111,17 +111,17 @@ module id_stage #(

logic [CVA6Cfg.NrIssuePorts-1:0] is_illegal;
logic [CVA6Cfg.NrIssuePorts-1:0] is_illegal_cmp;
logic [CVA6Cfg.NrIssuePorts-1:0] is_illegal_cvxif;
logic [CVA6Cfg.NrIssuePorts-1:0] is_illegal_cvxif,is_illegal_cvxif_zcmp,is_illegal_cvxif_zcmt;
logic [CVA6Cfg.NrIssuePorts-1:0][31:0] instruction;
logic [CVA6Cfg.NrIssuePorts-1:0][31:0] compressed_instr;
logic [CVA6Cfg.NrIssuePorts-1:0][31:0] instruction_cvxif;
logic [CVA6Cfg.NrIssuePorts-1:0][31:0] instruction_cvxif,instruction_cvxif_zcmp,instruction_cvxif_zcmt;
logic [CVA6Cfg.NrIssuePorts-1:0] is_compressed;
logic [CVA6Cfg.NrIssuePorts-1:0] is_compressed_cmp;
logic [CVA6Cfg.NrIssuePorts-1:0] is_compressed_cvxif;
logic [CVA6Cfg.NrIssuePorts-1:0] is_compressed_cvxif,is_compressed_cvxif_zcmp,is_compressed_cvxif_zcmt;

logic [CVA6Cfg.NrIssuePorts-1:0] is_macro_instr_i;
logic stall_instr_fetch;
logic stall_macro_deco;
logic stall_macro_deco, stall_macro_deco_zcmp, stall_macro_deco_zcmt ;
logic is_last_macro_instr_o;
logic is_double_rd_macro_instr_o;
logic [CVA6Cfg.NrIssuePorts-1:0] is_zcmt_instr_i;
Expand All @@ -148,7 +148,7 @@ module id_stage #(
.is_zcmt_instr_o (is_zcmt_instr_i[i])
);
end
if (CVA6Cfg.RVZCMP) begin
if (CVA6Cfg.RVZCMP || CVA6Cfg.RVZCMT) begin
//sequencial decoder
macro_decoder #(
.CVA6Cfg(CVA6Cfg)
Expand All @@ -157,43 +157,16 @@ module id_stage #(
.is_macro_instr_i (is_macro_instr_i[0]),
.clk_i (clk_i),
.rst_ni (rst_ni),
.instr_o (instruction_cvxif[0]),
.instr_o (instruction_cvxif_zcmp[0]),
.illegal_instr_i (is_illegal[0]),
.is_compressed_i (is_compressed[0]),
.issue_ack_i (issue_instr_ack_i[0]),
.illegal_instr_o (is_illegal_cvxif[0]),
.is_compressed_o (is_compressed_cvxif[0]),
.fetch_stall_o (stall_macro_deco),
.illegal_instr_o (is_illegal_cvxif_zcmp[0]),
.is_compressed_o (is_compressed_cvxif_zcmp[0]),
.fetch_stall_o (stall_macro_deco_zcmp),
.is_last_macro_instr_o (is_last_macro_instr_o),
.is_double_rd_macro_instr_o(is_double_rd_macro_instr_o)
);
if (CVA6Cfg.SuperscalarEn) begin
assign instruction_cvxif[CVA6Cfg.NrIssuePorts-1] = '0;
assign is_illegal_cvxif[CVA6Cfg.NrIssuePorts-1] = '0;
assign is_compressed_cvxif[CVA6Cfg.NrIssuePorts-1] = '0;
end
cvxif_compressed_if_driver #(
.CVA6Cfg(CVA6Cfg),
.x_compressed_req_t(x_compressed_req_t),
.x_compressed_resp_t(x_compressed_resp_t)
) i_cvxif_compressed_if_driver_i (
.clk_i (clk_i),
.rst_ni (rst_ni),
.hart_id_i (hart_id_i),
.is_compressed_i (is_compressed_cvxif),
.is_illegal_i (is_illegal_cvxif),
.instruction_i (instruction_cvxif),
.is_compressed_o (is_compressed_cmp),
.is_illegal_o (is_illegal_cmp),
.instruction_o (instruction),
.stall_i (stall_macro_deco),
.stall_o (stall_instr_fetch),
.compressed_ready_i(compressed_ready_i),
.compressed_resp_i (compressed_resp_i),
.compressed_valid_o(compressed_valid_o),
.compressed_req_o (compressed_req_o)
);
end else if (CVA6Cfg.RVZCMT) begin
zcmt_decoder #(
.CVA6Cfg(CVA6Cfg),
.dcache_req_i_t(dcache_req_i_t),
Expand All @@ -205,19 +178,24 @@ module id_stage #(
.is_zcmt_instr_i(is_zcmt_instr_i[0]),
.clk_i (clk_i),
.rst_ni (rst_ni),
.instr_o (instruction_cvxif[0]),
.instr_o (instruction_cvxif_zcmt[0]),
.illegal_instr_i(is_illegal[0]),
.is_compressed_i(is_compressed[0]),
.issue_ack_i (issue_instr_ack_i[0]),
.illegal_instr_o(is_illegal_cvxif[0]),
.is_compressed_o(is_compressed_cvxif[0]),
.fetch_stall_o (stall_macro_deco),
.illegal_instr_o(is_illegal_cvxif_zcmt[0]),
.is_compressed_o(is_compressed_cvxif_zcmt[0]),
.fetch_stall_o (stall_macro_deco_zcmt),
.jvt_base_i (jvt_base_i),
.jvt_mode_i (jvt_mode_i),
.is_zcmt_o (is_zcmt),
.req_port_i (dcache_req_ports_i),
.req_port_o (dcache_req_ports_o)
);

assign instruction_cvxif[0] = is_zcmt_instr_i[0] ? instruction_cvxif_zcmt[0] : instruction_cvxif_zcmp[0];
assign is_illegal_cvxif[0] = is_zcmt_instr_i[0] ? is_illegal_cvxif_zcmt[0]: is_illegal_cvxif_zcmp[0];
assign is_compressed_cvxif[0] = is_zcmt_instr_i[0] ? is_compressed_cvxif_zcmt[0]: is_compressed_cvxif_zcmp[0];
assign stall_macro_deco = is_zcmt_instr_i[0] ? stall_macro_deco_zcmt: stall_macro_deco_zcmp;
if (CVA6Cfg.SuperscalarEn) begin
assign instruction_cvxif[CVA6Cfg.NrIssuePorts-1] = '0;
assign is_illegal_cvxif[CVA6Cfg.NrIssuePorts-1] = '0;
Expand Down
2 changes: 1 addition & 1 deletion core/include/cv32a60x_config_pkg.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,7 @@ package cva6_config_pkg;
RVH: bit'(0),
RVZCMT: bit'(1),
RVZCB: bit'(1),
RVZCMP: bit'(0),
RVZCMP: bit'(1),
XFVec: bit'(0),
CvxifEn: bit'(1),
RVZiCond: bit'(0),
Expand Down
57 changes: 21 additions & 36 deletions core/zcmt_decoder.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@ module zcmt_decoder #(
input logic illegal_instr_i, // From compressed decoder
input logic is_compressed_i, // is compressed instruction
input logic issue_ack_i, // Check if the intruction is acknowledged
input logic [CVA6Cfg.XLEN-1:6] jvt_base_i, // JVT CSR base
input logic [CVA6Cfg.XLEN-6:0] jvt_base_i, // JVT CSR base
input logic [5:0] jvt_mode_i, // JVT CSR mode
input dcache_req_o_t req_port_i, // Data cache request ouput - CACHE

Expand Down Expand Up @@ -74,22 +74,12 @@ module zcmt_decoder #(
end else if (instr_i[9:2] >= 32 & instr_i[9:2] <= 32) begin //JALT instruction
zcmt_instr_type = JALT;
index = instr_i[9:2];
end else begin
zcmt_instr_type = NOT_ZCMT; //NOT ZCMT instruction
illegal_instr_o = 1'b1;
instr_o_reg = instr_i;
end
end
end
end
end
end
end
end
end
end
end else begin
zcmt_instr_type = NOT_ZCMT; //NOT ZCMT instruction
illegal_instr_o = 1'b1;
instr_o_reg = instr_i;
end
end
end
default: begin
illegal_instr_o = 1'b1;
instr_o_reg = instr_i;
Expand All @@ -108,13 +98,13 @@ module zcmt_decoder #(
end else begin
state_d = IDLE;
end
end
end
REQ_SENT: begin
state_d = TABLE_FETCH;
case (zcmt_instr_type)
JT: begin
if (CVA6Cfg.XLEN == 32) begin
jvt_table_add = {jvt_base_i[31:6], 6'b000000};
jvt_table_add = {jvt_base_i, 6'b000000};
table_address = jvt_table_add + (index << 2);
table_a = {2'b00, table_address[CVA6Cfg.XLEN-1:0]};
req_port_o.address_index = table_a[9:0];
Expand All @@ -130,9 +120,9 @@ module zcmt_decoder #(
req_port_o.tag_valid = 1;

end else if (CVA6Cfg.XLEN == 64) begin
jvt_table_add = {jvt_base_i[31:6], 6'b000000};
table_address = jvt_table_add + (index << 3);
table_a = {2'b00, table_address[CVA6Cfg.XLEN-1:0]};
//jvt_table_add = {jvt_base_i, 6'b000000};
//table_address = jvt_table_add + (index << 3);
//table_a = {2'b00, table_address[CVA6Cfg.XLEN-1:0]};
// will will completed in future( for 64 bit embedded core)
illegal_instr_o = 1'b1;
end else begin
Expand All @@ -142,7 +132,7 @@ module zcmt_decoder #(
end
JALT: begin
if (CVA6Cfg.XLEN == 32) begin
jvt_table_add = {jvt_base_i[31:6], 6'b000000};
jvt_table_add = {jvt_base_i, 6'b000000};
table_address = jvt_table_add + (index << 2);
table_a = {2'b00, table_address[CVA6Cfg.XLEN-1:0]};
req_port_o.address_index = table_a[9:0];
Expand All @@ -158,9 +148,9 @@ module zcmt_decoder #(
req_port_o.tag_valid = 1;

end else if (CVA6Cfg.XLEN == 64) begin
jvt_table_add = {jvt_base_i[31:6], 6'b000000};
table_address = jvt_table_add + (index << 3);
table_a = {2'b00, table_address[CVA6Cfg.XLEN-1:0]};
//jvt_table_add = {jvt_base_i, 6'b000000};
//table_address = jvt_table_add + (index << 3);
//table_a = {2'b00, table_address[CVA6Cfg.XLEN-1:0]};
// will will completed in future( for 64 bit embedded core)
illegal_instr_o = 1'b1;
end else begin
Expand All @@ -170,16 +160,15 @@ module zcmt_decoder #(
end
default: state_d = IDLE;
endcase
end
end
TABLE_FETCH: begin
if (req_port_i.data_rid & req_port_i.data_rvalid) begin
data_rdata_d = req_port_i.data_rdata;
state_d = JUMP;
end else begin
state_d = TABLE_FETCH;
end
end
end
end
JUMP: begin
if (issue_ack_i) begin

Expand All @@ -191,19 +180,20 @@ module zcmt_decoder #(
}; //- jal pc_offset, x0
end else if (zcmt_instr_type == JALT) begin
instr_o_reg = {
jump_add[20], jump_add[10:1], jump_add[11], jump_add[19:12], 5'h1, riscv::OpcodeJal
jump_add[20], jump_add[10:1], jump_add[11], jump_add[19:12], 5'h1, riscv::OpcodeJal
};
end

is_zcmt_o = 1'b1;
fetch_stall_o = 1'b0;
state_d = IDLE;
end else begin
state_d = JUMP;
end
end
default: begin
state_d = IDLE;
end
end
endcase
end

Expand All @@ -212,14 +202,9 @@ module zcmt_decoder #(
state_q <= IDLE;
data_rdata_q <= '0;

end else begin
end else begin
state_q <= state_d;
data_rdata_q <= data_rdata_d;

end
end
end
end
end
end
endmodule

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