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Fix missing parametrization in performance counters (openhwgroup#2740)
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ricted98 authored Jan 26, 2025
1 parent 3ebb510 commit fb4a8d4
Showing 1 changed file with 3 additions and 3 deletions.
6 changes: 3 additions & 3 deletions core/perf_counters.sv
Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@ module perf_counters
input logic rst_ni,
input logic debug_mode_i, // debug mode
// SRAM like interface
input logic [11:0] addr_i, // read/write address (up to 6 counters possible)
input logic [11:0] addr_i, // read/write address (up to ariane_pkg::MHPMCounterNum counters possible)
input logic we_i, // write enable
input logic [CVA6Cfg.XLEN-1:0] data_i, // data to write
output logic [CVA6Cfg.XLEN-1:0] data_o, // data to read
Expand Down Expand Up @@ -68,7 +68,7 @@ module perf_counters
//internal signal to keep track of exception
logic read_access_exception, update_access_exception;

logic events[6:1];
logic events[MHPMCounterNum:1];
//internal signal for MUX select line input
logic [4:0] mhpmevent_d[MHPMCounterNum:1];
logic [4:0] mhpmevent_q[MHPMCounterNum:1];
Expand Down Expand Up @@ -146,7 +146,7 @@ module perf_counters
update_access_exception = 1'b0;

// Increment the non-inhibited counters with active events
for (int unsigned i = 1; i <= 6; i++) begin
for (int unsigned i = 1; i <= MHPMCounterNum; i++) begin
if ((!debug_mode_i) && (!we_i)) begin
if ((events[i]) == 1 && (!mcountinhibit_i[i+2])) begin
generic_counter_d[i] = generic_counter_q[i] + 1'b1;
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