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__enable/disable_fiq is forbidden on Cortex-M since IAR 9.40.1. #102

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merged 1 commit into from
Dec 4, 2023
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__enable/disable_fiq is forbidden on Cortex-M since IAR 9.40.1. #102

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25 changes: 21 additions & 4 deletions CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h
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Original file line number Diff line number Diff line change
Expand Up @@ -314,14 +314,25 @@ __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {

#include "iccarm_builtin.h"

#define __disable_fault_irq __iar_builtin_disable_fiq
#define __disable_irq __iar_builtin_disable_interrupt
#define __enable_fault_irq __iar_builtin_enable_fiq
#define __enable_irq __iar_builtin_enable_interrupt
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr


#if (defined(__ARM_ARCH_ISA_THUMB) && __ARM_ARCH_ISA_THUMB >= 2)
__IAR_FT void __disable_fault_irq()
{
__ASM volatile ("CPSID F" ::: "memory");
}

__IAR_FT void __enable_fault_irq()
{
__ASM volatile ("CPSIE F" ::: "memory");
}
#endif


#define __get_APSR() (__arm_rsr("APSR"))
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
#define __get_CONTROL() (__arm_rsr("CONTROL"))
Expand Down Expand Up @@ -648,9 +659,15 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
}

__IAR_FT void __disable_fault_irq()
{
__ASM volatile ("CPSID F" ::: "memory");
}

#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
__IAR_FT void __enable_fault_irq()
{
__ASM volatile ("CPSIE F" ::: "memory");
}


#endif /* (__CORTEX_M >= 0x03) */
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