Merge pull request #6

sync trunk
AXERA-TECH · Feb 6, 2025 · 0c3b0dc · 0c3b0dc
2 parents a0a32a9 + 32fefd7
commit 0c3b0dc
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diff --git a/README.md b/README.md
@@ -6,7 +6,7 @@
 
 ## Overview
 
-**pyAXCL**基于[AXCL](https://axcl-docs.readthedocs.io/zh-cn/latest/) 驱动上实现的  Python API，支持开发板和M.2算力卡形态。
+**pyAXCL**基于[AXCL](https://axcl-docs.readthedocs.io/zh-cn/latest/) 驱动上实现的python API，支持开发板和M.2算力卡形态。
 
 <img src="https://axcl-docs.readthedocs.io/zh-cn/latest/_images/axcl_architecture.svg" style="zoom:80%;" />
 

diff --git a/axcl/ax_codec_comm.py b/axcl/ax_codec_comm.py
@@ -36,9 +36,9 @@
 
 
 AX_AAC_TRANS_TYPE_E = c_int32
-AX_AAC_TRANS_TYPE_UNKNOWN = -1, # Unknown format.
-AX_AAC_TRANS_TYPE_RAW = 0,      # "as is" access units (packet based since there is obviously no sync layer)
-AX_AAC_TRANS_TYPE_ADTS = 2,     # ADTS bitstream format.
+AX_AAC_TRANS_TYPE_UNKNOWN = -1
+AX_AAC_TRANS_TYPE_RAW = 0
+AX_AAC_TRANS_TYPE_ADTS = 2
 AX_AAC_TRANS_TYPE_BUTT = 3
 
 

diff --git a/sample/memory/sample_memory.py b/sample/memory/sample_memory.py
@@ -17,11 +17,6 @@
 from ctypes import memset
 
 
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 BASE_DIR = os.path.dirname(os.path.abspath(__file__))
 sys.path.append(BASE_DIR + '/..')
 sys.path.append(BASE_DIR + '/../..')