Single_Cycle_RISCV_CPU

This is a cycle RSICV CPU that implements 30 instructions in RV32I

Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
ALU_Decoder.sv		ALU_Decoder.sv
Control_unit_top.sv		Control_unit_top.sv
Main_Decoder.sv		Main_Decoder.sv
PC_Adder.sv		PC_Adder.sv
README.md		README.md
Reg_file.sv		Reg_file.sv
Single_cycle_cpu.vcd.gtkw		Single_cycle_cpu.vcd.gtkw
alu.sv		alu.sv
command.txt		command.txt
data_mem.sv		data_mem.sv
dump.vcd		dump.vcd
instr_mem.sv		instr_mem.sv
mux2x1.sv		mux2x1.sv
mux4x1.sv		mux4x1.sv
out.vvp		out.vvp
pc.sv		pc.sv
sign_extend.sv		sign_extend.sv
single_cycle_tb.sv		single_cycle_tb.sv
single_cycle_top.sv		single_cycle_top.sv
waveform.png		waveform.png

Provide feedback