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revision 2.0
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AnterCreeper committed Oct 22, 2023
1 parent a6e333a commit 67189a3
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36 changes: 21 additions & 15 deletions test_audio_rtl/src/dac.cst
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Expand Up @@ -5,38 +5,44 @@
//Part Number: GW1NR-LV9QN88PC6/I5
//Device: GW1NR-9
//Device Version: C
//Created Time: Fri 05 12 13:46:45 2023
//Created Time: Sun 10 22 23:39:36 2023

IO_LOC "io_i2c_scl" 48;
IO_PORT "io_i2c_scl" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 OPEN_DRAIN=OFF BANK_VCCIO=3.3;
IO_PORT "io_i2c_scl" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=24 OPEN_DRAIN=ON BANK_VCCIO=3.3;
IO_LOC "io_i2s_data" 27;
IO_PORT "io_i2s_data" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=24 BANK_VCCIO=3.3;
IO_PORT "io_i2s_data" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=4 BANK_VCCIO=3.3;
IO_LOC "io_i2s_lrclk" 25;
IO_PORT "io_i2s_lrclk" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=24 BANK_VCCIO=3.3;
IO_PORT "io_i2s_lrclk" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=4 BANK_VCCIO=3.3;
IO_LOC "io_i2s_bclk" 26;
IO_PORT "io_i2s_bclk" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=24 BANK_VCCIO=3.3;
IO_PORT "io_i2s_bclk" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=4 BANK_VCCIO=3.3;
IO_LOC "io_spi_mosi" 37;
IO_PORT "io_spi_mosi" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
IO_LOC "io_spi_clk" 36;
IO_PORT "io_spi_clk" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
IO_LOC "io_spi_cs" 38;
IO_PORT "io_spi_cs" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
IO_LOC "test3" 16;
IO_PORT "test3" PULL_MODE=NONE DRIVE=4 BANK_VCCIO=1.8;
IO_LOC "test2" 15;
IO_PORT "test2" PULL_MODE=NONE DRIVE=4 BANK_VCCIO=1.8;
IO_LOC "test1" 14;
IO_PORT "test1" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=4 BANK_VCCIO=1.8;
IO_LOC "irq_s" 16;
IO_PORT "irq_s" PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "irq_n" 15;
IO_PORT "irq_n" PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "idle" 14;
IO_PORT "idle" PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "valid" 13;
IO_PORT "valid" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=4 BANK_VCCIO=1.8;
IO_PORT "valid" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "done" 11;
IO_PORT "done" PULL_MODE=NONE DRIVE=4 BANK_VCCIO=1.8;
IO_PORT "done" PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "busy" 10;
IO_PORT "busy" PULL_MODE=NONE DRIVE=4 BANK_VCCIO=1.8;
IO_PORT "busy" PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "io_i2c_sda" 49;
IO_PORT "io_i2c_sda" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 OPEN_DRAIN=OFF BANK_VCCIO=3.3;
IO_PORT "io_i2c_sda" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=24 OPEN_DRAIN=ON BANK_VCCIO=3.3;
IO_LOC "io_spi_miso" 39;
IO_PORT "io_spi_miso" IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
IO_LOC "msel" 63;
IO_PORT "msel" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
IO_LOC "btn_n" 86;
IO_PORT "btn_n" PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "btn_s" 85;
IO_PORT "btn_s" PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "iclk" 35;
IO_PORT "iclk" IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
IO_LOC "clk_27" 52;
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17 changes: 17 additions & 0 deletions test_audio_rtl/src/gowin_sdpb/gowin_sdpb.ipc
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[General]
ipc_version=4
file=gowin_sdpb
module=Gowin_SDPB
target_device=gw1nr9c-004
type=ram_sdpb
version=1.0

[Config]
BYTE_SIZE=0
DEPTH_A=512
DEPTH_B=128
LANG=0
READ=0
RESET_MODE=true
WIDTH_A=8
WIDTH_B=32
19 changes: 19 additions & 0 deletions test_audio_rtl/src/gowin_sdpb/gowin_sdpb.mod
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-series GW1NR
-device GW1NR-9
-device_version C
-package QFN88P
-part_number GW1NR-LV9QN88PC6/I5


-mod_name Gowin_SDPB
-file_name gowin_sdpb
-path /home/lenovo/gowin/project/dac/src/gowin_sdpb/
-type RAM_SDP
-file_type vlg
-bram_b true
-depth_0 512
-depth_1 128
-width_0 8
-width_1 32
-read_mode bypass
-reset_mode sync
51 changes: 51 additions & 0 deletions test_audio_rtl/src/gowin_sdpb/gowin_sdpb.v
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//Copyright (C)2014-2023 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: IP file
//GOWIN Version: V1.9.8.11 Education
//Part Number: GW1NR-LV9QN88PC6/I5
//Device: GW1NR-9
//Device Version: C
//Created Time: Sat Oct 14 12:27:58 2023

module Gowin_SDPB (dout, clka, cea, reseta, clkb, ceb, resetb, oce, ada, din, adb);

output [31:0] dout;
input clka;
input cea;
input reseta;
input clkb;
input ceb;
input resetb;
input oce;
input [8:0] ada;
input [7:0] din;
input [6:0] adb;

wire gw_gnd;

assign gw_gnd = 1'b0;

SDPB sdpb_inst_0 (
.DO({dout[31:24],dout[23:16],dout[15:8],dout[7:0]}),
.CLKA(clka),
.CEA(cea),
.RESETA(reseta),
.CLKB(clkb),
.CEB(ceb),
.RESETB(resetb),
.OCE(oce),
.BLKSELA({gw_gnd,gw_gnd,gw_gnd}),
.BLKSELB({gw_gnd,gw_gnd,gw_gnd}),
.ADA({gw_gnd,gw_gnd,ada[8:0],gw_gnd,gw_gnd,gw_gnd}),
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[7:0]}),
.ADB({gw_gnd,gw_gnd,adb[6:0],gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd})
);

defparam sdpb_inst_0.READ_MODE = 1'b0;
defparam sdpb_inst_0.BIT_WIDTH_0 = 8;
defparam sdpb_inst_0.BIT_WIDTH_1 = 32;
defparam sdpb_inst_0.BLK_SEL_0 = 3'b000;
defparam sdpb_inst_0.BLK_SEL_1 = 3'b000;
defparam sdpb_inst_0.RESET_MODE = "SYNC";

endmodule //Gowin_SDPB
27 changes: 27 additions & 0 deletions test_audio_rtl/src/gowin_sdpb/gowin_sdpb_tmp.v
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//Copyright (C)2014-2023 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: Template file for instantiation
//GOWIN Version: V1.9.8.11 Education
//Part Number: GW1NR-LV9QN88PC6/I5
//Device: GW1NR-9
//Device Version: C
//Created Time: Sat Oct 14 12:27:58 2023

//Change the instance name and port connections to the signal names
//--------Copy here to design--------

Gowin_SDPB your_instance_name(
.dout(dout_o), //output [31:0] dout
.clka(clka_i), //input clka
.cea(cea_i), //input cea
.reseta(reseta_i), //input reseta
.clkb(clkb_i), //input clkb
.ceb(ceb_i), //input ceb
.resetb(resetb_i), //input resetb
.oce(oce_i), //input oce
.ada(ada_i), //input [8:0] ada
.din(din_i), //input [7:0] din
.adb(adb_i) //input [6:0] adb
);

//--------Copy end-------------------
2 changes: 1 addition & 1 deletion test_audio_rtl/src/i2c_hci.v
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Expand Up @@ -103,7 +103,7 @@ begin
end
end

always
always @(*)
begin
case(LUT_INDEX)
// Config Data
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