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Multi edge diving issue
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@Asma-Mohsin
Asma-Mohsin committed Nov 12, 2024
1 parent e8ca557 commit 659984c
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Showing 6 changed files with 217 additions and 22 deletions.
Binary file added verilog/rtl/.cvxif_pau.v.swp
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Binary file added verilog/rtl/.summer_school_mpd_wrapper.v.swp
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91 changes: 91 additions & 0 deletions verilog/rtl/piso.v.skip
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module piso #(
parameter WIDTH = 8 // Parameter to define the bit width
)(
input wire clk1, // Clock signal
input wire clk2,
input wire rst, // Reset signal
input wire load, // Load signal to load parallel data
input wire [WIDTH-1:0] parallel_in, // Parallel input data
output wire serial_out // Serial output
);

genvar i;
reg [WIDTH-1:0] shift_reg;

generate
for (i = WIDTH-1; i > 0; i = i - 1) begin : piso_bits
// Master-slave latch pair for each bit (excluding the first bit)
MasterSlaveLatch msl (
.clk1(clk1),
.clk2(clk2),
.rst(rst),
.d(load ? parallel_in[i] : shift_reg[i-1]), // Load or shift data
.q(shift_reg[i])
);
end
endgenerate

// First latch in the chain (handle the 0th bit)
MasterSlaveLatch msl0 (
.clk1(clk1),
.clk2(clk2),
.rst(rst),
.d(load ? parallel_in[0] : 1'b0), // Load or shift in 0
.q(shift_reg[0])
);

// Serial output is the last bit of the shift register
assign serial_out = shift_reg[WIDTH-1];

endmodule

// Master-Slave latch with synchronous reset
module MasterSlaveLatch(
input wire clk1,
input wire clk2,
input wire rst,
input wire d,
output wire q
);

wire master_q, slave_q;

// Master latch: Transparent when clk is low
Latch master (
.enable(clk1), // Master latch is enabled when clk is low
.rst(rst),
.d(d),
.q(master_q)
);

// Slave latch: Transparent when clk is high
Latch slave (
.enable(clk2), // Slave latch is enabled when clk is high
.rst(rst),
.d(master_q),
.q(slave_q)
);

// Output of the slave latch is the output of the master-slave pair
assign q = slave_q;

endmodule

// Simple latch module with reset
module Latch(
input wire enable,
input wire rst,
input wire d,
output reg q
);

always @(*) begin
if (rst) begin
q <= 1'b0; // Reset the latch
end else if (enable) begin
q <= d; // Capture input when enabled
end
end

endmodule

103 changes: 103 additions & 0 deletions verilog/rtl/sipo.v.skip
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module sipo #(
parameter WIDTH = 8 // Parameter to define the bit width
)(
input wire clk1, // Clock signal
input wire clk2,
input wire rst, // Reset signal
input wire serial_in, // Serial input
input wire load, // Load the output
output wire [WIDTH-1:0] parallel_out // Parameterized parallel output
);

genvar i;
wire [WIDTH-1:0] shift_reg;
reg [WIDTH-1:0] parallel_shadow;

generate
for (i = 0; i < WIDTH; i = i + 1) begin : sipo_bits
if (i == 0) begin
// First master-slave latch pair receives the serial input
MasterSlaveLatch msl (
.clk1(clk1),
.clk2(clk2),
.rst(rst),
.d(serial_in),
.q(shift_reg[i])
);
end else begin
// Each subsequent master-slave latch pair takes the output of the previous stage
MasterSlaveLatch msl (
.clk1(clk1),
.clk2(clk2),
.rst(rst),
.d(shift_reg[i-1]),
.q(shift_reg[i])
);
end
end
endgenerate

// Connect the shift register to the output
assign parallel_shadow = shift_reg;
always @(clk) begin
if(rst) parallel_shadow <= {WIDTH{1'b0}}
else begin
if (load) begin
parallel_out <= parallel_shadow;
end
end

end

endmodule

// Master-Slave latch with synchronous reset
module MasterSlaveLatch(
input wire clk1,
input wire clk2,
input wire rst,
input wire d,
output wire q
);

wire master_q, slave_q;

// Master latch: Transparent when clk is low
Latch master (
.enable(clk1), // Master latch is enabled when clk is low
.rst(rst),
.d(d),
.q(master_q)
);

// Slave latch: Transparent when clk is high
Latch slave (
.enable(clk2), // Slave latch is enabled when clk is high
.rst(rst),
.d(master_q),
.q(slave_q)
);

// Output of the slave latch is the output of the master-slave pair
assign q = slave_q;

endmodule

// Simple latch module with reset
module Latch(
input wire enable,
input wire rst,
input wire d,
output reg q
);

always @(*) begin
if (rst) begin
q <= 1'b0; // Reset the latch
end else if (enable) begin
q <= d; // Capture input when enabled
end
end

endmodule

42 changes: 21 additions & 21 deletions verilog/rtl/summer_school_mpd_wrapper.v
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@@ -1,4 +1,4 @@
`timescale 1ns / 1ps `timescale 1ns / 1ps
`timescale 1ns / 1ps


module summer_school_top_wrapper #(
Expand Down Expand Up @@ -295,26 +295,26 @@ module summer_school_top_wrapper #(

// LA
1'b1: begin
//inputs
// if (la_oenb[101:1]) begin
// issue_req_instr = la_data_in[101:70];
// issue_valid = la_data_in[69];
// register_valid = la_data_in[68];
// register_rs[1] = la_data_in[67:36];
// register_rs[0] = la_data_in[35:4];
// register_rs_valid = la_data_in[3:2];
// result_ready = la_data_in[1];
//
//
// end else begin
// la_data_out[39] = issue_ready;
// la_data_out[38] = issue_resp_accept;
// la_data_out[37] = issue_resp_writeback;
// la_data_out[36:35] = issue_resp_register_read;
// la_data_out[34] = register_ready;
// la_data_out[33] = result_valid;
// la_data_out[32:1] = result_data;
// end
// inputs
if (& la_oenb[101:1]) begin
issue_req_instr = la_data_in[101:70];
issue_valid = la_data_in[69];
register_valid = la_data_in[68];
register_rs[1] = la_data_in[67:36];
register_rs[0] = la_data_in[35:4];
register_rs_valid = la_data_in[3:2];
result_ready = la_data_in[1];


end else begin
la_data_out[39] = issue_ready;
la_data_out[38] = issue_resp_accept;
la_data_out[37] = issue_resp_writeback;
la_data_out[36:35] = issue_resp_register_read;
la_data_out[34] = register_ready;
la_data_out[33] = result_valid;
la_data_out[32:1] = result_data;
end
end

// eFPGA
Expand Down
3 changes: 2 additions & 1 deletion verilog/rtl/uprj_netlists.v
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Expand Up @@ -17,7 +17,7 @@
// Include caravel global defines for the number of the user project IO pads
`include "defines.v"
`define USE_POWER_PINS

/*
`ifdef GL
// Assume default net type to be wire because GL netlists don't have the wire definitions
`default_nettype wire
Expand All @@ -27,3 +27,4 @@
`include "user_project_wrapper.v"
`include "summer_school_mpd_wrapper.v"
`endif
*/

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