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Fix more linter usses
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Original file line number | Diff line number | Diff line change |
---|---|---|
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@@ -15,3 +15,4 @@ | |
/venv-cocotb | ||
/verilog/dv/cocotb/design_info.yaml | ||
*.swp | ||
lint.log |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,3 @@ | ||
#!/bin/bash | ||
|
||
verilator --lint-only -Wall --Wno-DECLFILENAME --top-module summer_school_top_wrapper /home/jart/fpga-ignite/FPGA_IGNITE_2024/openlane/test_IP/../../verilog/rtl/defines.v /home/jart/fpga-ignite/FPGA_IGNITE_2024/openlane/test_IP/../../verilog/rtl/*.v /home/jart/fpga-ignite/FPGA_IGNITE_2024/openlane/test_IP/../../verilog/rtl/cvxif_pau.v /home/jart/fpga-ignite/FPGA_IGNITE_2024/openlane/test_IP/../../verilog/rtl/Tile/N_term_single/*.v /home/jart/fpga-ignite/FPGA_IGNITE_2024/openlane/test_IP/../../verilog/rtl/Tile/N_term_RAM_IO/*.v /home/jart/fpga-ignite/FPGA_IGNITE_2024/openlane/test_IP/../../verilog/rtl/Tile/LUT4AB/*.v /home/jart/fpga-ignite/FPGA_IGNITE_2024/openlane/test_IP/../../verilog/rtl/Tile/RAM_IO/*.v /home/jart/fpga-ignite/FPGA_IGNITE_2024/openlane/test_IP/../../verilog/rtl/Tile/S_term_single/*.v /home/jart/fpga-ignite/FPGA_IGNITE_2024/openlane/test_IP/../../verilog/rtl/Tile/S_term_RAM_IO/*.v /home/jart/fpga-ignite/FPGA_IGNITE_2024/openlane/test_IP/../../verilog/rtl/Tile/W_IO/*.v /home/jart/fpga-ignite/FPGA_IGNITE_2024/openlane/test_IP/../../verilog/rtl/Tile/*.v -Wno-fatal --relative-includes > lint.log 2>&1 |
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