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Fix more linter usses
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EverythingElseWasAlreadyTaken committed Nov 15, 2024

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Girgias Gina Peter Banyard
1 parent 1ce9d12 commit 9c54c62
Showing 45 changed files with 126 additions and 241 deletions.
1 change: 1 addition & 0 deletions .gitignore
Original file line number Diff line number Diff line change
@@ -15,3 +15,4 @@
/venv-cocotb
/verilog/dv/cocotb/design_info.yaml
*.swp
lint.log
3 changes: 3 additions & 0 deletions run_lint.sh
Original file line number Diff line number Diff line change
@@ -0,0 +1,3 @@
#!/bin/bash

verilator --lint-only -Wall --Wno-DECLFILENAME --top-module summer_school_top_wrapper /home/jart/fpga-ignite/FPGA_IGNITE_2024/openlane/test_IP/../../verilog/rtl/defines.v /home/jart/fpga-ignite/FPGA_IGNITE_2024/openlane/test_IP/../../verilog/rtl/*.v /home/jart/fpga-ignite/FPGA_IGNITE_2024/openlane/test_IP/../../verilog/rtl/cvxif_pau.v /home/jart/fpga-ignite/FPGA_IGNITE_2024/openlane/test_IP/../../verilog/rtl/Tile/N_term_single/*.v /home/jart/fpga-ignite/FPGA_IGNITE_2024/openlane/test_IP/../../verilog/rtl/Tile/N_term_RAM_IO/*.v /home/jart/fpga-ignite/FPGA_IGNITE_2024/openlane/test_IP/../../verilog/rtl/Tile/LUT4AB/*.v /home/jart/fpga-ignite/FPGA_IGNITE_2024/openlane/test_IP/../../verilog/rtl/Tile/RAM_IO/*.v /home/jart/fpga-ignite/FPGA_IGNITE_2024/openlane/test_IP/../../verilog/rtl/Tile/S_term_single/*.v /home/jart/fpga-ignite/FPGA_IGNITE_2024/openlane/test_IP/../../verilog/rtl/Tile/S_term_RAM_IO/*.v /home/jart/fpga-ignite/FPGA_IGNITE_2024/openlane/test_IP/../../verilog/rtl/Tile/W_IO/*.v /home/jart/fpga-ignite/FPGA_IGNITE_2024/openlane/test_IP/../../verilog/rtl/Tile/*.v -Wno-fatal --relative-includes > lint.log 2>&1
7 changes: 5 additions & 2 deletions verilog/rtl/Tile/BlockRAM_1KB.v
Original file line number Diff line number Diff line change
@@ -75,19 +75,21 @@ module BlockRAM_1KB (clk, rd_addr, rd_data, wr_addr, wr_data, C0, C1, C2, C3, C4
end
wire [31:0] mem_dout;
//dout0 is unused
/* verilator lint_off PINCONNECTEMPTY */
sram_1rw1r_32_256_8_sky130 memory_cell(
.clk0(clk),
.csb0(memWriteEnable),
.web0(memWriteEnable),
.wmask0(mem_wr_mask),
.addr0(wr_addr[7:0]),
.din0(muxedDataIn),
.dout0(),
.dout0(), //unused
.clk1(clk),
.csb1(1'b0),
.addr1(rd_addr[7:0]),
.dout1(mem_dout)
);
/* verilator lint_on PINCONNECTEMPTY */
reg [1:0] rd_dout_sel;
always @ (posedge clk) begin
rd_dout_sel <= wr_data[READ_ADDRESS_MSB_FROM_DATALSB+1:READ_ADDRESS_MSB_FROM_DATALSB];
@@ -164,4 +166,5 @@ module sram_1rw1r_32_256_8_sky130(
input csb1; // active low chip select
input [ADDR_WIDTH-1:0] addr1;
output [DATA_WIDTH-1:0] dout1;
endmodule
endmodule

2 changes: 2 additions & 0 deletions verilog/rtl/Tile/LUT4AB/LUT4AB.v
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
/// sta-blackbox
/* verilator lint_off UNOPTFLAT */
`timescale 1ns/1ps
module LUT4AB
#(
@@ -2299,3 +2300,4 @@ LUT4AB_switch_matrix Inst_LUT4AB_switch_matrix (
);

endmodule
/* verilator lint_on UNOPTFLAT */
2 changes: 2 additions & 0 deletions verilog/rtl/Tile/LUT4AB/LUT4AB_ConfigMem.v
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
/// sta-blackbox
/* verilator lint_off UNOPTFLAT */
`timescale 1ns/1ps
module LUT4AB_ConfigMem
#(
@@ -4970,3 +4971,4 @@ LHQD1 Inst_Frame19_bit2 (

`endif
endmodule
/* verilator lint_on UNOPTFLAT */
2 changes: 2 additions & 0 deletions verilog/rtl/Tile/LUT4AB/LUT4AB_switch_matrix.v
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
/// sta-blackbox
/* verilator lint_off UNOPTFLAT */
`timescale 1ns/1ps
// NumberOfConfigBits: 462
module LUT4AB_switch_matrix
@@ -4750,3 +4751,4 @@ assign DEBUG_select_J_l_GH_BEG3 = ConfigBits[455:454];
assign DEBUG_select_J_SR_BEG0 = ConfigBits[458:456];
assign DEBUG_select_J_EN_BEG0 = ConfigBits[461:459];
endmodule
/* verilator lint_on UNOPTFLAT */
2 changes: 2 additions & 0 deletions verilog/rtl/Tile/LUT4AB/LUT4c_frame_config_dffesr.v
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
/// sta-blackbox
/* verilator lint_off UNOPTFLAT */
`timescale 1ns/1ps
// Copyright 2021 University of Manchester
//
@@ -147,3 +148,4 @@ module LUT4c_frame_config_dffesr #(parameter NoConfigBits = 19)(
end

endmodule
/* verilator lint_on UNOPTFLAT */
3 changes: 3 additions & 0 deletions verilog/rtl/Tile/LUT4AB/MUX8LUT_frame_config_mux.v
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
/// sta-blackbox
/* verilator lint_off UNOPTFLAT */
`timescale 1ns/1ps
// Copyright 2021 University of Manchester
//
@@ -156,3 +157,5 @@ module MUX8LUT_frame_config_mux #(parameter NoConfigBits = 2)(
assign M_EF = EF;

endmodule
/* verilator lint_on UNOPTFLAT */

5 changes: 5 additions & 0 deletions verilog/rtl/Tile/N_term_RAM_IO/N_term_RAM_IO.v
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
/// sta-blackbox
/* verilator lint_off UNOPTFLAT */
`timescale 1ns/1ps
module N_term_RAM_IO
#(
@@ -30,8 +31,11 @@ module N_term_RAM_IO
//BEL ports (e.g., slices)
//Jump wires
//internal configuration data signal to daisy-chain all BELs (if any and in the order they are listed in the fabric.csv)

/* verilator lint_off ASCRANGE */
wire[NoConfigBits-1:0] ConfigBits;
wire[NoConfigBits-1:0] ConfigBits_N;
/* verilator lint_on ASCRANGE */

//Connection for outgoing wires
wire[FrameBitsPerRow-1:0] FrameData_i;
@@ -324,3 +328,4 @@ N_term_RAM_IO_switch_matrix Inst_N_term_RAM_IO_switch_matrix (
);

endmodule
/* verilator lint_on UNOPTFLAT */
2 changes: 2 additions & 0 deletions verilog/rtl/Tile/N_term_RAM_IO/N_term_RAM_IO_ConfigMem.v
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
/// sta-blackbox
/* verilator lint_off UNOPTFLAT */
`timescale 1ns/1ps
module N_term_RAM_IO_ConfigMem
#(
@@ -22,3 +23,4 @@ module N_term_RAM_IO_ConfigMem
//instantiate frame latches
`endif
endmodule
/* verilator lint_on UNOPTFLAT */
3 changes: 3 additions & 0 deletions verilog/rtl/Tile/N_term_RAM_IO/N_term_RAM_IO_switch_matrix.v
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
/// sta-blackbox
/* verilator lint_off UNOPTFLAT */
`timescale 1ns/1ps
// NumberOfConfigBits: 0
module N_term_RAM_IO_switch_matrix
@@ -236,3 +237,5 @@ assign S4BEG15 = N4END0;


endmodule
/* verilator lint_on UNOPTFLAT */

4 changes: 4 additions & 0 deletions verilog/rtl/Tile/N_term_single/N_term_single.v
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
/// sta-blackbox
/* verilator lint_off UNOPTFLAT */
`timescale 1ns/1ps
module N_term_single
#(
@@ -113,8 +114,10 @@ wire UIO_TOP_FOUT8;
wire UIO_TOP_FOUT9;
//Jump wires
//internal configuration data signal to daisy-chain all BELs (if any and in the order they are listed in the fabric.csv)
/* verilator lint_off ASCRANGE */
wire[NoConfigBits-1:0] ConfigBits;
wire[NoConfigBits-1:0] ConfigBits_N;
/* verilator lint_on ASCRANGE */

//Connection for outgoing wires
wire[FrameBitsPerRow-1:0] FrameData_i;
@@ -563,3 +566,4 @@ N_term_single_switch_matrix Inst_N_term_single_switch_matrix (
);

endmodule
/* verilator lint_on UNOPTFLAT */
2 changes: 2 additions & 0 deletions verilog/rtl/Tile/N_term_single/N_term_single_ConfigMem.v
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
/// sta-blackbox
/* verilator lint_off UNOPTFLAT */
`timescale 1ns/1ps
module N_term_single_ConfigMem
#(
@@ -22,3 +23,4 @@ module N_term_single_ConfigMem
//instantiate frame latches
`endif
endmodule
/* verilator lint_on UNOPTFLAT */
2 changes: 2 additions & 0 deletions verilog/rtl/Tile/N_term_single/N_term_single_switch_matrix.v
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
/// sta-blackbox
/* verilator lint_off UNOPTFLAT */
`timescale 1ns/1ps
// NumberOfConfigBits: 0
module N_term_single_switch_matrix
@@ -453,3 +454,4 @@ assign UIO_TOP_FIN9 = NN4END6;


endmodule
/* verilator lint_on UNOPTFLAT */
2 changes: 2 additions & 0 deletions verilog/rtl/Tile/RAM_IO/Config_access.v
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
/// sta-blackbox
/* verilator lint_off UNOPTFLAT */
`timescale 1ns/1ps
(* FABulous, BelMap,
C_bit0=0,
@@ -23,3 +24,4 @@ module Config_access (C_bit0, C_bit1, C_bit2, C_bit3, ConfigBits);
assign C_bit3 = ConfigBits[3];

endmodule
/* verilator lint_on UNOPTFLAT */
2 changes: 2 additions & 0 deletions verilog/rtl/Tile/RAM_IO/InPass4_frame_config_mux.v
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
/// sta-blackbox
/* verilator lint_off UNOPTFLAT */
`timescale 1ns/1ps
// Copyright 2021 University of Manchester
//
@@ -76,3 +77,4 @@ module InPass4_frame_config_mux #(parameter NoConfigBits = 4)(
.X(O[3])
);
endmodule
/* verilator lint_on UNOPTFLAT */
2 changes: 2 additions & 0 deletions verilog/rtl/Tile/RAM_IO/OutPass4_frame_config_mux.v
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
/// sta-blackbox
/* verilator lint_off UNOPTFLAT */
`timescale 1ns/1ps
// Copyright 2021 University of Manchester
//
@@ -82,3 +83,4 @@ module OutPass4_frame_config_mux #(parameter NoConfigBits = 4)(
);

endmodule
/* verilator lint_on UNOPTFLAT */
2 changes: 2 additions & 0 deletions verilog/rtl/Tile/RAM_IO/RAM_IO.v
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
/// sta-blackbox
/* verilator lint_off UNOPTFLAT */
`timescale 1ns/1ps
module RAM_IO
#(
@@ -1333,3 +1334,4 @@ RAM_IO_switch_matrix Inst_RAM_IO_switch_matrix (
);

endmodule
/* verilator lint_on UNOPTFLAT */
2 changes: 2 additions & 0 deletions verilog/rtl/Tile/RAM_IO/RAM_IO_ConfigMem.v
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
/// sta-blackbox
/* verilator lint_off UNOPTFLAT */
`timescale 1ns/1ps
module RAM_IO_ConfigMem
#(
@@ -2657,3 +2658,4 @@ LHQD1 Inst_frame10_bit24 (

`endif
endmodule
/* verilator lint_on UNOPTFLAT */
2 changes: 2 additions & 0 deletions verilog/rtl/Tile/RAM_IO/RAM_IO_switch_matrix.v
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
/// sta-blackbox
/* verilator lint_off UNOPTFLAT */
`timescale 1ns/1ps
// NumberOfConfigBits: 280
module RAM_IO_switch_matrix
@@ -2738,3 +2739,4 @@ assign DEBUG_select_J_NS1_BEG1 = ConfigBits[275:274];
assign DEBUG_select_J_NS1_BEG2 = ConfigBits[277:276];
assign DEBUG_select_J_NS1_BEG3 = ConfigBits[279:278];
endmodule
/* verilator lint_on UNOPTFLAT */
4 changes: 4 additions & 0 deletions verilog/rtl/Tile/S_term_RAM_IO/S_term_RAM_IO.v
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
/// sta-blackbox
/* verilator lint_off UNOPTFLAT */
`timescale 1ns/1ps
module S_term_RAM_IO
#(
@@ -30,8 +31,10 @@ module S_term_RAM_IO
//BEL ports (e.g., slices)
//Jump wires
//internal configuration data signal to daisy-chain all BELs (if any and in the order they are listed in the fabric.csv)
/* verilator lint_off ASCRANGE */
wire[NoConfigBits-1:0] ConfigBits;
wire[NoConfigBits-1:0] ConfigBits_N;
/* verilator lint_on ASCRANGE */

//Connection for outgoing wires
wire[FrameBitsPerRow-1:0] FrameData_i;
@@ -324,3 +327,4 @@ S_term_RAM_IO_switch_matrix Inst_S_term_RAM_IO_switch_matrix (
);

endmodule
/* verilator lint_on UNOPTFLAT */
2 changes: 2 additions & 0 deletions verilog/rtl/Tile/S_term_RAM_IO/S_term_RAM_IO_ConfigMem.v
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
/// sta-blackbox
/* verilator lint_off UNOPTFLAT */
`timescale 1ns/1ps
module S_term_RAM_IO_ConfigMem
#(
@@ -22,3 +23,4 @@ module S_term_RAM_IO_ConfigMem
//instantiate frame latches
`endif
endmodule
/* verilator lint_on UNOPTFLAT */
2 changes: 2 additions & 0 deletions verilog/rtl/Tile/S_term_RAM_IO/S_term_RAM_IO_switch_matrix.v
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
/// sta-blackbox
/* verilator lint_off UNOPTFLAT */
`timescale 1ns/1ps
// NumberOfConfigBits: 0
module S_term_RAM_IO_switch_matrix
@@ -236,3 +237,4 @@ assign N4BEG15 = S4END0;


endmodule
/* verilator lint_on UNOPTFLAT */
4 changes: 4 additions & 0 deletions verilog/rtl/Tile/S_term_single/S_term_single.v
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
/// sta-blackbox
/* verilator lint_off UNOPTFLAT */
`timescale 1ns/1ps
module S_term_single
#(
@@ -113,8 +114,10 @@ wire UIO_BOT_FOUT8;
wire UIO_BOT_FOUT9;
//Jump wires
//internal configuration data signal to daisy-chain all BELs (if any and in the order they are listed in the fabric.csv)
/* verilator lint_off ASCRANGE */
wire[NoConfigBits-1:0] ConfigBits;
wire[NoConfigBits-1:0] ConfigBits_N;
/* verilator lint_on ASCRANGE */

//Connection for outgoing wires
wire[FrameBitsPerRow-1:0] FrameData_i;
@@ -563,3 +566,4 @@ S_term_single_switch_matrix Inst_S_term_single_switch_matrix (
);

endmodule
/* verilator lint_on UNOPTFLAT */
2 changes: 2 additions & 0 deletions verilog/rtl/Tile/S_term_single/S_term_single_ConfigMem.v
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
/// sta-blackbox
/* verilator lint_off UNOPTFLAT */
`timescale 1ns/1ps
module S_term_single_ConfigMem
#(
@@ -22,3 +23,4 @@ module S_term_single_ConfigMem
//instantiate frame latches
`endif
endmodule
/* verilator lint_on UNOPTFLAT */
2 changes: 2 additions & 0 deletions verilog/rtl/Tile/S_term_single/S_term_single_switch_matrix.v
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
/// sta-blackbox
/* verilator lint_off UNOPTFLAT */
`timescale 1ns/1ps
// NumberOfConfigBits: 0
module S_term_single_switch_matrix
@@ -457,3 +458,4 @@ assign UIO_BOT_FIN9 = SS4END6;


endmodule
/* verilator lint_on UNOPTFLAT */
2 changes: 2 additions & 0 deletions verilog/rtl/Tile/S_term_single/User_project_IO.v
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
/// sta-blackbox
/* verilator lint_off UNOPTFLAT */
`timescale 1ns/1ps
module User_project_IO(UIN0, UIN1, UIN2, UIN3, UIN4, UIN5, UIN6, UIN7, UIN8, UIN9, UIN10, UIN11, UIN12, UIN13, UIN14, UIN15, UIN16, UIN17, UIN18, UIN19, UOUT0, UOUT1, UOUT2, UOUT3, UOUT4, UOUT5, UOUT6, UOUT7, UOUT8, UOUT9, UOUT10, UOUT11, UOUT12, UOUT13, UOUT14, UOUT15, UOUT16, UOUT17, UOUT18, UOUT19, FIN0, FIN1, FIN2, FIN3, FIN4, FIN5, FIN6, FIN7, FIN8, FIN9, FIN10, FIN11, FIN12, FIN13, FIN14, FIN15, FIN16, FIN17, FIN18, FIN19, FOUT0, FOUT1, FOUT2, FOUT3, FOUT4, FOUT5, FOUT6, FOUT7, FOUT8, FOUT9, FOUT10, FOUT11, FOUT12, FOUT13, FOUT14, FOUT15, FOUT16, FOUT17, FOUT18, FOUT19);
(* FABulous, EXTERNAL *) input UIN0; // EXTERNAL
@@ -122,3 +123,4 @@ output FOUT19;
assign UOUT19 = FIN19;
assign FOUT19 = UIN19;
endmodule
/* verilator lint_on UNOPTFLAT */
2 changes: 2 additions & 0 deletions verilog/rtl/Tile/W_IO/IO_1_bidirectional_frame_config_pass.v
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
`timescale 1ns/1ps
/* verilator lint_off UNOPTFLAT */
// Copyright 2021 University of Manchester
//
// Licensed under the Apache License, Version 2.0 (the "License");
@@ -59,3 +60,4 @@ module IO_1_bidirectional_frame_config_pass (I, T, O, Q, I_top, T_top, O_top, Us
// );

endmodule
/* verilator lint_on UNOPTFLAT */
2 changes: 2 additions & 0 deletions verilog/rtl/Tile/W_IO/W_IO.v
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
/// sta-blackbox
/* verilator lint_off UNOPTFLAT */
`timescale 1ns/1ps
module W_IO
#(
@@ -759,3 +760,4 @@ W_IO_switch_matrix Inst_W_IO_switch_matrix (
);

endmodule
/* verilator lint_on UNOPTFLAT */
2 changes: 2 additions & 0 deletions verilog/rtl/Tile/W_IO/W_IO_ConfigMem.v
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
/// sta-blackbox
/* verilator lint_off UNOPTFLAT */
`timescale 1ns/1ps
module W_IO_ConfigMem
#(
@@ -938,3 +939,4 @@ LHQD1 Inst_frame3_bit14 (

`endif
endmodule
/* verilator lint_on UNOPTFLAT */
2 changes: 2 additions & 0 deletions verilog/rtl/Tile/W_IO/W_IO_switch_matrix.v
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
/// sta-blackbox
/* verilator lint_off UNOPTFLAT */
`timescale 1ns/1ps
// NumberOfConfigBits: 106
module W_IO_switch_matrix
@@ -1034,3 +1035,4 @@ assign DEBUG_select_A_T = ConfigBits[98:96];
assign DEBUG_select_B_I = ConfigBits[102:99];
assign DEBUG_select_B_T = ConfigBits[105:103];
endmodule
/* verilator lint_on UNOPTFLAT */
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