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Merge pull request #20 from Asma-Mohsin/fix/remove_met_5_from_term_tiles
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Replace Posit macro by flat implementation
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@Asma-Mohsin
Asma-Mohsin authored Nov 23, 2024
2 parents 4442c08 + 5e922fc commit c911ddd
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Showing 25 changed files with 1,047 additions and 50 deletions.
18 changes: 8 additions & 10 deletions openlane/flat_BRAM/config.json
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Expand Up @@ -4,8 +4,12 @@
"VERILOG_FILES": [
"dir::../../verilog/rtl/defines.v",
"dir::../../verilog/rtl/*.v",
"dir::../../verilog/rtl/Tile/*.v"

"dir::../../verilog/rtl/Tile/*.v",
"dir::../../verilog/rtl/posit/*.v",
"dir::../../verilog/rtl/posit/pau/*.v",
"dir::../../verilog/rtl/posit/pau/add/*.v",
"dir::../../verilog/rtl/posit/pau/div/*.v",
"dir::../../verilog/rtl/posit/pau/mult/*.v"
],
"CLOCK_PERIOD": 40,
"CLOCK_PORT": "wb_clk_i",
Expand Down Expand Up @@ -33,7 +37,6 @@
"dir::../../verilog/rtl/Tile/S_term_single/*.v",
"dir::../../verilog/rtl/Tile/S_term_RAM_IO/*.v",
"dir::../../verilog/rtl/Tile/W_IO/*.v"

],
"ROUTING_CORES": 10,
"FP_TAP_HORIZONTAL_HALO": 50,
Expand All @@ -49,7 +52,6 @@
"FP_PDN_CORE_RING_VWIDTH": 3.1,
"FP_PDN_ENABLE_GLOBAL_CONNECTIONS": 1,
"FP_PDN_MACRO_HOOKS": [
"cvxif_pau_inst vccd1 vssd1 vccd1 vssd1,",
"flexbex_eFPGA.data_mem_i vccd1 vssd1 vccd1 vssd1,",
"flexbex_eFPGA.eFPGA_top_i.eFPGA_inst.Tile_X1Y0_N_term_single vccd1 vssd1 vccd1 vssd1,",
"flexbex_eFPGA.eFPGA_top_i.eFPGA_inst.Tile_X2Y0_N_term_single vccd1 vssd1 vccd1 vssd1,",
Expand Down Expand Up @@ -134,19 +136,15 @@
"flexbex_eFPGA.eFPGA_top_i.Inst_BlockRAM_2.memory_cell vccd1 vssd1 vccd1 vssd1"
],
"EXTRA_LEFS": [
"dir::../../lef/cvxif_pau.lef",
"dir::./macros/lef/*.lef"
],
"EXTRA_GDS_FILES": [
"dir::../../gds/cvxif_pau.gds",
"dir::./macros/gds/*.gds"
],
"EXTRA_LIBS": [
"dir::../../lib/cvxif_pau.lib",
"dir::./macros/lib/*.lib"
],

"RUN_IRDROP_REPORT" : 1,
"RUN_IRDROP_REPORT": 1,
"FP_PDN_MULTILAYER": true,
"SYNTH_POWER_DEFINE": "USE_POWER_PINS",
"PDK": "sky130A",
Expand All @@ -160,7 +158,7 @@
"MACRO_PLACEMENT_CFG": "dir::macro_final_test.cfg",
"MAX_TRANSITION_CONSTRAINT": 1.0,
"MAX_FANOUT_CONSTRAINT": 16,
"RUN_LINTER": 0,
"RUN_LINTER": 1,
"PL_RESIZER_SETUP_SLACK_MARGIN": 0.4,
"GLB_RESIZER_SETUP_SLACK_MARGIN": 0.2,
"GLB_RESIZER_HOLD_SLACK_MARGIN": 0.2,
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1 change: 0 additions & 1 deletion openlane/flat_BRAM/macro.cfg
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@@ -1,4 +1,3 @@
cvxif_pau_inst 2716.313 100.0 N
flexbex_eFPGA.data_mem_i 50.0 2062.0 N
flexbex_eFPGA.eFPGA_top_i.eFPGA_inst.Tile_X1Y0_N_term_single 578.0 348.0 N
flexbex_eFPGA.eFPGA_top_i.eFPGA_inst.Tile_X2Y0_N_term_single 578.0 603.0 N
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33 changes: 0 additions & 33 deletions verilog/rtl/black_box_modules/cvxif_pau.v
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This file was deleted.

168 changes: 168 additions & 0 deletions verilog/rtl/posit/cvxif_pau.v
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module cvxif_pau (
clk,
rst,
issue_valid,
issue_ready,
issue_req_instr,
issue_resp_accept,
issue_resp_writeback,
issue_resp_register_read,
register_valid,
register_ready,
register_rs0,
register_rs1,
register_rs_valid,
result_valid,
result_ready,
result_data
);
input clk;
input rst;
input issue_valid;
output reg issue_ready;
input [31:0] issue_req_instr;
output reg issue_resp_accept;
output wire issue_resp_writeback;
output reg [1:0] issue_resp_register_read;
input register_valid;
output wire register_ready;
input [31:0] register_rs0;
input [31:0] register_rs1;
input [1:0] register_rs_valid;
output reg result_valid;
input result_ready;
output reg [31:0] result_data;
localparam COUNTER_LEN = 2;
localparam PAU_WAIT_TIME = 3;
localparam PAU_N = 16;
localparam PAU_ES = 1;
reg [2:0] op;
reg [2:0] next_op;
reg [15:0] a;
reg [15:0] b;
reg [15:0] next_a;
reg [15:0] next_b;
wire [15:0] c_add;
wire [15:0] c_mul;
wire [15:0] c_div;
reg start;
wire done_add;
wire done_mul;
wire done_div;
reg [1:0] pau_wait_counter;
reg [1:0] next_pau_wait_counter;
reg add_i;
reg add_z;
reg mul_i;
reg mul_z;
reg div_i;
reg div_z;
posit_add #(
.N(PAU_N),
.es(PAU_ES)
) u_posit_add(
.in1(a),
.in2(b),
.start(start),
.out(c_add),
.inf(add_i),
.zero(add_z),
.done(done_add)
);
posit_mult #(
.N(PAU_N),
.es(PAU_ES)
) u_posit_mult(
.in1(a),
.in2(b),
.start(start),
.out(c_mul),
.inf(mul_i),
.zero(mul_z),
.done(done_mul)
);
posit_div #(
.N(PAU_N),
.es(PAU_ES)
) u_posit_div(
.in1(a),
.in2(b),
.start(start),
.out(c_div),
.inf(div_i),
.zero(div_z),
.done(done_div)
);
localparam ADD_OP = 3'b000;
localparam SUB_OP = 3'b001;
localparam MUL_OP = 3'b010;
localparam DIV_OP = 3'b011;
wire match_instruction;
assign match_instruction = ((issue_req_instr[6:0] == 7'b1111011) && (issue_req_instr[31:25] == 7'b0000000)) && ((((issue_req_instr[14:12] == ADD_OP) || (issue_req_instr[14:12] == SUB_OP)) || (issue_req_instr[14:12] == MUL_OP)) || (issue_req_instr[14:12] == DIV_OP));
assign issue_resp_writeback = 1'b1;
wire done;
assign done = (done_add | done_mul) | done_div;
reg [1:0] current_state;
reg [1:0] next_state;
always @(posedge clk)
if (rst) begin
current_state <= 2'd0;
pau_wait_counter <= 0;
result_data <= 0;
end
else begin
current_state <= next_state;
op <= next_op;
a <= next_a;
b <= next_b;
pau_wait_counter <= next_pau_wait_counter;
if ((current_state == 2'd2) && (next_state == 2'd3))
case (issue_req_instr[14:12])
ADD_OP: result_data <= c_add;
SUB_OP: result_data <= c_add;
MUL_OP: result_data <= c_mul;
DIV_OP: result_data <= c_div;
endcase
end
always @(*) begin
next_state = current_state;
next_op = op;
next_a = a;
next_b = b;
next_pau_wait_counter = pau_wait_counter;
issue_ready = 1'b0;
issue_resp_accept = 1'b0;
result_valid = 1'b0;
start = 1'b0;
case (current_state)
2'd0: begin
issue_ready = 1'b1;
if (issue_valid && match_instruction) begin
issue_resp_accept = 1'b1;
next_op = issue_req_instr[14:12];
issue_resp_register_read = 2'b11;
next_state = 2'd1;
end
end
2'd1:
if (register_valid && (register_rs_valid == 2'b11)) begin
next_a = register_rs0[15:0];
next_b = register_rs1[15:0];
next_pau_wait_counter = {COUNTER_LEN {1'b0}};
next_state = 2'd2;
end
2'd2: begin
start = 1'b1;
if (pau_wait_counter < PAU_WAIT_TIME)
next_pau_wait_counter = pau_wait_counter + 1;
else if (done && (pau_wait_counter == PAU_WAIT_TIME))
next_state = 2'd3;
end
2'd3: begin
result_valid = 1'b1;
if (result_ready)
next_state = 2'd0;
end
endcase
end
endmodule
18 changes: 18 additions & 0 deletions verilog/rtl/posit/pau/DSR_left_N_S.v
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module DSR_left_N_S(a,b,c);
parameter N=16;
parameter S=4;
input [N-1:0] a;
input [S-1:0] b;
output [N-1:0] c;

wire [N-1:0] tmp [S-1:0];
assign tmp[0] = b[0] ? a << 7'd1 : a;
genvar i;
generate
for (i=1; i<S; i=i+1)begin:loop_blk
assign tmp[i] = b[i] ? tmp[i-1] << 2**i : tmp[i-1];
end
endgenerate
assign c = tmp[S-1];

endmodule
18 changes: 18 additions & 0 deletions verilog/rtl/posit/pau/DSR_right_N_S.v
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module DSR_right_N_S(a,b,c);
parameter N=16;
parameter S=4;
input [N-1:0] a;
input [S-1:0] b;
output [N-1:0] c;

wire [N-1:0] tmp [S-1:0];
assign tmp[0] = b[0] ? a >> 7'd1 : a;
genvar i;
generate
for (i=1; i<S; i=i+1)begin:loop_blk
assign tmp[i] = b[i] ? tmp[i-1] >> 2**i : tmp[i-1];
end
endgenerate
assign c = tmp[S-1];

endmodule
39 changes: 39 additions & 0 deletions verilog/rtl/posit/pau/LOD.v
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module LOD (in, out, vld);

function [31:0] log2;
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction


parameter N = 64;
parameter S = log2(N);

input [N-1:0] in;
output [S-1:0] out;
output vld;

generate
if (N == 2)
begin
assign vld = |in;
assign out = ~in[1] & in[0];
end
else if (N & (N-1))
//LOD #(1<<S) LOD ({1<<S {1'b0}} | in,out,vld);
LOD #(1<<S) LOD ({in,{((1<<S) - N) {1'b0}}},out,vld);
else
begin
wire [S-2:0] out_l, out_h;
wire out_vl, out_vh;
LOD #(N>>1) l(in[(N>>1)-1:0],out_l,out_vl);
LOD #(N>>1) h(in[N-1:N>>1],out_h,out_vh);
assign vld = out_vl | out_vh;
assign out = out_vh ? {1'b0,out_h} : {out_vl,out_l};
end
endgenerate
endmodule
19 changes: 19 additions & 0 deletions verilog/rtl/posit/pau/LOD_N.v
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module LOD_N (in, out);

function [31:0] log2;
input reg [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction

parameter N = 64;
parameter S = log2(N);
input [N-1:0] in;
output [S-1:0] out;

wire vld;
LOD #(.N(N)) l1 (in, out, vld);
endmodule
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