lvs issues

Asma-Mohsin · Dec 6, 2024 · b6df022 · b6df022
1 parent a19c1c9
commit b6df022
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Showing 62 changed files with 1,230,488 additions and 1,228,972 deletions.
diff --git a/def/DSP.def b/def/DSP.def
diff --git a/gds/DSP.gds.gz b/gds/DSP.gds.gz
diff --git a/lef/DSP.lef b/lef/DSP.lef
diff --git a/lib/DSP.lib b/lib/DSP.lib
diff --git a/mag/DSP.mag b/mag/DSP.mag
diff --git a/maglef/DSP.mag b/maglef/DSP.mag
diff --git a/openlane/DSP/config.json b/openlane/DSP/config.json
@@ -15,13 +15,13 @@
     "GLB_RESIZER_TIMING_OPTIMIZATIONS": 1,
     "//": "seems important",
     "FP_SIZING": "absolute",
-    "DIE_AREA": "0 0 225 454",
+    "DIE_AREA": "0 0 225 455",
     "CLOCK_PERIOD": "40",
     "CLOCK_PORT": "UserCLK",
     "RUN_CTS": 1,
     "CELL_PAD": 4,
     "RUN_LINTER": 0,
-    "GRT_OBS": "met5 0 0 225 454",
+    "GRT_OBS": "met5 0 0 225 455",
     "STD_CELL_LIBRARY": "sky130_fd_sc_hd",
     "PDK": "sky130A",
     "PDK_ROOT": "/home/asma/Desktop/open_eFPGA/dependencies/pdks/",

diff --git a/openlane/DSP/pin_order.cfg b/openlane/DSP/pin_order.cfg
@@ -27,6 +27,7 @@ Tile_X0Y1_UserCLK
 Tile_X0Y1_FrameStrobe\[.*
 
 #E
+$1
 Tile_X0Y1_W1END\[.* 
 Tile_X0Y1_W2MID\[.*
 Tile_X0Y1_W2END\[.*
@@ -50,9 +51,9 @@ Tile_X0Y0_E2BEGb\[.*
 Tile_X0Y0_EE4BEG\[.*
 Tile_X0Y0_E6BEG\[.*
 Tile_X0Y0_FrameData_O\[.*
-$3
 
 #W
+$1
 Tile_X0Y1_W1BEG\[.*
 Tile_X0Y1_W2BEG\[.*
 Tile_X0Y1_W2BEGb\[.*
@@ -76,4 +77,3 @@ Tile_X0Y0_E2END\[.*
 Tile_X0Y0_EE4END\[.*
 Tile_X0Y0_E6END\[.*
 Tile_X0Y0_FrameData\[.*
-$3
diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
@@ -5,12 +5,17 @@
         "dir::../../verilog/rtl/*.v",
         "dir::../../verilog/rtl/Fabric/*.v"
     ],
+
+    "FP_TAP_VERTICAL_HALO": 50,  "//": "no cell placed between IPs",
+    "FP_TAP_HORIZONTAL_HALO": 50, "//": "no cell placed between IPs",
+
+    "PL_TARGET_DENSITY": 0.8,
     "ROUTING_CORES": 10,
     "CLOCK_PERIOD": 40,
     "CLOCK_PORT": "wb_clk_i",
     "CLOCK_NET": "wb_clk_i",
-    "GRT_ALLOW_CONGESTION":0,
-
+    "GRT_ALLOW_CONGESTION":1,
+    "FP_PDN_ENABLE_MACROS_GRID": 1,
     "FP_PDN_MACRO_HOOKS": [
         "eFPGA_top_i.eFPGA_inst.Tile_X0Y1_W_IO vccd1 vssd1 vccd1 vssd1",
         "eFPGA_top_i.eFPGA_inst.Tile_X0Y2_W_IO vccd1 vssd1 vccd1 vssd1",
@@ -157,21 +162,19 @@
         "dir::../../verilog/rtl/BB/*.v",
         "dir::../../verilog/rtl/Tile/*/*.v"
     ],
-    "FP_MACRO_VERTICAL_HALO": 20, "//": "no cell placed between IPs",
-    "FP_MACRO_HORIZONTAL_HALO": 20, "//": "no cell placed between IPs",
-    "FP_PDN_HORIZONTAL_HALO": 25,
-    "FP_PDN_VERTICAL_HALO": 25,
+    "FP_PDN_HORIZONTAL_HALO": 35,
+    "FP_PDN_VERTICAL_HALO": 35,
 
+    "PL_MACRO_HALO": "50 50,",
 
-    "PL_MACRO_HALO": "10 10",
     "EXTRA_LEFS": "dir::macro/lef/*.lef",
     "EXTRA_GDS_FILES": "dir::macro/gds/*.gds",
     "EXTRA_LIBS": "dir::macro/lib/*.lib",
     "BASE_SDC_FILE": "dir::base_user_project_wrapper.sdc",
     "IO_SYNC": 0,
     "MAX_TRANSITION_CONSTRAINT": 1.5,
     "RUN_LINTER": 0,
-    "QUIT_ON_SYNTH_CHECKS": 0,
+    "QUIT_ON_SYNTH_CHECKS": 1,
     "FP_PDN_CHECK_NODES": 0,
     "SYNTH_ELABORATE_ONLY": 0,
     "PL_RANDOM_GLB_PLACEMENT": 0,
@@ -183,12 +186,12 @@
     "FP_PDN_ENABLE_RAILS": 1,
     "GRT_REPAIR_ANTENNAS": 1,
     "RUN_FILL_INSERTION": 1,
-    "RUN_TAP_DECAP_INSERTION": 0,
+    "RUN_TAP_DECAP_INSERTION": 1,
     "FP_PDN_VPITCH": 75,
     "FP_PDN_HPITCH": 75,
     "FP_PDN_VOFFSET": 30,
     "FP_PDN_HOFFSET": 30,
-    "RUN_CTS": 0,
+    "RUN_CTS": 1,
     "MAGIC_ZEROIZE_ORIGIN": 0,
     "FP_SIZING": "absolute",
     "RUN_CVC": 0,

diff --git a/openlane/user_project_wrapper/macro/gds/DSP.gds b/openlane/user_project_wrapper/macro/gds/DSP.gds