initial commit

.gitignore

@@ -11,4 +11,5 @@
 /caravel
 /dependencies
 /mgmt_core_wrapper
-/logs
+/logs
+venv-cocotb

openlane/BRAM/config.json

@@ -0,0 +1,56 @@
+{
+   "DESIGN_NAME": "BlockRAM_1KB",
+   "VERILOG_FILES": [ "dir::./src/BlockRAM_1KB.v"],
+
+   "RUN_LINTER": 0,
+   "SYNTH_MAX_FANOUT": 5,
+   "FP_SIZING": "absolute",
+   "DIE_AREA": "0 0 570 471.23",
+
+   "CLOCK_PERIOD": "40",
+   "CLOCK_PORT": "clk",
+   "CLOCK_TREE_SYNTH": 1,
+   "CELL_PAD": 4,
+
+   "DESIGN_IS_CORE": 0,
+   "FP_PDN_CORE_RING": 0,
+   "GLB_RT_MAXLAYER": 5,
+
+   "SYNTH_NO_FLAT": 1,
+   "SYNTH_FLAT_TOP": 1,
+   "SYNTH_READ_BLACKBOX_LIB": 1,
+
+   "FP_IO_VLENGTH": 0.8,
+   "FP_IO_HLENGTH": 0.8,
+   "FP_IO_HTHICKNESS_MULT": 1,
+   "FP_IO_VTHICKNESS_MULT": 1,
+   "ROUTING_CORES": 12,
+   "TOP_MARGIN_MULT": 2,
+   "BOTTOM_MARGIN_MULT": 2,
+   "FP_IO_MODE": 0,
+   "FP_PIN_ORDER_CFG": ["dir::./pin_order.cfg"],
+   "FP_PDN_MACRO_HOOKS": ["memory_cell  vccd1 vssd1 vccd1 vssd1"],
+
+   "ROUTING_CORES": 12,
+   "VDD_PINS": "vccd1",
+   "GND_PINS": "vssd1",
+   "FP_PDN_VOFFSET": 10,
+   "FP_PDN_VPITCH": 20,
+   "FP_PDN_HPITCH": 60,
+   "FP_PDN_IRDROP": 0,
+   "FP_PDN_CHECK_NODES": 0,
+   "GLB_RT_OBS": "li1 70 35 549 431, met1 70 35 549 431, met2 70 35 549 431, met3 70 35 549 431, met4 70 35 549 431, met5 0 0 570 471.23",
+   "MACRO_PLACEMENT_CFG": [ "dir::./macros/placements/macro_placement.cfg"],
+
+   "FP_PDN_ENABLE_GLOBAL_CONNECTIONS": 1,
+   "VDD_NETS": [
+           "vccd1"
+       ],
+       "GND_NETS": [
+           "vssd1"
+       ],
+
+   "VERILOG_FILES_BLACKBOX": [ "dir::./macros/verilog/sky130_sram_1kbyte_1rw1r_32x256_8.v"],
+   "EXTRA_LEFS": [ "dir::./macros/lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef"],
+   "EXTRA_GDS_FILES": [ "dir::./macros/gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds"]
+}

openlane/BRAM/gate_map.v

@@ -0,0 +1,114 @@
+/*
+module \$_DLATCH_N_ (E, D, Q);
+  //wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
+  input E, D;
+  output Q;
+//  TLATNX1M _TECHMAP_REPLACE_ (
+  sky130_fd_sc_hd__udp_dlatch_p _TECHMAP_REPLACE_ (
+    .D(D),
+    .GATE(E),
+    .Q(Q)
+  );
+endmodule
+
+module \$_DLATCH_P_ (E, D, Q);
+  //wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
+  input E, D;
+  output Q;
+//  TLATNX1M _TECHMAP_REPLACE_ (
+  sky130_fd_sc_hd__udp_dlatch_p _TECHMAP_REPLACE_ (
+    .D(D),
+    .GATE(E),
+    .Q(Q)
+  );
+endmodule
+module \$_DLATCH_N_ (E, D, Q);
+  input E, D;
+  output Q;
+  sky130_fd_sc_hd__dlrtp_1 _TECHMAP_REPLACE_ (
+    .D(D),
+    .GATE(E),
+    .RESET_B(1'b1), //disable reset (active low)
+    .Q(Q)
+  );
+endmodule
+
+module \$_DLATCH_P_ (E, D, Q);
+  input E, D;
+  output Q;
+  sky130_fd_sc_hd__dlrtp_1 _TECHMAP_REPLACE_ (
+    .D(D),
+    .GATE(E),
+    .RESET_B(1'b1), //disable reset (active low)
+    .Q(Q)
+  );
+endmodule
+*/
+
+/*
+module \$_DLATCH_N_ (E, D, Q, QN);
+  input E, D;
+  output Q, QN;
+  sky130_fd_sc_hd__dlxbn_1 _TECHMAP_REPLACE_ (
+    .D(D),
+    .GATE(E),
+    .Q(Q),
+    .Q_N(QN)
+  );
+endmodule
+
+module \$_DLATCH_P_ (E, D, Q, QN);
+  input E, D;
+  output Q, QN;
+  sky130_fd_sc_hd__dlxbp_1 _TECHMAP_REPLACE_ (
+    .D(D),
+    .GATE(E),
+    .Q(Q),
+    .Q_N(QN)
+  );
+endmodule
+*/
+
+module LHQD1 (E, D, Q, QN);
+  input E, D;
+  output Q, QN;
+  sky130_fd_sc_hd__dlxbp_1 _TECHMAP_REPLACE_ (
+    .D(D),
+    .GATE(E),
+    .Q(Q),
+    .Q_N(QN)
+  );
+endmodule
+
+/*
+module cus_mux41_buf (A0, A1, A2, A3, S0, S0N, S1, S1N, X);
+  input A0, A1, A2, A3, S0, S0N, S1, S1N;
+  output X;
+	cus_tg_mux41_buf _TECHMAP_REPLACE_ (
+	.A0 (A0),
+	.A1 (A1),
+	.A2 (A2),
+	.A3 (A3),
+	.S0 (S0),
+	.S0N (S0N),
+	.S1 (S1),
+	.S1N (S1N),
+	.X (X)
+	);
+endmodule
+*/
+module cus_mux41_buf (A0, A1, A2, A3, S0, S0N, S1, S1N, X);
+  input A0, A1, A2, A3, S0, S0N, S1, S1N;
+  output X;
+        sky130_fd_sc_hd__mux4_1 _TECHMAP_REPLACE_ (
+        .A0 (A0),
+        .A1 (A1),
+        .A2 (A2),
+        .A3 (A3),
+        .S0 (S0),
+        //.S0N (S0N),
+        .S1 (S1),
+        //.S1N (S1N),
+        .X (X)
+        );
+endmodule

openlane/BRAM/macros/gds/update_gds.csh

@@ -0,0 +1,11 @@
+#!/bin/csh
+cp ~/SKY130/eFPGA_v2/Innovus/CLB/OUTPUTs/LUT4AB.gds .
+cp ~/SKY130/eFPGA_v2/Innovus/RegFile/OUTPUTs/RegFile.gds .
+cp ~/SKY130/eFPGA_v2/Innovus/W_IO/OUTPUTs/W_IO.gds .
+cp ~/SKY130/eFPGA_v2/Innovus/RAM_IO/OUTPUTs/RAM_IO.gds .
+cp ~/SKY130/eFPGA_v2/Innovus/N_term_single/OUTPUTs/N_term_single.gds .
+cp ~/SKY130/eFPGA_v2/Innovus/N_term_single2/OUTPUTs/N_term_single2.gds .
+cp ~/SKY130/eFPGA_v2/Innovus/N_term_RAM_IO/OUTPUTs/N_term_RAM_IO.gds .
+cp ~/SKY130/eFPGA_v2/Innovus/S_term_RAM_IO/OUTPUTs/S_term_RAM_IO.gds .
+cp ~/SKY130/eFPGA_v2/Innovus/S_term_single2/OUTPUTs/S_term_single2.gds .
+cp ~/SKY130/eFPGA_v2/Innovus/S_term_single/OUTPUTs/S_term_single.gds .