Demonstration of the fully open FABulous eFPGA using the OpenLane flow.
This repo experiments an implementation of an eFPGA from RTL to GDS with open Skywater-130 PDK. The design RTL was generated by FABulous framework. The fabric consists of 672x LUT4s (14x6 CLBs), 56x LUT5s (14x1 RegFiles), 7x DSPs and 7x BRAMs (7x1KB) with dual-ported memory blocks for register files and FIFOs. An embedded UART for configurations and CPU_IO interface (e.g., to RISC-V core) were also implemented in this version.
The fabrics were fully implemented using the OpenLane flow then integrated onto eFabless caravel.
