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HDMI_ALTERA/HDMI.qpf

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+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2020  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+# Date created = 15:38:22  January 10, 2021
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "20.1"
+DATE = "15:38:22  January 10, 2021"
+
+# Revisions
+
+PROJECT_REVISION = "HDMI_Encode"

HDMI_ALTERA/HDMI_Encode.qsf

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+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2020  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+# Date created = 15:38:22  January 10, 2021
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		HDMI_Encode_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE EP4CE6E22C7
+set_global_assignment -name TOP_LEVEL_ENTITY HDMI_Encoder
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:38:22  JANUARY 10, 2021"
+set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_instance_assignment -name IO_STANDARD LVDS_E_3R -to tmds
+set_instance_assignment -name IO_STANDARD LVDS_E_3R -to tmds[3]
+set_instance_assignment -name IO_STANDARD LVDS_E_3R -to tmds[2]
+set_instance_assignment -name IO_STANDARD LVDS_E_3R -to tmds[1]
+set_instance_assignment -name IO_STANDARD LVDS_E_3R -to tmds[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk
+set_location_assignment PIN_23 -to clk
+set_location_assignment PIN_66 -to DE
+set_location_assignment PIN_52 -to tmds[0]
+set_location_assignment PIN_53 -to "tmds[0](n)"
+set_location_assignment PIN_54 -to tmds[1]
+set_location_assignment PIN_55 -to "tmds[1](n)"
+set_location_assignment PIN_59 -to tmds[2]
+set_location_assignment PIN_60 -to "tmds[2](n)"
+set_location_assignment PIN_49 -to tmds[3]
+set_location_assignment PIN_50 -to "tmds[3](n)"
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
+set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH HDMI_test_tb -section_id eda_simulation
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name EDA_TEST_BENCH_NAME HDMI_test_tb -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id HDMI_test_tb
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME HDMI_test_tb -section_id HDMI_test_tb
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_simulation
+set_global_assignment -name EDA_TEST_BENCH_FILE HDMI_Encoder_tb.sv -section_id HDMI_test_tb
+set_global_assignment -name SYSTEMVERILOG_FILE HDMI_Encoder.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/HDMI_PLL.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/hdmi.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/Console/glyphmap.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/Console/console.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/Console/attributemap.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/Audio_Sample/Sine_1KHz_16b_48ksps.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/Audio_Sample/sawtooth.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/tmds_channel.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/source_product_description_info_frame.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/packet_picker.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/packet_assembler.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/auxiliary_video_information_info_frame.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/audio_sample_packet.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/audio_info_frame.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/audio_clock_regeneration_packet.sv
+set_global_assignment -name SDC_FILE HDMI_SDC1.sdc
+set_global_assignment -name SYSTEMVERILOG_FILE HDMI_Encoder_tb.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/HDMI_serializer_altlvds.sv
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

HDMI_ALTERA/HDMI_Encoder.sv

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+module HDMI_Encoder (
+
+	input  logic       clk,
+
+	output logic [3:0] tmds,  // Remember to set your IO standard in Quartus to LVDS or LVDS_E_3R mode.
+
+	output logic       DE     // Data enable for NXP TMDS Amp.
+);
+
+// Video ID Code 1    = 640  x 480  @ 60Hz    - c0=25200  KHz
+// Video ID Code 2    = 720  x 480  @ 59.94Hz - c0=27000  KHz
+// Video ID Code 4    = 1280 x 720  @ 59.94Hz - c0=74250  KHz
+// Video ID Code 34   = 1920 x 1080 @ 29.97Hz - c0=74250  KHz
+// Video ID Code 964  = 1280 x 960  @ 59.94Hz - c0=94500  KHz  4:3  4x VGA 640x480  // Brian Special,  4:3 960p, = 4x VGA640x480 - 94.5MHz
+// Video ID Code 965  = 1280 x 960  @ 60Hz    - c0=108000 KHz  Vesa  1280x960
+// Video ID Code 969  = 1440 x 960  @ 59.94Hz - c0=108000 KHz  16:9 4x 480p 720x480. // Brian Special, 16:9 960p, = 4x 480p - 108MHz
+// Video ID Code 1024 = 1280 x 1024 @ 60Hz    - c0=108000 KHz  Vesa  1280x1024 - 108MHz
+// Video ID Code 1084 = 1920 x 1080 @ 49Hz    - c0=108000 KHz  // Brian Special 1080p49hz super reduced blanking - 108MHz
+//
+// These 2 modes are 'TOO FAST FOR NORMAL PLL SETTINGS' since Quartus tries to run the PLL's core oscilator at 4x since we
+// we have under-scored the source clock frequency to allow Quartus to fully compile the design with the over clocked serial TMDS outputs.
+// A manual forced hand-made PLL configuration sent into a re-configurable PLL with the core at 2x might function.
+//
+// Video ID Code 16   = 1920 x 1080 @ 59.94Hz - c0=148500 KHz
+// Video ID Code 1085 = 1920 x 1080 @ 50Hz    - c0=121500 KHz  // Brian Special 1080p50hz reduced blanking - 121.5MHz
+//
+
+parameter  int VIDEO_ID        = 2    ;
+parameter  int DVI_MODE        = 0      ;
+parameter      VIDEO_REFRESH   = 59.94  ;
+
+// Read instructions inside "HDMI_PLL.sv" for allowable PLL settings and which are best to be used.
+parameter  int  HDPLL_CLK_KHZ_IN        = 50000;     // PLL source clock frequency in KHz.    *** There is a limited selection.  Read instructions inside "HDMI_PLL.sv" for allowable PLL settings.
+parameter  int  HDPLL_PIXEL_KHZ_OUT     = 27000;     // PLL clk_pixel output frequency in KHz *** There is a limited selection.  Read instructions inside "HDMI_PLL.sv" for allowable PLL settings.
+parameter  bit  HDPLL_USE_2_PLLS        = 1'b1 ;     // If the source clock isn't 27MHz and you want an exact pixel clock for every frequency, enabling will 
+parameter  int  HDPLL_TRICK_MBPS        = 0    ;     // 0=disable, set to 640 or 740 to trick Quartus into believing the LVDS is running at that this speed.
+                                                     // Not as safe as using the HDMI_SERTX_INTERNAL_PLL feature in the HDMI_SERTX_altlvds module.
+parameter  int  HDPLL_AUDIO_HZ          = 48000;     // Selects the desired frequency of the clk_audio out & number of pulses per second the audio_ena output strobes.
+parameter  bit  HDPLL_AUDIO_TCK_FLOAT   = 1'b1;      // Does a interpreted sub-clk_pixel division when generating the clk_audio and audio_ena output.
+
+parameter  bit  HDMI_SERTX_INTERNAL_PLL = 0  ;       // When enabled, the altlvds_tx serializer will generate it's own 5x PLL for it's serial transmit clock
+parameter  int  HDMI_SERTX_PIXEL_MBPS   = HDPLL_PIXEL_KHZ_OUT/100 ; // When the INTERNAL_PLL is enabled, this value specifies the pixel clock frequency.
+                                                     // You may underscore the clock frequency to trick quartus into allowing compilation for slower LVDS ports.
+                                                     // IE, use a setting of 740 to allow a Cyclone-7 740mbps LVDS bus compile when using 720p's 742.5mbps.
+
+parameter  bit INV_TMDS0 = 1'b0 ;    // Invert the TMDS channel 0 (IE swaps the +&- pins/output polarity when using a LVDS differential output.) 
+parameter  bit INV_TMDS1 = 1'b0 ;    // Invert the TMDS channel 1 (IE swaps the +&- pins/output polarity when using a LVDS differential output.) 
+parameter  bit INV_TMDS2 = 1'b0 ;    // Invert the TMDS channel 2 (IE swaps the +&- pins/output polarity when using a LVDS differential output.) 
+parameter  bit INV_TMDS3 = 1'b0 ;    // Invert the TMDS channel 3 (IE swaps the +&- pins/output polarity when using a LVDS differential output.) 
+
+
+parameter  int AUDIO_BIT_WIDTH = 16    ;
+localparam int SAMPLE_RATE     = HDPLL_AUDIO_HZ ;
+
+//parameter BIT_WIDTH   = 13 ;  //This is usually pointless in HDL.  The compiler automatically simplifies out/removes unused bits in logic registers.
+//parameter BIT_HEIGHT  = 12 ;  //So long as your specify the minimum required, let the compiler do the work.
+parameter FONT_WIDTH  = 8  ;
+parameter FONT_HEIGHT = 16 ;
+
+
+logic        [15:0] audio_sample_word [1:0] = '{ 16'sd0, 16'sd0 } ;
+logic signed [15:0] sine_1k ;
+
+logic               clk_pixel, clk_pixel_x5, clk_audio, audio_ena;
+
+
+// *********************************************************************************************************
+// *** Read instructions inside "HDMI_PLL.sv" for allowable PLL settings and which are best to be used.  ***
+// *********************************************************************************************************
+HDMI_PLL #( .HDPLL_CLK_KHZ_IN(HDPLL_CLK_KHZ_IN), .HDPLL_PIXEL_KHZ_OUT(HDPLL_PIXEL_KHZ_OUT), .HDPLL_USE_2_PLLS(HDPLL_USE_2_PLLS),
+            .HDPLL_TRICK_MBPS(HDPLL_TRICK_MBPS), .HDPLL_AUDIO_HZ(HDPLL_AUDIO_HZ),           .HDPLL_AUDIO_TCK_FLOAT(HDPLL_AUDIO_TCK_FLOAT)
+) HDMI_PLL( .clk_in(clk),                        .clk_pixel(clk_pixel),                     .clk_audio(clk_audio),
+            .audio_ena(audio_ena),               .clk_pixel_x5(clk_pixel_x5)  );
+// *********************************************************************************************************
+
+
+always_comb DE = 1'b0;
+always_comb audio_sample_word [1:0] = '{ sine_1k, sine_1k } ;
+
+// only use .clk_ena if the .clk is tied to the clk_pixel instead of an audio sample clock.
+Sine_1KHz_16b_48ksps Sine_1k ( .clk(clk_pixel), .clk_ena(audio_ena), .audio(sine_1k) ); 
+
+
+logic [23:0] rgb = 24'd0    ;
+logic [12:0] cx             ; // Maximum of 8191 pixels from left to right, IE frame width of 4400 for 2160p can be done.
+logic [11:0] cy             ; // Maximum of 4095 lines counter for Y counter, IE 2160p which had 2250 lines can be done.
+logic [12:0] screen_start_x ;
+logic [11:0] screen_start_y ;
+logic [12:0] frame_width    ;
+logic [11:0] frame_height   ;
+logic [12:0] screen_width   ;
+logic [11:0] screen_height  ;
+
+hdmi #(
+    .HDMI_SERTX_INTERNAL_PLL (HDMI_SERTX_INTERNAL_PLL), // Set to 1 to activate a dedicated PLL for the altlvds_tc.  Set to 0 and you need to provide the clk_pixel_x5.
+    .HDMI_SERTX_PIXEL_MBPS   (HDMI_SERTX_PIXEL_MBPS),   // Sets the pixel clock frequency for Altera's altlvds_tx serializer megafunction.  Only used when HDMI_SERTX_INTERNAL_PLL is enabled.
+	                                                     // May be used to trick the compiler's maximum mbps, IE claim a slower clock than what the compiler will allow for specific IO standards.
+    .INV_TMDS0         (INV_TMDS0),      // Invert the TMDS channel 0 (IE swaps the +&- pins/output polarity when using a LVDS differential output.) 
+    .INV_TMDS1         (INV_TMDS1),      // Invert the TMDS channel 1 (IE swaps the +&- pins/output polarity when using a LVDS differential output.) 
+    .INV_TMDS2         (INV_TMDS2),      // Invert the TMDS channel 2 (IE swaps the +&- pins/output polarity when using a LVDS differential output.) 
+    .INV_TMDS3         (INV_TMDS3),      // Invert the TMDS channel 3 (IE swaps the +&- pins/output polarity when using a LVDS differential output.) 
+
+	.VIDEO_ID_CODE      (VIDEO_ID),       // Defaults to 640x480 which should be supported by almost if not all HDMI sinks. See README.md or CEA-861-D for enumeration of video id codes.
+	.DVI_OUTPUT         (DVI_MODE),       // Enable this flag for DVI output. Use this to reduce resource usage if you're only outputting video (non-HDMI).
+	.VIDEO_REFRESH_RATE (VIDEO_REFRESH),  // Specify the refresh rate in Hz we're using for audio calculations
+	.AUDIO_RATE         (SAMPLE_RATE),    // As specified in Section 7.3, the minimal audio requirements are met: 16-bit or more L-PCM audio at 32 kHz, 44.1 kHz, or 48 kHz.
+	.AUDIO_BIT_WIDTH    (AUDIO_BIT_WIDTH) // Defaults to minimum bit lengths required to represent positions. Modify these parameters if you have alternate desired bit lengths.
+) hdmi(
+  // inputs
+  .clk_pixel_x5        (clk_pixel_x5),
+  .clk_pixel           (clk_pixel),
+  .clk_audio           (clk_pixel),      // When using the clk_pixel synchronous enable audio sample, clk_audio_ena, place clk_pixel here.
+  .clk_audio_ena       (audio_ena),      // Set this to 1'b1 if you are using a true speed asynchronous clk_audio clock instead of synchronous clk_pixel mode.
+  .rgb                 (rgb),
+  .audio_sample_word   (audio_sample_word),
+  // video outputs
+  .tmds_tx             (tmds),
+  // internal outputs (don't go outside FPGA)
+  .cx                  (cx),
+  .cy                  (cy),
+  .screen_start_x      (screen_start_x),
+  .screen_start_y      (screen_start_y),
+  .frame_width         (frame_width),
+  .frame_height        (frame_height),
+  .screen_width        (screen_width),
+  .screen_height       (screen_height)
+);
+
+//logic [7:0] character = 8'h30 ;
+//logic [5:0] prevcy    = 6'd0  ;
+
+// Border test (left = red, top = green, right = blue, bottom = blue, fill = black)
+always @(posedge clk_pixel) begin
+
+  rgb <= { cx == screen_start_x ? ~8'd0 : 8'd0, cy == screen_start_y ? ~8'd0 : 8'd0, cx == frame_width - 1'd1 || cy == frame_height - 1'd1 ? ~8'd0 : 8'd0 } ;
+/*
+  if (cy == 10'd0)
+  begin
+      character <= 8'h30;
+      prevcy <= 6'd0;
+  end
+  else if (prevcy != cy[9:4])
+  begin
+      character <= character + 8'h01;
+      prevcy <= cy[9:4];
+  end
+*/ 
+end
+
+//console console(.clk_pixel(clk_pixel), .codepoint(character), .attribute({cx[9], cy[8:6], cx[8:5]}), .cx(cx), .cy(cy), .rgb(rgb));
+
+endmodule

HDMI_ALTERA/HDMI_Encoder_tb.sv

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+
+// HDMI_Encoder global testbench
+
+`timescale 1 ps/ 1 ps // 1 picosecond steps, 1 picosecond precision.
+
+
+module HDMI_test_tb();
+logic        clk;
+logic        DE;
+logic  [3:0] tmds;
+
+localparam real CLK_MHz  = 50.000 ;
+localparam real STOP_uS  = 1000000 ;
+
+localparam period  = 500000/CLK_MHz ;
+localparam endtime = STOP_uS * 50;
+
+// assign statements (if any)                          
+HDMI_Encoder DUT(
+// port map - connection between master ports and signals/registers   
+	.clk(clk),
+	.DE(DE),
+	.tmds(tmds)
+);
+
+
+//$add wave -position insertpoint sim:/HDMI_test_tb/DUT/clk_pixel ;
+
+initial 
+begin 
+
+clk = 1'b1;
+//reset = 1'b1;
+#period;
+
+clk = 1'b0;
+//reset = 1'b1;
+#period;
+
+clk = 1'b1;
+//reset = 1'b1;
+#period;
+end 
+
+// clk
+always #period clk = !clk;
+always #endtime $stop;   // Pause the simulation
+
+endmodule

HDMI_ALTERA/HDMI_SDC1.sdc

@@ -0,0 +1,5 @@
+set_time_format -unit ns -decimal_places 3
+create_clock -period 20 clk
+
+derive_pll_clocks
+derive_clock_uncertainty