fixing the bug in the cache hierarchy, issue #52;

src/Cache.cpp

@@ -185,7 +185,9 @@ bool Cache::send(Request req) {
 
     // Send the request to next level;
     if (!is_last_level) {
-      lower_cache->send(req);
+      if(!lower_cache->send(req)) {
+        retry_list.push_back(req);
+      }
     } else {
       cachesys->wait_list.push_back(
           make_pair(cachesys->clk + latency[int(level)], req));
@@ -382,6 +384,18 @@ void Cache::callback(Request& req) {
   }
 }
 
+void Cache::tick() {
+
+    if(!lower_cache->is_last_level)
+        lower_cache->tick();
+
+    for (auto it = retry_list.begin(); it != retry_list.end(); it++) {
+        if(lower_cache->send(*it))
+            it = retry_list.erase(it);
+    }
+
+}
+
 void CacheSystem::tick() {
   debug("clk %ld", clk);
 

src/Cache.h

@@ -53,6 +53,8 @@ class Cache {
   Cache(int size, int assoc, int block_size, int mshr_entry_num,
       Level level, std::shared_ptr<CacheSystem> cachesys);
 
+  void tick();
+
   // L1, L2, L3 accumulated latencies
   int latency[int(Level::MAX)] = {4, 4 + 12, 4 + 12 + 31};
   int latency_each[int(Level::MAX)] = {4, 12, 31};
@@ -81,6 +83,7 @@ class Cache {
   unsigned int tag_offset;
   unsigned int mshr_entry_num;
   std::vector<std::pair<long, std::list<Line>::iterator>> mshr_entries;
+  std::list<Request> retry_list;
 
   std::map<int, std::list<Line> > cache_lines;
 

src/Processor.cpp

@@ -164,6 +164,8 @@ Core::Core(const Config& configs, int coreid,
       caches[0]->concatlower(llc);
     }
     caches[1]->concatlower(caches[0].get());
+
+    first_level_cache = caches[1].get();
   }
   if (no_core_caches) {
     more_reqs = trace.get_filtered_request(
@@ -210,6 +212,9 @@ void Core::tick()
 {
     clk++;
 
+    if(first_level_cache != nullptr)
+        first_level_cache->tick();
+
     retired += window.retire();
 
     if (expected_limit_insts == 0 && !more_reqs) return;

src/Processor.h

@@ -106,6 +106,8 @@ class Core {
     bool more_reqs;
     long last = 0;
 
+    Cache* first_level_cache = nullptr;
+
     ScalarStat memory_access_cycles;
     ScalarStat cpu_inst;
     MemoryBase& memory;