Fixes for running with TestRIG

CTSRD-CHERI · Jan 7, 2025 · 43d6ff7 · 43d6ff7
1 parent a1ce8f9
commit 43d6ff7
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Showing 3 changed files with 11 additions and 6 deletions.
diff --git a/Makefile b/Makefile
@@ -137,6 +137,9 @@ SAIL_ARCH_RVFI_SRCS = \
                  $(SAIL_RISCV_MODEL_DIR)/riscv_types_common.sail \
                  $(SAIL_CHERI_MODEL_DIR)/cheri_riscv_types.sail \
                  $(SAIL_RISCV_MODEL_DIR)/riscv_types.sail \
+                 $(SAIL_RISCV_MODEL_DIR)/riscv_csr_begin.sail \
+                 $(SAIL_RISCV_MODEL_DIR)/riscv_clic_prelude.sail \
+                 $(SAIL_RISCV_MODEL_DIR)/riscv_convert_invalid_addr.sail \
                  $(SAIL_REGS_SRCS) \
                  $(SAIL_SYS_SRCS) \
                  $(SAIL_RISCV_MODEL_DIR)/riscv_platform.sail \
@@ -152,7 +155,9 @@ SAIL_STEP_SRCS = $(SAIL_RISCV_MODEL_DIR)/riscv_step_common.sail \
                  $(SAIL_RISCV_MODEL_DIR)/riscv_step.sail
 
 RVFI_STEP_SRCS = $(SAIL_RISCV_MODEL_DIR)/riscv_step_common.sail \
+                 $(SAIL_CHERI_MODEL_DIR)/cheri_step_ext.sail \
                  $(SAIL_RISCV_MODEL_DIR)/riscv_step_rvfi.sail \
+                 $(SAIL_CHERI_MODEL_DIR)/cheri_execute.sail \
                  $(SAIL_CHERI_MODEL_DIR)/cheri_decode_ext.sail \
                  $(SAIL_RISCV_MODEL_DIR)/riscv_fetch_rvfi.sail \
                  $(SAIL_RISCV_MODEL_DIR)/riscv_step.sail

diff --git a/sail-riscv b/sail-riscv
diff --git a/src/cheri_step_ext.sail b/src/cheri_step_ext.sail
@@ -6,7 +6,7 @@
 /*  SPDX-License-Identifier: BSD-2-Clause                                                */
 /*=======================================================================================*/
 
-function ext_reset() -> unit = {
+function ext_cheri_reset() -> unit = {
   PCC = infinite_cap;
   nextPCC = infinite_cap;
   ddc = infinite_cap;
@@ -64,18 +64,18 @@ function ext_reset() -> unit = {
   x31 = {x31 with tag = false};
 }
 
-function ext_reset_misa() -> unit = {
+function ext_cheri_reset_misa() -> unit = {
   // set misa.X to indicate the presence of a non-standard extension.
   misa[X] = 0b1;
 }
 
-function ext_fetch_hook(f : FetchResult) -> FetchResult = f
+//function ext_fetch_hook(f : FetchResult) -> FetchResult = f
 
 function ext_fetch_mem_read_hi(paddr : xlenbits, pbmt : PBMT) -> MemoryOpResult(half) = mem_read(Execute(), pbmt, paddr, 2, false, false, false)
 function ext_fetch_mem_read_lo(paddr : xlenbits, pbmt : PBMT) -> MemoryOpResult(half) = mem_read(Execute(), pbmt, paddr, 2, false, false, false)
 
-function ext_pre_step_hook()  -> unit = ()
-function ext_post_step_hook() -> unit = ()
+//function ext_pre_step_hook()  -> unit = ()
+//function ext_post_step_hook() -> unit = ()
 
 // Print an instruction we are executing. For CHERI we print the mode too.
 function ext_print_instr forall 'n, 'n in {16, 32} . (