修改性能计数器clock计数逻辑

Ciliphen · May 30, 2024 · 6b420f4 · 6b420f4
1 parent 35281cc
commit 6b420f4
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Showing 2 changed files with 4 additions and 1 deletion.
diff --git a/src/rv_core.hpp b/src/rv_core.hpp
@@ -19,6 +19,7 @@ extern long long bru_pred_fail;
 extern long long bru_pred_fail;
 extern long long dual_issue_cnt;
 extern long long commit_cnt;
+extern long long clock_cnt;
 
 enum alu_op
 {
@@ -125,7 +126,7 @@ class rv_core
                 printf("dcache hit rate: %.2lf\n", 1.0 * dcache_hit / dcache_req * 100);
                 printf("branch predication accuracy: %.2lf\n", (1 - 1.0 * bru_pred_fail / bru_pred_branch) * 100);
                 printf("dual issue rate: %.2lf\n", 1.0 * dual_issue_cnt / commit_cnt * 100);
-                printf("IPC: %.2lf\n", 1.0 * commit_cnt / priv.get_cycle());
+                printf("IPC: %.2lf\n", 1.0 * commit_cnt / clock_cnt);
             }
 
             printf("Test timeout! at pc 0x%lx\n", pc);

diff --git a/src/sim_mycpu.cpp b/src/sim_mycpu.cpp
@@ -30,6 +30,7 @@ long long bru_pred_branch = 0;
 long long bru_pred_fail = 0;
 long long dual_issue_cnt = 0;
 long long commit_cnt = 0;
+long long clock_cnt = 0;
 
 long long current_pc;
 
@@ -559,6 +560,7 @@ void riscv_test_run(Vtop_axi_wrapper *top, axi4_ref<32, 64, 4> &mmio_ref, const
             dcache_hit += top->debug_perf_dcache_hit;
             bru_pred_branch += top->debug_perf_bru_pred_branch;
             bru_pred_fail += top->debug_perf_bru_pred_fail;
+            clock_cnt++;
         }
         commit_cnt += top->debug_commit;
         if (!top->clock && !top->reset)