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Added D2 STRIPE indicator to PCB
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@stuartpittaway
stuartpittaway committed Mar 16, 2021
1 parent e454be6 commit a509988
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2 changes: 1 addition & 1 deletion ModuleV440/ModuleV440.csv
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"Source:","E:\source\diyBMSv4\ModuleV440\ModuleV440.sch"
"Date:","11/03/2021 18:31:06"
"Date:","16/03/2021 13:47:03"
"Tool:","Eeschema (5.1.5)-3"
"Generator:","C:\Program Files\KiCad\bin\scripting\plugins/bom_csv_grouped_by_value.py"
"Component Count:","42"
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37 changes: 20 additions & 17 deletions ModuleV440/ModuleV440.kicad_pcb
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(general
(thickness 1.6)
(drawings 46)
(drawings 47)
(tracks 379)
(zones 0)
(modules 45)
Expand All @@ -12,7 +12,7 @@
(page A4)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(31 B.Cu signal hide)
(32 B.Adhes user hide)
(33 F.Adhes user hide)
(34 B.Paste user hide)
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(descr "JST PH series connector, S2B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator")
(tags "connector JST PH top entry")
(path /5BF5891C)
(fp_text reference RX1 (at 1 -2.55) (layer F.SilkS)
(fp_text reference RX1 (at 1.8 -2.53) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "RX Connector" (at 1 7.45) (layer F.Fab)
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(tags resistor)
(path /5BF1E307)
(attr smd)
(fp_text reference R5 (at -2.625 -0.05) (layer F.SilkS)
(fp_text reference R5 (at -2.675 0.68) (layer F.SilkS)
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(fp_text value 220OHMS (at -3.985 -0.03) (layer F.Fab)
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(tags SOT-23)
(path /5D1FB1C3)
(attr smd)
(fp_text reference D1 (at 1.11 -2.68 180) (layer F.SilkS)
(fp_text reference D1 (at 2.3 1.55 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
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(fp_text value AZ432ANTR-E1 (at 0.08 8.17 180) (layer F.Fab)
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(tags capacitor)
(path /5E5CDAE4)
(attr smd)
(fp_text reference C4 (at -0.975 -1.575) (layer F.SilkS)
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(fp_text value 22pF (at 0.175 -1.645) (layer F.Fab)
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(tags "SMD SMT crystal")
(path /5E5E68B4)
(attr smd)
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(fp_text value "8MHZ Ceramic Resonator" (at 22.6 2.315) (layer F.Fab)
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)
)

(gr_text <STRIPE (at 126.6476 91.7176 90) (layer F.SilkS) (tstamp 6050B62E)
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(gr_text "©2019-2021\nStuart Pittaway" (at 109.6176 87.3376) (layer B.SilkS) (tstamp 5BF98E96)
(effects (font (size 1.2 1.2) (thickness 0.3)) (justify mirror))
)
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(gr_text "DO NOT SHORT CIRCUIT\nDO NOT REVERSE POLARITY\nDO NOT CONNECT RX to RX\nDO NOT CONNECT TX to TX" (at 113.1176 79.0376) (layer B.SilkS) (tstamp 5EA9622B)
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(gr_text "11 Mar 2021" (at 113.0676 49.1626) (layer B.SilkS) (tstamp 5C2BB1AB)
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Expand All @@ -2042,7 +2045,7 @@
(gr_text github.com/stuartpittaway/diyBMSv4 (at 124.8676 71.6876 90) (layer B.SilkS) (tstamp 5BF98EB5)
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(via (at 127.2876 76.0176) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 1) (tstamp 5F8C7E07))
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(via (at 120.0926 96.4326) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 1) (tstamp 6016739B))
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)
)
)
(zone (net 1) (net_name GND) (layer B.Cu) (tstamp 604A4F77) (hatch edge 0.508)
(zone (net 1) (net_name GND) (layer B.Cu) (tstamp 6050BA6A) (hatch edge 0.508)
(connect_pads (clearance 0.508))
(min_thickness 0.254)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.7) (smoothing chamfer) (radius 2))
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)
)
)
(zone (net 1) (net_name GND) (layer F.Cu) (tstamp 604A4F74) (hatch edge 0.508)
(zone (net 1) (net_name GND) (layer F.Cu) (tstamp 6050BA67) (hatch edge 0.508)
(connect_pads (clearance 0.508))
(min_thickness 0.254)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.7) (smoothing chamfer) (radius 2))
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2 changes: 1 addition & 1 deletion ModuleV440/ModuleV440.xml
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<export version="D">
<design>
<source>E:\source\diyBMSv4\ModuleV440\ModuleV440.sch</source>
<date>11/03/2021 18:31:06</date>
<date>16/03/2021 13:47:03</date>
<tool>Eeschema (5.1.5)-3</tool>
<sheet number="1" name="/" tstamps="/">
<title_block>
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