GitHub - DarkForte/MIPS-50_Instructions_Pipelined_CPU: A 5-level pipelined CPU described with Verilog, supports 50 MIPS instructions and interruption

DarkForte / MIPS-50_Instructions_Pipelined_CPU Public

A 5-level pipelined CPU described with Verilog, supports 50 MIPS instructions and interruption

Notifications

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
src		src
流水线测试		流水线测试
.gitattributes		.gitattributes
.gitignore		.gitignore
CodeCombiner.cpp		CodeCombiner.cpp
CodeCombiner.exe		CodeCombiner.exe
P8.cr.mti		P8.cr.mti
P8.mpf		P8.mpf
PIN_Verified - 副本.UCF		PIN_Verified - 副本.UCF
PIN_Verified.ucf		PIN_Verified.ucf
code.txt		code.txt
code_combined.txt		code_combined.txt
code_handler.txt		code_handler.txt
public.v		public.v
test1.asm		test1.asm
test1nocomment.asm		test1nocomment.asm
test2.asm		test2.asm
test2nocomment.asm		test2nocomment.asm
test3.asm		test3.asm
test3nocomment.asm		test3nocomment.asm
test5.asm		test5.asm
test5nocomment.asm		test5nocomment.asm
test6Comment.asm		test6Comment.asm
test6handler.asm		test6handler.asm
test6handlerComment.asm		test6handlerComment.asm
test6nocomment.asm		test6nocomment.asm
test7 - 副本.asm		test7 - 副本.asm
test7.asm		test7.asm
test7handler - 副本.asm		test7handler - 副本.asm
test7handler.asm		test7handler.asm
vsim.wlf		vsim.wlf
中断.txt		中断.txt
流水线控制信号.xlsx		流水线控制信号.xlsx