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Changes for Heads on NovaCustom V560TU #609

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2 changes: 0 additions & 2 deletions Makefile.mk
Original file line number Diff line number Diff line change
Expand Up @@ -227,9 +227,7 @@ ifeq ($(CONFIG_USE_BLOBS),y)
# until expressly requested and enabled with --checkout
forgetthis:=$(shell git submodule update --init --checkout 3rdparty/blobs $(quiet_errors))
forgetthis:=$(shell git submodule update --init --checkout 3rdparty/intel-microcode $(quiet_errors))
ifeq ($(CONFIG_FSP_USE_REPO),y)
forgetthis:=$(shell git submodule update --init --checkout 3rdparty/fsp $(quiet_errors))
endif
ifeq ($(CONFIG_USE_AMD_BLOBS),y)
forgetthis:=$(shell git submodule update --init --checkout 3rdparty/amd_blobs $(quiet_errors))
endif
Expand Down
36 changes: 21 additions & 15 deletions src/lib/jpeg.c
Original file line number Diff line number Diff line change
@@ -1,9 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */

/*
* Provide a simple API around the Wuffs JPEG decoder
* Uses the heap (and lots of it) for the image-size specific
* work buffer, so ramstage-only.
* Provide a simple API around the Wuffs JPEG decoder.
*/

#include <stdint.h>
Expand Down Expand Up @@ -85,6 +83,24 @@ int jpeg_decode(unsigned char *filedata, size_t filesize, unsigned char *pic,
return JPEG_DECODE_FAILED;
}

/* Opting in to lower quality means that we can pass an empty slice as the
* "work buffer" argument to wuffs_jpeg__decoder__decode_frame below.
*
* Decoding progressive (not sequential) JPEGs would still require dynamic
* memory allocation (and the amount of work buffer required depends on the
* image dimensions), but we choose to just reject progressive JPEGs. It is
* simpler than sometimes calling malloc (which can fail, especially for
* large allocations) and free.
*
* More commentary about these quirks is at
* https://github.com/google/wuffs/blob/beaf45650085a16780b5f708b72daaeb1aa865c8/std/jpeg/decode_quirks.wuffs
*/
wuffs_jpeg__decoder__set_quirk(
&dec, WUFFS_BASE__QUIRK_QUALITY,
WUFFS_BASE__QUIRK_QUALITY__VALUE__LOWER_QUALITY);
wuffs_jpeg__decoder__set_quirk(
&dec, WUFFS_JPEG__QUIRK_REJECT_PROGRESSIVE_JPEGS, 1);

wuffs_base__image_config imgcfg;
wuffs_base__io_buffer src = wuffs_base__ptr_u8__reader(filedata, filesize, true);
status = wuffs_jpeg__decoder__decode_image_config(&dec, &imgcfg, &src);
Expand All @@ -104,19 +120,9 @@ int jpeg_decode(unsigned char *filedata, size_t filesize, unsigned char *pic,
return JPEG_DECODE_FAILED;
}

uint64_t workbuf_len_min_incl = wuffs_jpeg__decoder__workbuf_len(&dec).min_incl;
uint8_t *workbuf_array = malloc(workbuf_len_min_incl);
if ((workbuf_array == NULL) && workbuf_len_min_incl) {
return JPEG_DECODE_FAILED;
}

wuffs_base__slice_u8 workbuf =
wuffs_base__make_slice_u8(workbuf_array, workbuf_len_min_incl);
status = wuffs_jpeg__decoder__decode_frame(&dec, &pixbuf, &src,
WUFFS_BASE__PIXEL_BLEND__SRC, workbuf, NULL);

free(workbuf_array);

WUFFS_BASE__PIXEL_BLEND__SRC,
wuffs_base__empty_slice_u8(), NULL);
if (status.repr) {
return JPEG_DECODE_FAILED;
}
Expand Down
8 changes: 8 additions & 0 deletions src/mainboard/clevo/mtl-h/ramstage.c
Original file line number Diff line number Diff line change
Expand Up @@ -201,6 +201,14 @@ static void mainboard_enable(struct device *dev)
#endif
}

void mainboard_update_soc_chip_config(struct soc_intel_meteorlake_config *config)
{
if (get_sleep_type_option() == SLEEP_TYPE_OPTION_S3)
config->s0ix_enable = 0;
else
config->s0ix_enable = 1;
}

struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
.init = mainboard_init,
Expand Down
2 changes: 2 additions & 0 deletions src/mainboard/clevo/mtl-h/romstage.c
Original file line number Diff line number Diff line change
Expand Up @@ -49,5 +49,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
mupd->FspmConfig.DcLoadline[1] = 310;
mupd->FspmConfig.DcLoadline[2] = 490;

mupd->FspmConfig.MmioSize = 2560;

memcfg_init(mupd, &mem_config, &dimm_module_spd_info, half_populated);
}
Binary file modified src/mainboard/clevo/mtl-h/variants/igpu/data.vbt
Binary file not shown.
4 changes: 3 additions & 1 deletion src/soc/intel/alderlake/finalize.c
Original file line number Diff line number Diff line change
Expand Up @@ -84,7 +84,9 @@ static void soc_finalize(void *unused)
printk(BIOS_DEBUG, "Finalizing chipset.\n");

pch_finalize();
apm_control(APM_CNT_FINALIZE);
if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3())
apm_control(APM_CNT_FINALIZE);

tbt_finalize();
if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) &&
CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
Expand Down
4 changes: 3 additions & 1 deletion src/soc/intel/cannonlake/finalize.c
Original file line number Diff line number Diff line change
Expand Up @@ -87,7 +87,9 @@ static void soc_finalize(void *unused)
printk(BIOS_DEBUG, "Finalizing chipset.\n");

pch_finalize();
apm_control(APM_CNT_FINALIZE);
if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3())
apm_control(APM_CNT_FINALIZE);

if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) &&
CONFIG(SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC))
heci1_disable();
Expand Down
27 changes: 26 additions & 1 deletion src/soc/intel/common/block/cse/cse.c
Original file line number Diff line number Diff line change
Expand Up @@ -1437,6 +1437,16 @@ static void cse_set_state(struct device *dev)

printk(BIOS_DEBUG, "CMOS: me_state = %u\n", cmos_me_state);

/*
* Skip action while ME is in debug (HAP) mode, as HECI will not work
* in this state
*/

if (cse_is_hfs1_com_debug()) {
printk(BIOS_DEBUG, "ME is in HAP mode, skipping soft temp disable");
return;
}

/*
* We only take action if the me_state doesn't match the CS(ME) working state
*/
Expand Down Expand Up @@ -1589,9 +1599,24 @@ static void cse_final(struct device *dev)
cse_final_end_of_firmware();
}

#if ENV_RAMSTAGE
static void heci_read_resources(struct device *dev)
{
/* Read standard PCI resources. */
pci_dev_read_resources(dev);

if (ENV_X86_32) {
/* Put resource below 4G to ensure coreboot can access it */
struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
res->limit = 0xffffffff;
res->flags &= ~IORESOURCE_ABOVE_4G;
}
}
#endif

struct device_operations cse_ops = {
.set_resources = pci_dev_set_resources,
.read_resources = pci_dev_read_resources,
.read_resources = heci_read_resources,
.enable_resources = pci_dev_enable_resources,
.init = pci_dev_init,
.ops_pci = &pci_dev_ops_pci,
Expand Down
7 changes: 7 additions & 0 deletions src/soc/intel/common/block/graphics/graphics.c
Original file line number Diff line number Diff line change
Expand Up @@ -278,6 +278,13 @@ static void graphics_dev_read_resources(struct device *dev)
pci_dev_set_resources(dev);
res_bar0->flags |= IORESOURCE_FIXED;
}

if (ENV_X86_32) {
/* Place framebuffer below 4G to ensure coreboot can access it */
struct resource *res_bar2 = find_resource(dev, PCI_BASE_ADDRESS_2);
res_bar2->limit = 0xffffffff;
res_bar2->flags &= ~IORESOURCE_ABOVE_4G;
}
}

static void graphics_join_mbus(void)
Expand Down
15 changes: 14 additions & 1 deletion src/soc/intel/common/block/i2c/i2c.c
Original file line number Diff line number Diff line change
Expand Up @@ -134,6 +134,19 @@ uintptr_t dw_i2c_base_address(unsigned int bus)
return (uintptr_t)ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), 16);
}

static void dw_i2c_read_resources(struct device *dev)
{
/* Read standard PCI resources. */
pci_dev_read_resources(dev);

if (ENV_X86_32) {
/* Put resource below 4G to ensure coreboot can access it */
struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
res->limit = 0xffffffff;
res->flags &= ~IORESOURCE_ABOVE_4G;
}
}

/*
* This function ensures that the device is actually out of reset and
* its ready for initialization sequence.
Expand Down Expand Up @@ -161,7 +174,7 @@ static void dw_i2c_device_init(struct device *dev)
}

struct device_operations i2c_dev_ops = {
.read_resources = pci_dev_read_resources,
.read_resources = dw_i2c_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.scan_bus = scan_static_bus,
Expand Down
4 changes: 4 additions & 0 deletions src/soc/intel/common/block/lpc/Makefile.mk
Original file line number Diff line number Diff line change
Expand Up @@ -5,3 +5,7 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c

ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc.c

ifeq ($(CONFIG_SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM),y)
smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c
endif
10 changes: 10 additions & 0 deletions src/soc/intel/common/block/smm/smihandler.c
Original file line number Diff line number Diff line change
Expand Up @@ -15,12 +15,14 @@
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <elog.h>
#include <intelblocks/cfg.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/oc_wdt.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/smihandler.h>
#include <intelblocks/tco.h>
#include <intelblocks/uart.h>
#include <intelpch/lockdown.h>
#include <smmstore.h>
#include <soc/nvs.h>
#include <soc/pci_devs.h>
Expand Down Expand Up @@ -347,6 +349,14 @@ static void finalize(void)
}
finalize_done = 1;

if (CONFIG(SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM)) {
/* SPI lock down configuration */
fast_spi_lockdown_bios(CHIPSET_LOCKDOWN_COREBOOT);

/* LPC/eSPI lock down configuration */
lpc_lockdown_config(CHIPSET_LOCKDOWN_COREBOOT);
}

if (CONFIG(SPI_FLASH_SMM))
/* Re-init SPI driver to handle locked BAR */
fast_spi_init();
Expand Down
3 changes: 3 additions & 0 deletions src/soc/intel/common/pch/include/intelpch/lockdown.h
Original file line number Diff line number Diff line change
Expand Up @@ -22,4 +22,7 @@ int get_lockdown_config(void);
*/
void soc_lockdown_config(int chipset_lockdown);

void fast_spi_lockdown_bios(int chipset_lockdown);
void lpc_lockdown_config(int chipset_lockdown);

#endif /* SOC_INTEL_COMMON_PCH_LOCKDOWN_H */
15 changes: 15 additions & 0 deletions src/soc/intel/common/pch/lockdown/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,22 @@
config SOC_INTEL_COMMON_PCH_LOCKDOWN
bool
default n
select HAVE_INTEL_CHIPSET_LOCKDOWN
help
This option allows to have chipset lockdown for DMI, FAST_SPI and
soc_lockdown_config() to implement any additional lockdown as PMC,
LPC for supported PCH.

config SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM
bool "Lock down SPI controller in SMM"
default n
depends on HAVE_SMI_HANDLER && !INTEL_CHIPSET_LOCKDOWN
select SPI_FLASH_SMM
help
This option allows to have chipset lockdown for FAST_SPI and LPC for
supported PCH. If selected, coreboot will skip locking down the SPI
and LPC controller. The payload or OS is responsible for locking it
using APM_CNT_FINALIZE SMI. Used by heads to set and lock PR0 flash
protection.

If unsure, say N.
5 changes: 5 additions & 0 deletions src/soc/intel/common/pch/lockdown/Makefile.mk
Original file line number Diff line number Diff line change
@@ -1,2 +1,7 @@
## SPDX-License-Identifier: GPL-2.0-only
ramstage-$(CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN) += lockdown.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN) += lockdown_lpc.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN) += lockdown_spi.c

smm-$(CONFIG_SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM) += lockdown_lpc.c
smm-$(CONFIG_SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM) += lockdown_spi.c
49 changes: 5 additions & 44 deletions src/soc/intel/common/pch/lockdown/lockdown.c
Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <bootstate.h>
#include <dasharo/options.h>
#include <intelblocks/cfg.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/lpc_lib.h>
Expand Down Expand Up @@ -61,56 +60,17 @@ static void fast_spi_lockdown_cfg(int chipset_lockdown)
/* Set FAST_SPI opcode menu */
fast_spi_set_opcode_menu();

/* Discrete Lock Flash PR registers */
fast_spi_pr_dlock();

/* Check if SPI transaction is pending */
fast_spi_cycle_in_progress();

/* Clear any outstanding status bits like AEL, FCERR, FDONE, SAF etc. */
fast_spi_clear_outstanding_status();

/* Lock FAST_SPIBAR */
fast_spi_lock_bar();

/* Set Vendor Component Lock (VCL) */
fast_spi_vscc0_lock();

/* Set BIOS Interface Lock, BIOS Lock */
if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
/* BIOS Interface Lock */
fast_spi_set_bios_interface_lock_down();

/* Only allow writes in SMM */
if (CONFIG(BOOTMEDIA_SMM_BWP) && is_smm_bwp_permitted()) {
fast_spi_set_eiss();
fast_spi_enable_wp();
}

/* BIOS Lock */
fast_spi_set_lock_enable();

/* EXT BIOS Lock */
fast_spi_set_ext_bios_lock_enable();
}
}

static void lpc_lockdown_config(int chipset_lockdown)
{
/* Set BIOS Interface Lock, BIOS Lock */
if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
/* BIOS Interface Lock */
lpc_set_bios_interface_lock_down();

/* Only allow writes in SMM */
if (CONFIG(BOOTMEDIA_SMM_BWP) && is_smm_bwp_permitted()) {
lpc_set_eiss();
lpc_enable_wp();
}

/* BIOS Lock */
lpc_set_lock_enable();
}
if (!CONFIG(SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM))
fast_spi_lockdown_bios(chipset_lockdown);
}

static void sa_lockdown_config(int chipset_lockdown)
Expand All @@ -136,8 +96,9 @@ static void platform_lockdown_config(void *unused)
/* SPI lock down configuration */
fast_spi_lockdown_cfg(chipset_lockdown);

/* LPC/eSPI lock down configuration */
lpc_lockdown_config(chipset_lockdown);
if (!CONFIG(SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM))
/* LPC/eSPI lock down configuration */
lpc_lockdown_config(chipset_lockdown);

/* GPMR lock down configuration */
gpmr_lockdown_cfg();
Expand Down
24 changes: 24 additions & 0 deletions src/soc/intel/common/pch/lockdown/lockdown_lpc.c
Original file line number Diff line number Diff line change
@@ -0,0 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <dasharo/options.h>
#include <intelblocks/cfg.h>
#include <intelblocks/lpc_lib.h>
#include <intelpch/lockdown.h>

void lpc_lockdown_config(int chipset_lockdown)
{
/* Set BIOS Interface Lock, BIOS Lock */
if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
/* BIOS Interface Lock */
lpc_set_bios_interface_lock_down();

/* Only allow writes in SMM */
if (CONFIG(BOOTMEDIA_SMM_BWP) && is_smm_bwp_permitted()) {
lpc_set_eiss();
lpc_enable_wp();
}

/* BIOS Lock */
lpc_set_lock_enable();
}
}
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