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--Descripcion: | ||
--Implementación de hardware para mostrar el uso de los displays de 7 segmentos | ||
-- en un contador de 0 a 9 corriendo en una tarjeta Cyclone IV. | ||
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LIBRARY IEEE; | ||
USE IEEE.STD_LOGIC_1164.ALL; | ||
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ENTITY CONTADOR09 IS | ||
PORT( | ||
CLK : IN STD_LOGIC; | ||
INI : IN STD_LOGIC; | ||
RESET : IN STD_LOGIC; | ||
DISPLAY : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | ||
T : OUT STD_LOGIC | ||
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); | ||
END CONTADOR09; | ||
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ARCHITECTURE BEHAVIORAL OF CONTADOR09 IS | ||
CONSTANT RETRASO_FIN : INTEGER := 49_999_999; | ||
--CONSTANT RETRASO_FIN : INTEGER := 499_999; | ||
SIGNAL RETRASO : INTEGER RANGE 0 TO RETRASO_FIN := 0; | ||
SIGNAL CONTADOR_PRINCIPAL : INTEGER RANGE 0 TO 9 := 0; | ||
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BEGIN | ||
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PROCESS(CLK) | ||
BEGIN | ||
IF RISING_EDGE(CLK) THEN | ||
IF RESET = '1' THEN | ||
RETRASO <= 0; | ||
CONTADOR_PRINCIPAL <= 0; | ||
ELSE | ||
IF INI = '1' THEN | ||
RETRASO <= RETRASO+1; | ||
IF RETRASO = RETRASO_FIN THEN | ||
RETRASO <= 0; | ||
CONTADOR_PRINCIPAL <= CONTADOR_PRINCIPAL+1; | ||
IF CONTADOR_PRINCIPAL = 9 THEN | ||
CONTADOR_PRINCIPAL <= 0; | ||
END IF; | ||
END IF; | ||
END IF; | ||
END IF; | ||
END IF; | ||
END PROCESS; | ||
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--ABCDEFG | ||
DISPLAY <= "0000" WHEN CONTADOR_PRINCIPAL = 0 ELSE --0 | ||
"0001" WHEN CONTADOR_PRINCIPAL = 1 ELSE --1 | ||
"0010" WHEN CONTADOR_PRINCIPAL = 2 ELSE --2 | ||
"0011" WHEN CONTADOR_PRINCIPAL = 3 ELSE --3 | ||
"0100" WHEN CONTADOR_PRINCIPAL = 4 ELSE --4 | ||
"0101" WHEN CONTADOR_PRINCIPAL = 5 ELSE --5 | ||
"0110" WHEN CONTADOR_PRINCIPAL = 6 ELSE --6 | ||
"0111" WHEN CONTADOR_PRINCIPAL = 7 ELSE --7 | ||
"1000" WHEN CONTADOR_PRINCIPAL = 8 ELSE --8 | ||
"1001"; | ||
T <= '0'; | ||
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END BEHAVIORAL; |
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--NOTA:NUNCA PONER "-" GUION EN EL NOMBRE DE UN ARCHIVO O PROYECTO. | ||
LIBRARY IEEE; | ||
USE IEEE.STD_LOGIC_1164.ALL; | ||
--USE IEEE.NUMERIC_STD.ALL; | ||
--USE IEEE.STD_LOGIC_ARITH.ALL; | ||
--USE IEEE.STD_LOGIC_UNSIGNED.ALL; | ||
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ENTITY WIRE1 IS | ||
PORT( | ||
CLK:IN STD_LOGIC; | ||
INI : IN STD_LOGIC; | ||
RESET : IN STD_LOGIC; | ||
--A,B,C,D : IN STD_LOGIC; | ||
A1,B1,C1,D1,T1 : OUT STD_LOGIC | ||
); | ||
END WIRE1; | ||
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ARCHITECTURE BEHAVIORAL OF WIRE1 IS | ||
SIGNAL A,B,C,D,T : STD_LOGIC; | ||
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COMPONENT CONTADOR09 | ||
PORT( | ||
CLK : IN STD_LOGIC; | ||
INI : IN STD_LOGIC; | ||
RESET : IN STD_LOGIC; | ||
DISPLAY : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | ||
T : OUT STD_LOGIC | ||
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); | ||
END COMPONENT; | ||
BEGIN | ||
U1: CONTADOR09 PORT MAP( | ||
CLK =>CLK, | ||
INI =>INI, | ||
RESET =>RESET, | ||
DISPLAY(0) => A, | ||
DISPLAY(1) => B, | ||
DISPLAY(2) => C, | ||
DISPLAY(3) => D, | ||
T =>T | ||
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); | ||
A1<=A; | ||
B1<=B; | ||
C1<=C; | ||
D1<=D; | ||
T1 <= T; | ||
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END BEHAVIORAL; |