[HDL] Replace oehb with oehb_dataless in floating point units (#283)

The following PR replace the oehb module with oehb_dataless in floating
point units since they do not have any data.

data/verilog/arith/addf.v

@@ -21,8 +21,6 @@ module addf #(
   //assert(DATA_TYPE == 32) else $error("addf currently only supports 32-bit floating point operands");
 
   wire join_valid, oehb_ready, buff_valid;
-  wire constant_zero = 1'b0;
-  wire open_value;
 
   // intermediate input signals for IEEE-754 to Flopoco-simple-float conversion
   wire [ DATA_TYPE + 1 :0] ip_lhs, ip_rhs;
@@ -50,15 +48,11 @@ module addf #(
     .valid_out(buff_valid)
   );
 
-  oehb #(
-    .DATA_TYPE(1)
-  ) oehb_lhs (
+  oehb_dataless oehb_lhs (
     .clk(clk),
     .rst(rst),
-    .ins(constant_zero),
     .ins_valid(buff_valid),
     .ins_ready(oehb_ready),
-    .outs(open_value),
     .outs_valid(result_valid),
     .outs_ready(result_ready)
   );

data/verilog/arith/divf.v

@@ -20,8 +20,6 @@ module divf #(
   //assert(DATA_TYPE == 32) else $error("divf currently only supports 32-bit floating point operands");
 
   wire join_valid, oehb_ready, buff_valid;
-  wire constant_zero = 1'b0;
-  wire open_value;
 
   // intermediate input signals for IEEE-754 to Flopoco-simple-float conversion
   wire [ DATA_TYPE + 1 :0] ip_lhs, ip_rhs;
@@ -49,15 +47,11 @@ module divf #(
     .valid_out(buff_valid)
   );
 
-  oehb #(
-    .DATA_TYPE(1)
-  ) oehb_lhs (
+  oehb_dataless  oehb_lhs (
     .clk(clk),
     .rst(rst),
-    .ins(constant_zero),
     .ins_valid(buff_valid),
     .ins_ready(oehb_ready),
-    .outs(open_value),
     .outs_valid(result_valid),
     .outs_ready(result_ready)
   );

data/verilog/arith/mulf.v

@@ -19,8 +19,6 @@ module mulf #(
 
   //assert(DATA_TYPE == 32) else $fatal("mulf currently only supports 32-bit inputs");
 
-  wire constant_zero = 1'b0;
-  wire open_value;
   wire join_valid;
   wire buff_valid, oehb_ready;
 
@@ -50,15 +48,11 @@ module mulf #(
     .valid_out(buff_valid)
   );
 
-  oehb #(
-    .DATA_TYPE(1)
-  ) oehb_lhs (
+  oehb_dataless oehb_lhs (
     .clk(clk),
     .rst(rst),
-    .ins(constant_zero),
     .ins_valid(buff_valid),
     .ins_ready(oehb_ready),
-    .outs(open_value),
     .outs_valid(result_valid),
     .outs_ready(result_ready)
   );

data/verilog/arith/subf.v

@@ -20,8 +20,6 @@ module subf #(
   //assert(DATA_TYPE == 32) else $fatal("subf currently only supports 32-bit operands");
 
   wire join_valid, oehb_ready, buff_valid;
-  wire constant_zero = 1'b0;
-  wire open_value;
 
   // subf is the same as addf, but we flip the sign bit of rhs
   wire [DATA_TYPE - 1 : 0] rhs_neg;
@@ -52,15 +50,11 @@ module subf #(
     .valid_out(buff_valid)
   );
 
-  oehb #(
-    .DATA_TYPE(1)
-  ) oehb_lhs (
+  oehb_dataless  oehb_lhs (
     .clk(clk),
     .rst(rst),
-    .ins(constant_zero),
     .ins_valid(buff_valid),
     .ins_ready(oehb_ready),
-    .outs(open_value),
     .outs_valid(result_valid),
     .outs_ready(result_ready)
   );

data/vhdl/arith/addf.vhd

@@ -43,16 +43,14 @@ begin
       ins_ready(1) => rhs_ready
     );
 
-  oehb : entity work.oehb(arch) generic map(1)
+  oehb : entity work.oehb_dataless(arch)
     port map(
       clk        => clk,
       rst        => rst,
       ins_valid  => buff_valid,
       outs_ready => result_ready,
       outs_valid => result_valid,
-      ins_ready  => oehb_ready,
-      ins(0)     => '0',
-      outs    => open
+      ins_ready  => oehb_ready
     );
 
   buff : entity work.delay_buffer(arch) generic map(latency - 1)

data/vhdl/arith/cmpf.vhd

@@ -104,16 +104,14 @@ architecture arch of cmpf_double_precision is
   signal ip_rhs : std_logic_vector(64 + 1 downto 0);
 begin
 
- oehb : entity work.oehb(arch) generic map(1)
+ oehb : entity work.oehb_dataless(arch)
   port map(
     clk        => clk,
     rst        => rst,
     ins_valid  => buff_valid,
     outs_ready => result_ready,
     outs_valid => result_valid,
-    ins_ready  => oehb_ready,
-    ins(0)     => '0',
-    outs    => open
+    ins_ready  => oehb_ready
   );
   join_inputs : entity work.join(arch) generic map(2)
     port map(

data/vhdl/arith/divf.vhd

@@ -43,17 +43,14 @@ begin
       ins_ready(1) => rhs_ready
     );
 
-  oehb : entity work.oehb(arch) generic map (1)
+  oehb : entity work.oehb_dataless(arch)
     port map(
       clk        => clk,
       rst        => rst,
       ins_valid  => buff_valid,
       outs_ready => result_ready,
       outs_valid => result_valid,
-      --outputs
-      ins_ready => oehb_ready,
-      ins(0)    => '0',
-      outs   => open
+      ins_ready => oehb_ready
     );
   buff : entity work.delay_buffer(arch) generic map(latency - 1)
   port map(

data/vhdl/arith/mulf.vhd

@@ -52,16 +52,14 @@ begin
       buff_valid
     );
 
-  oehb : entity work.oehb(arch) generic map(1)
+  oehb : entity work.oehb_dataless(arch)
   port map(
     clk        => clk,
     rst        => rst,
     ins_valid  => buff_valid,
     outs_ready => result_ready,
     outs_valid => result_valid,
-    ins_ready  => oehb_ready,
-    ins(0)     => '0',
-    outs    => open
+    ins_ready  => oehb_ready
   );
 
   ieee2nfloat_lhs: entity work.InputIEEE_32bit(arch)

data/vhdl/arith/subf.vhd

@@ -46,16 +46,14 @@ begin
       ins_ready(1) => rhs_ready
     );
 
-  oehb : entity work.oehb(arch) generic map(1)
+  oehb : entity work.oehb_dataless(arch)
     port map(
       clk => clk,
       rst => rst,
       ins_valid => buff_valid,
       outs_ready => result_ready,
       outs_valid => result_valid,
-      ins_ready => oehb_ready,
-      ins(0) => '0',
-      outs => open
+      ins_ready => oehb_ready
     );
 
   rhs_neg <= not rhs(32 - 1) & rhs(32 - 2 downto 0);