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Merge pull request #4073 from Sonicadvance1/constexpr_all_tables
OpcodeDispatcher: Constexpr-ify all the tables possible
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45 changes: 45 additions & 0 deletions
45
FEXCore/Source/Interface/Core/OpcodeDispatcher/DDDTables.h
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,45 @@ | ||
| // SPDX-License-Identifier: MIT | ||
| #pragma once | ||
| #include "Interface/Core/OpcodeDispatcher.h" | ||
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| namespace FEXCore::IR { | ||
| constexpr std::tuple<uint8_t, uint8_t, FEXCore::X86Tables::OpDispatchPtr> OpDispatch_DDDTable[] = { | ||
| {0x0C, 1, &OpDispatchBuilder::PI2FWOp}, | ||
| {0x0D, 1, &OpDispatchBuilder::Vector_CVT_Int_To_Float<4, false>}, | ||
| {0x1C, 1, &OpDispatchBuilder::PF2IWOp}, | ||
| {0x1D, 1, &OpDispatchBuilder::Vector_CVT_Float_To_Int<4, false, false>}, | ||
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| {0x86, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorUnaryOp, IR::OP_VFRECP, 4>}, | ||
| {0x87, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorUnaryOp, IR::OP_VFRSQRT, 4>}, | ||
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| {0x8A, 1, &OpDispatchBuilder::PFNACCOp}, | ||
| {0x8E, 1, &OpDispatchBuilder::PFPNACCOp}, | ||
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| {0x90, 1, &OpDispatchBuilder::VPFCMPOp<1>}, | ||
| {0x94, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VFMIN, 4>}, | ||
| {0x96, 1, &OpDispatchBuilder::VectorUnaryDuplicateOp<IR::OP_VFRECP, 4>}, | ||
| {0x97, 1, &OpDispatchBuilder::VectorUnaryDuplicateOp<IR::OP_VFRSQRT, 4>}, | ||
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| {0x9A, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VFSUB, 4>}, | ||
| {0x9E, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VFADD, 4>}, | ||
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| {0xA0, 1, &OpDispatchBuilder::VPFCMPOp<2>}, | ||
| {0xA4, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VFMAX, 4>}, | ||
| // Can be treated as a move | ||
| {0xA6, 1, &OpDispatchBuilder::MOVVectorUnalignedOp}, | ||
| {0xA7, 1, &OpDispatchBuilder::MOVVectorUnalignedOp}, | ||
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| {0xAA, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUROp, IR::OP_VFSUB, 4>}, | ||
| {0xAE, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VFADDP, 4>}, | ||
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| {0xB0, 1, &OpDispatchBuilder::VPFCMPOp<0>}, | ||
| {0xB4, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VFMUL, 4>}, | ||
| // Can be treated as a move | ||
| {0xB6, 1, &OpDispatchBuilder::MOVVectorUnalignedOp}, | ||
| {0xB7, 1, &OpDispatchBuilder::PMULHRWOp}, | ||
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| {0xBB, 1, &OpDispatchBuilder::PSWAPDOp}, | ||
| {0xBF, 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VURAVG, 1>}, | ||
| }; | ||
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| } // namespace FEXCore::IR |
82 changes: 82 additions & 0 deletions
82
FEXCore/Source/Interface/Core/OpcodeDispatcher/H0F38Tables.h
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,82 @@ | ||
| // SPDX-License-Identifier: MIT | ||
| #pragma once | ||
| #include "Interface/Core/OpcodeDispatcher.h" | ||
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| namespace FEXCore::IR { | ||
| #define OPD(prefix, opcode) (((prefix) << 8) | opcode) | ||
| constexpr uint16_t PF_38_NONE = 0; | ||
| constexpr uint16_t PF_38_66 = (1U << 0); | ||
| constexpr uint16_t PF_38_F3 = (1U << 2); | ||
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| constexpr std::tuple<uint16_t, uint8_t, FEXCore::X86Tables::OpDispatchPtr> OpDispatch_H0F38Table[] = { | ||
| {OPD(PF_38_NONE, 0x00), 1, &OpDispatchBuilder::PSHUFBOp}, | ||
| {OPD(PF_38_66, 0x00), 1, &OpDispatchBuilder::PSHUFBOp}, | ||
| {OPD(PF_38_NONE, 0x01), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VADDP, 2>}, | ||
| {OPD(PF_38_66, 0x01), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VADDP, 2>}, | ||
| {OPD(PF_38_NONE, 0x02), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VADDP, 4>}, | ||
| {OPD(PF_38_66, 0x02), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VADDP, 4>}, | ||
| {OPD(PF_38_NONE, 0x03), 1, &OpDispatchBuilder::PHADDS}, | ||
| {OPD(PF_38_66, 0x03), 1, &OpDispatchBuilder::PHADDS}, | ||
| {OPD(PF_38_NONE, 0x04), 1, &OpDispatchBuilder::PMADDUBSW}, | ||
| {OPD(PF_38_66, 0x04), 1, &OpDispatchBuilder::PMADDUBSW}, | ||
| {OPD(PF_38_NONE, 0x05), 1, &OpDispatchBuilder::PHSUB<2>}, | ||
| {OPD(PF_38_66, 0x05), 1, &OpDispatchBuilder::PHSUB<2>}, | ||
| {OPD(PF_38_NONE, 0x06), 1, &OpDispatchBuilder::PHSUB<4>}, | ||
| {OPD(PF_38_66, 0x06), 1, &OpDispatchBuilder::PHSUB<4>}, | ||
| {OPD(PF_38_NONE, 0x07), 1, &OpDispatchBuilder::PHSUBS}, | ||
| {OPD(PF_38_66, 0x07), 1, &OpDispatchBuilder::PHSUBS}, | ||
| {OPD(PF_38_NONE, 0x08), 1, &OpDispatchBuilder::PSIGN<1>}, | ||
| {OPD(PF_38_66, 0x08), 1, &OpDispatchBuilder::PSIGN<1>}, | ||
| {OPD(PF_38_NONE, 0x09), 1, &OpDispatchBuilder::PSIGN<2>}, | ||
| {OPD(PF_38_66, 0x09), 1, &OpDispatchBuilder::PSIGN<2>}, | ||
| {OPD(PF_38_NONE, 0x0A), 1, &OpDispatchBuilder::PSIGN<4>}, | ||
| {OPD(PF_38_66, 0x0A), 1, &OpDispatchBuilder::PSIGN<4>}, | ||
| {OPD(PF_38_NONE, 0x0B), 1, &OpDispatchBuilder::PMULHRSW}, | ||
| {OPD(PF_38_66, 0x0B), 1, &OpDispatchBuilder::PMULHRSW}, | ||
| {OPD(PF_38_66, 0x10), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorVariableBlend, 1>}, | ||
| {OPD(PF_38_66, 0x14), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorVariableBlend, 4>}, | ||
| {OPD(PF_38_66, 0x15), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorVariableBlend, 8>}, | ||
| {OPD(PF_38_66, 0x17), 1, &OpDispatchBuilder::PTestOp}, | ||
| {OPD(PF_38_NONE, 0x1C), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorUnaryOp, IR::OP_VABS, 1>}, | ||
| {OPD(PF_38_66, 0x1C), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorUnaryOp, IR::OP_VABS, 1>}, | ||
| {OPD(PF_38_NONE, 0x1D), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorUnaryOp, IR::OP_VABS, 2>}, | ||
| {OPD(PF_38_66, 0x1D), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorUnaryOp, IR::OP_VABS, 2>}, | ||
| {OPD(PF_38_NONE, 0x1E), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorUnaryOp, IR::OP_VABS, 4>}, | ||
| {OPD(PF_38_66, 0x1E), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorUnaryOp, IR::OP_VABS, 4>}, | ||
| {OPD(PF_38_66, 0x20), 1, &OpDispatchBuilder::ExtendVectorElements<1, 2, true>}, | ||
| {OPD(PF_38_66, 0x21), 1, &OpDispatchBuilder::ExtendVectorElements<1, 4, true>}, | ||
| {OPD(PF_38_66, 0x22), 1, &OpDispatchBuilder::ExtendVectorElements<1, 8, true>}, | ||
| {OPD(PF_38_66, 0x23), 1, &OpDispatchBuilder::ExtendVectorElements<2, 4, true>}, | ||
| {OPD(PF_38_66, 0x24), 1, &OpDispatchBuilder::ExtendVectorElements<2, 8, true>}, | ||
| {OPD(PF_38_66, 0x25), 1, &OpDispatchBuilder::ExtendVectorElements<4, 8, true>}, | ||
| {OPD(PF_38_66, 0x28), 1, &OpDispatchBuilder::PMULLOp<4, true>}, | ||
| {OPD(PF_38_66, 0x29), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VCMPEQ, 8>}, | ||
| {OPD(PF_38_66, 0x2A), 1, &OpDispatchBuilder::MOVVectorNTOp}, | ||
| {OPD(PF_38_66, 0x2B), 1, &OpDispatchBuilder::PACKUSOp<4>}, | ||
| {OPD(PF_38_66, 0x30), 1, &OpDispatchBuilder::ExtendVectorElements<1, 2, false>}, | ||
| {OPD(PF_38_66, 0x31), 1, &OpDispatchBuilder::ExtendVectorElements<1, 4, false>}, | ||
| {OPD(PF_38_66, 0x32), 1, &OpDispatchBuilder::ExtendVectorElements<1, 8, false>}, | ||
| {OPD(PF_38_66, 0x33), 1, &OpDispatchBuilder::ExtendVectorElements<2, 4, false>}, | ||
| {OPD(PF_38_66, 0x34), 1, &OpDispatchBuilder::ExtendVectorElements<2, 8, false>}, | ||
| {OPD(PF_38_66, 0x35), 1, &OpDispatchBuilder::ExtendVectorElements<4, 8, false>}, | ||
| {OPD(PF_38_66, 0x37), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VCMPGT, 8>}, | ||
| {OPD(PF_38_66, 0x38), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VSMIN, 1>}, | ||
| {OPD(PF_38_66, 0x39), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VSMIN, 4>}, | ||
| {OPD(PF_38_66, 0x3A), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VUMIN, 2>}, | ||
| {OPD(PF_38_66, 0x3B), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VUMIN, 4>}, | ||
| {OPD(PF_38_66, 0x3C), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VSMAX, 1>}, | ||
| {OPD(PF_38_66, 0x3D), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VSMAX, 4>}, | ||
| {OPD(PF_38_66, 0x3E), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VUMAX, 2>}, | ||
| {OPD(PF_38_66, 0x3F), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VUMAX, 4>}, | ||
| {OPD(PF_38_66, 0x40), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::VectorALUOp, IR::OP_VMUL, 4>}, | ||
| {OPD(PF_38_66, 0x41), 1, &OpDispatchBuilder::PHMINPOSUWOp}, | ||
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| {OPD(PF_38_NONE, 0xF0), 2, &OpDispatchBuilder::MOVBEOp}, | ||
| {OPD(PF_38_66, 0xF0), 2, &OpDispatchBuilder::MOVBEOp}, | ||
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| {OPD(PF_38_66, 0xF6), 1, &OpDispatchBuilder::ADXOp}, | ||
| {OPD(PF_38_F3, 0xF6), 1, &OpDispatchBuilder::ADXOp}, | ||
| }; | ||
| #undef OPD | ||
|
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| } // namespace FEXCore::IR |
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