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Tsinghua University
- Beijing
Highlights
- Pro
Pinned Loading
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gnn-acceleration-framework-with-FPGA
gnn-acceleration-framework-with-FPGA Publicincluding compiler to encode DGL GNN model to instructions, runtime software to transfer data and control the accelerator, and hardware verilog code that can be implemented on FPGA
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RTL_library_of_basic_hardware_units
RTL_library_of_basic_hardware_units PublicHere are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and support the hardware design tradeoff.
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face_recognation_with_caffe_and_DPU
face_recognation_with_caffe_and_DPU PublicFace Recognition Application based on CPU Version of Caffe and FPGA accelerator based on PCIE Interface, programed with python, C++, multithread, opencv2
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Program_Design-Tetris
Program_Design-Tetris PublicTetris program running in cmd line of windows system, written in C++. Windows命令行游戏,俄罗斯方块
C++
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Gaussian_noise_on_LeNet_experiment
Gaussian_noise_on_LeNet_experiment PublicGaussian noise on Lenet experiment with pytorch. Lenet神经网络上的高斯噪声传播实验.
Jupyter Notebook
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