Merge pull request #13 from ChipUSM/main

CHIPCHILE_CANELOS24_WorkshopTO

CHIPCHILE_CANELOS24_WorkshopTO/design_data/orfs/config.mk

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+# Process node
+export PROCESS = ihp-sg13g2
+
+#-----------------------------------------------------
+# Tech/Libs
+# ----------------------------------------------------
+export TECH_LEF = $(PDK_ROOT)/$(PDK)/libs.ref/sg13g2_stdcell/lef/sg13g2_tech.lef
+export SC_LEF =   $(PDK_ROOT)/$(PDK)/libs.ref/sg13g2_stdcell/lef/sg13g2_stdcell.lef
+
+export LIB_FILES = $(PDK_ROOT)/$(PDK)/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_typ_1p20V_25C.lib \
+	                  $(ADDITIONAL_LIBS)
+export GDS_FILES = $(PDK_ROOT)/$(PDK)/libs.ref/sg13g2_stdcell/gds/sg13g2_stdcell.gds \
+	                  $(ADDITIONAL_GDS)
+
+#export GDS_LAYER_MAP = $(PDK_ROOT)/$(PDK)/libs.tech/klayout/tech/sg13g2.map
+
+# Dont use cells to ease congestion
+# Specify at least one filler cell if none
+
+# The *probe* are for inserting probe points and have metal shapes
+# on all layers.
+# *lpflow* cells are for multi-power domains
+export DONT_USE_CELLS += \
+sg13g2_lgcp_1 \
+sg13g2_sighold \
+sg13g2_slgcp_1 \
+sg13g2_dfrbp_2
+
+
+# Define fill cells
+export FILL_CELLS = sg13g2_fill_1 sg13g2_fill_2 sg13g2_decap_4 sg13g2_decap_8
+# -----------------------------------------------------
+#  Yosys
+#  ----------------------------------------------------
+# Set the TIEHI/TIELO cells
+# These are used in yosys synthesis to avoid logical 1/0's in the netlist
+export TIEHI_CELL_AND_PORT = sg13g2_tiehi L_HI
+export TIELO_CELL_AND_PORT = sg13g2_tielo L_LO
+
+# Used in synthesis
+export MIN_BUF_CELL_AND_PORTS = sg13g2_buf_1 A X
+
+# Yosys mapping files
+export LATCH_MAP_FILE = $(PLATFORM_DIR)/cells_latch.v
+export CLKGATE_MAP_FILE = $(PLATFORM_DIR)/cells_clkgate.v
+
+# Define ABC driver and load
+export ABC_DRIVER_CELL = sg13g2_buf_4
+export ABC_LOAD_IN_FF = 6.0
+# Set yosys-abc clock period to first "clk_period" value or "-period" value found in sdc file
+export ABC_CLOCK_PERIOD_IN_PS ?= $(shell sed -nE "s/^set clk_period (.+)|.* -period (.+) .*/\1\2/p" $(SDC_FILE) | head -1 | awk '{print $$1*1000}')
+#--------------------------------------------------------
+# Floorplan
+# -------------------------------------------------------
+
+# Placement site for core cells
+# This can be found in the technology lef
+export PLACE_SITE = CoreSite
+
+# IO Placer pin layers
+export IO_PLACER_H = Metal2
+export IO_PLACER_V = Metal3
+
+# Define default PDN config
+export PDN_TCL ?= $(PLATFORM_DIR)/pdn.tcl
+
+# To allow the core rings to fit inside the core area
+export CORE_MARGIN ?= 16.5
+
+# There are no Endcap and Welltie cells in this PDK, so
+# `cut_rows` has to be called from the tapcell script.
+export TAPCELL_TCL = $(PLATFORM_DIR)/tapcell.tcl
+
+export MACRO_PLACE_HALO ?= 40 40
+export MACRO_PLACE_CHANNEL ?= 80 80
+
+#---------------------------------------------------------
+# Place
+# --------------------------------------------------------
+export PLACE_DENSITY ?= 0.65
+
+# ---------------------------------------------------------
+#  Route
+# ---------------------------------------------------------
+# FastRoute options
+export MIN_ROUTING_LAYER 		?= Metal2
+export MAX_ROUTING_LAYER 		?= Metal5
+#export VIA_IN_PIN_MIN_LAYER ?= Metal1
+#export VIA_IN_PIN_MAX_LAYER ?= Metal1
+#export DISABLE_VIA_GEN      ?= 1
+#
+# Define fastRoute tcl
+export FASTROUTE_TCL ?= $(PLATFORM_DIR)/fastroute.tcl
+
+# KLayout technology file
+export KLAYOUT_TECH_FILE =  $(PDK_ROOT)/$(PDK)/libs.tech/klayout/tech/sg13g2.lyt
+#
+# Rules for metal fill
+export FILL_CONFIG = $(PLATFORM_DIR)/fill.json
+#
+# Template definition for power grid analysis
+#export TEMPLATE_PGA_CFG ?= $(PLATFORM_DIR)/template_pga.cfg
+
+# OpenRCX extRules
+export RCX_RULES = $(PLATFORM_DIR)/rcx_patterns.rules
+
+# ---------------------------------------------------------
+#  IR Drop
+# ---------------------------------------------------------
+
+# IR drop estimation supply net name to be analyzed and supply voltage variable
+# For multiple nets: PWR_NETS_VOLTAGES  = "VDD1 1.8 VDD2 1.2"
+export PWR_NETS_VOLTAGES  ?= "VDD 1.2"
+export GND_NETS_VOLTAGES  ?= "VSS 0.0"
+export IR_DROP_LAYER ?= Metal1
+
+# DRC Check
+export KLAYOUT_DRC_FILE = $(PDK_ROOT)/$(PDK)/libs.tech/klayout/tech/drc/sg13g2_maximal.lydrc
+
+#LVS Check
+export CDL_FILE =  $(PDK_ROOT)/$(PDK)/libs.ref/sg13g2_stdcell/cdl/sg13g2_stdcell.cdl
+export KLAYOUT_LVS_FILE = $(PDK_ROOT)/$(PDK)/libs.tech/klayout/tech/lvs/sg13g2_full.lylvs

CHIPCHILE_CANELOS24_WorkshopTO/design_data/orfs/designs/ihp-sg13g2/MixedSignal_AIaccelerator_AMux/config.mk

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+export DESIGN_NICKNAME = MixedSignal_AIaccelerator_AMux
+export DESIGN_NAME = MixedSignal_AIaccelerator_AMux
+export PLATFORM    = ihp-sg13g2
+
+export VERILOG_FILES =  $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v \
+                        $(DESIGN_HOME)/src/ser_neuron_grid/*.v \
+
+
+
+export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
+
+export DIE_AREA = 0 0 1400 1400
+export CORE_AREA = 400 400 1000 738
+export FOOTPRINT_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/pad.tcl
+export PDN_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/pdn.tcl
+
+export PLACE_DENSITY = 0.7
+export TNS_END_PERCENT = 100
+
+export SYNTH_MEMORY_MAX_BITS = 16384
+
+# Allow routing on the TopMetal layers, for the padring connections
+export MAX_ROUTING_LAYER = TopMetal2
+
+# Following exports should be part of platforms/ihp-sg13g2/config.mk and
+# might be obsolete in the future.
+export ADDITIONAL_LEFS = \
+    $(IHP_PDK_ROOT)/$(PDK)/libs.ref/sg13g2_io/lef/sg13g2_io.lef \
+    $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macros/bondpad/lef/bondpad_70x70.lef
+export ADDITIONAL_GDS = \
+    $(IHP_PDK_ROOT)/$(PDK)/libs.ref/sg13g2_io/gds/sg13g2_io.gds \
+    $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macros/bondpad/gds/bondpad_70x70.gds
+export ADDITIONAL_LIBS = \
+    $(IHP_PDK_ROOT)/$(PDK)/libs.ref/sg13g2_io/lib/sg13g2_io_dummy.lib
+export CDL_FILE = \
+    $(IHP_PDK_ROOT)/$(PDK)/libs.ref/sg13g2_stdcell/cdl/sg13g2_stdcell.cdl \
+    $(IHP_PDK_ROOT)/$(PDK)/libs.ref/sg13g2_io/cdl/sg13g2_io.cdl \
+    $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macros/bondpad/cdl/bondpad_70x70.cdl
+
+
+export ADDITIONAL_LEFS += \
+        $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macros/analog_blockage/lef/analog_blockage.lef
+#export MACRO_PLACEMENT = \
+        $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macro_placement.cfg

CHIPCHILE_CANELOS24_WorkshopTO/design_data/orfs/designs/ihp-sg13g2/MixedSignal_AIaccelerator_AMux/constraint.sdc

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+set clk_name  clk
+set clk_port_name clk_PAD
+set clk_period 10.4
+set clk_io_pct 0.2
+
+set clk_port [get_ports $clk_port_name]
+
+set clk_input_ports [get_ports {
+    clk_PAD
+    rst_n_PAD
+    chip_in_PAD
+    chip_in_analog_PAD
+}]
+
+set clk_output_ports [get_ports {
+    chip_out_PAD
+}]
+
+create_clock -name $clk_name -period $clk_period $clk_port
+
+set_driving_cell -lib_cell sg13g2_IOPadIn -pin pad $clk_port
+set_driving_cell -lib_cell sg13g2_IOPadIn -pin pad $clk_input_ports
+set_driving_cell -lib_cell sg13g2_IOPadOut4mA -pin pad $clk_output_ports
+
+set_input_delay  [expr $clk_period * $clk_io_pct] -clock $clk_name $clk_input_ports 
+set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $clk_output_ports

CHIPCHILE_CANELOS24_WorkshopTO/design_data/orfs/designs/ihp-sg13g2/MixedSignal_AIaccelerator_AMux/export.me

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+#design specific 
+export ORFS_ROOT=$ORFS_DIR
+export OPENROAD_EXE=$(command -v openroad)
+export YOSYS_CMD=$(command -v yosys)
+export WORK_HOME=$(pwd)
+export IHP_PDK_ROOT=$PDK_ROOT
+export DESIGN_HOME=$WORK_HOME/designs
+export DESIGN_CONFIG=${DESIGN_HOME}/ihp-sg13g2/MixedSignal_AIaccelerator_AMux/config.mk
+#design specific 
+
+##### update the platform files
+sudo cp config.mk /opt/OpenROAD-flow-scripts/flow/platforms/ihp-sg13g2/
+cp designs/ihp-sg13g2/top_1mm2/sg13g2_io_dummy.lib /opt/pdks/ihp-sg13g2/libs.ref/sg13g2_io/lib/
+

CHIPCHILE_CANELOS24_WorkshopTO/design_data/orfs/designs/ihp-sg13g2/MixedSignal_AIaccelerator_AMux/macros/bondpad/cdl/bondpad_70x70.cdl

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+.SUBCKT bondpad_70x70 pad
+*.PININFO pad:B
+.ENDS

CHIPCHILE_CANELOS24_WorkshopTO/design_data/orfs/designs/ihp-sg13g2/MixedSignal_AIaccelerator_AMux/macros/bondpad/lef/bondpad_70x70.lef

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+VERSION 5.8 ;
+
+MACRO bondpad_70x70
+  CLASS COVER ;
+  ORIGIN 0 0 ;
+  FOREIGN bondpad_70x70 0 0 ;
+  SIZE 70.0 BY 70.0 ;
+  SYMMETRY X Y R90 ;
+  SITE sg13g2_ioSite ;
+  PIN pad
+    USE SIGNAL ;
+    PORT
+      LAYER Metal2 ;
+        RECT 0 0 70.0 70.0 ;
+      LAYER Metal3 ;
+        RECT 0 0 70.0 70.0 ;
+      LAYER Metal4 ;
+        RECT 0 0 70.0 70.0 ;
+      LAYER Metal5 ;
+        RECT 0 0 70.0 70.0 ;
+      LAYER TopMetal1 ;
+        RECT 0 0 70.0 70.0 ;
+      LAYER TopMetal2 ;
+        RECT 0 0 70.0 70.0 ;
+    END
+  END pad
+
+  OBS
+    LAYER Metal1 ;
+      RECT 0 0 70.0 70.0 ;
+    LAYER Metal2 ;
+      RECT 0 0 70.0 70.0 ;
+    LAYER Metal3 ;
+      RECT 0 0 70.0 70.0 ;
+    LAYER Metal4 ;
+      RECT 0 0 70.0 70.0 ;
+    LAYER Metal5 ;
+      RECT 0 0 70.0 70.0 ;
+    LAYER TopMetal1 ;
+      RECT 0 0 70.0 70.0 ;
+    LAYER TopMetal2 ;
+      RECT 0 0 70.0 70.0 ;
+  END
+END bondpad_70x70

CHIPCHILE_CANELOS24_WorkshopTO/design_data/orfs/designs/ihp-sg13g2/MixedSignal_AIaccelerator_AMux/pad.tcl

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+# Based on https://github.com/IHP-GmbH/IHP-Open-DesignLib/blob/c8f9135780226fb7c731c70147ae194e55a523a3/ElemRV/design_data/src/pad.tcl
+
+set IO_LENGTH 180
+set IO_WIDTH 80
+set BONDPAD_SIZE 70
+set SEALRING_OFFSET 70
+set MAX_NUM_PADS_HORIZONTAL 7
+set MAX_NUM_PADS_VERTICAL 7
+
+proc calc_horizontal_pad_location {index} {
+    global IO_LENGTH
+    global IO_WIDTH
+    global BONDPAD_SIZE
+    global MAX_NUM_PADS_HORIZONTAL
+    global SEALRING_OFFSET
+
+    set DIE_WIDTH [expr {[lindex $::env(DIE_AREA) 2] - [lindex $::env(DIE_AREA) 0]}]
+    set PAD_OFFSET [expr {$IO_LENGTH + $BONDPAD_SIZE + $SEALRING_OFFSET}]
+    set PAD_AREA_WIDTH [expr {$DIE_WIDTH - ($PAD_OFFSET * 2)}]
+    set HORIZONTAL_PAD_DISTANCE [expr {($PAD_AREA_WIDTH / $MAX_NUM_PADS_HORIZONTAL) - $IO_WIDTH}]
+
+    return [expr {$PAD_OFFSET + (($IO_WIDTH + $HORIZONTAL_PAD_DISTANCE) * $index) + ($HORIZONTAL_PAD_DISTANCE / 2)}]
+}
+
+proc calc_vertical_pad_location {index} {
+    global IO_LENGTH
+    global IO_WIDTH
+    global BONDPAD_SIZE
+    global MAX_NUM_PADS_VERTICAL
+    global SEALRING_OFFSET
+
+    set DIE_HEIGHT [expr {[lindex $::env(DIE_AREA) 3] - [lindex $::env(DIE_AREA) 1]}]
+    set PAD_OFFSET [expr {$IO_LENGTH + $BONDPAD_SIZE + $SEALRING_OFFSET}]
+    set PAD_AREA_HEIGHT [expr {$DIE_HEIGHT - ($PAD_OFFSET * 2)}]
+    set VERTICAL_PAD_DISTANCE [expr {($PAD_AREA_HEIGHT / $MAX_NUM_PADS_VERTICAL) - $IO_WIDTH}]
+
+    return [expr {$PAD_OFFSET + (($IO_WIDTH + $VERTICAL_PAD_DISTANCE) * $index) + ($VERTICAL_PAD_DISTANCE / 2)}]
+}
+
+#set_io_pin_constraint -pin_names {chip_internal[0] chip_internal[1] chip_internal[2] chip_internal[3] chip_internal[4] chip_internal[5] chip_internal[6] chip_internal[7]} -region top:*
+place_pin -pin_name chip_internal[0] -layer Metal5 -location {450 738}
+place_pin -pin_name chip_internal[1] -layer Metal5 -location {460 738}
+place_pin -pin_name chip_internal[2] -layer Metal5 -location {470 738}
+place_pin -pin_name chip_internal[3] -layer Metal5 -location {480 738}
+place_pin -pin_name chip_internal[4] -layer Metal5 -location {500 738}
+place_pin -pin_name chip_internal[5] -layer Metal5 -location {510 738}
+place_pin -pin_name chip_internal[6] -layer Metal5 -location {520 738}
+place_pin -pin_name chip_internal[7] -layer Metal5 -location {530 738}
+
+place_pin -pin_name chip_internal[8] -layer Metal5 -location {540 738}
+place_pin -pin_name chip_internal[9] -layer Metal5 -location {550 738}
+place_pin -pin_name chip_internal[10] -layer Metal5 -location {560 738}
+place_pin -pin_name chip_internal[11] -layer Metal5 -location {570 738}
+place_pin -pin_name chip_internal[12] -layer Metal5 -location {580 738}
+place_pin -pin_name chip_internal[13] -layer Metal5 -location {590 738}
+place_pin -pin_name chip_internal[14] -layer Metal5 -location {600 738}
+place_pin -pin_name chip_internal[15] -layer Metal5 -location {610 738}
+
+make_fake_io_site -name IOLibSite -width 1 -height $IO_LENGTH
+make_fake_io_site -name IOLibCSite -width $IO_LENGTH -height $IO_LENGTH
+
+set IO_OFFSET [expr {$BONDPAD_SIZE + $SEALRING_OFFSET}]
+# Create IO Rows
+make_io_sites \
+    -horizontal_site IOLibSite \
+    -vertical_site IOLibSite \
+    -corner_site IOLibCSite \
+    -offset $IO_OFFSET
+
+# Place Pads
+place_pad -row IO_SOUTH -location [calc_horizontal_pad_location  0] {sg13g2_chip_in_0}
+place_pad -row IO_SOUTH -location [calc_horizontal_pad_location  1] {sg13g2_chip_in_1} 
+place_pad -row IO_SOUTH -location [calc_horizontal_pad_location  2] {sg13g2_IOPadIOVss_1} -master sg13g2_IOPadIOVss
+place_pad -row IO_SOUTH -location [calc_horizontal_pad_location  3] {sg13g2_IOPadIOVdd_1} -master sg13g2_IOPadIOVdd
+place_pad -row IO_SOUTH -location [calc_horizontal_pad_location  4] {sg13g2_chip_in_2}
+place_pad -row IO_SOUTH -location [calc_horizontal_pad_location  5] {sg13g2_chip_in_3} 
+place_pad -row IO_SOUTH -location [calc_horizontal_pad_location  6] {sg13g2_chip_in_4}
+
+place_pad -row IO_EAST -location [calc_vertical_pad_location  0] {sg13g2_chip_in_5}
+place_pad -row IO_EAST -location [calc_vertical_pad_location  1] {sg13g2_chip_in_6}
+place_pad -row IO_EAST -location [calc_vertical_pad_location  2] {sg13g2_chip_in_7} 
+place_pad -row IO_EAST -location [calc_vertical_pad_location  3] {sg13g2_IOPadVss_1} -master sg13g2_IOPadVss
+place_pad -row IO_EAST -location [calc_vertical_pad_location  4] {sg13g2_chip_analog_0} 
+place_pad -row IO_EAST -location [calc_vertical_pad_location  5] {sg13g2_chip_analog_1}
+place_pad -row IO_EAST -location [calc_vertical_pad_location  6] {sg13g2_chip_analog_2}
+
+place_pad -row IO_NORTH -location [calc_horizontal_pad_location  0] {sg13g2_chip_analog_3}
+place_pad -row IO_NORTH -location [calc_horizontal_pad_location  1] {sg13g2_chip_analog_4}
+place_pad -row IO_NORTH -location [calc_horizontal_pad_location  2] {sg13g2_chip_analog_5}
+place_pad -row IO_NORTH -location [calc_horizontal_pad_location  3] {sg13g2_chip_analog_6}
+place_pad -row IO_NORTH -location [calc_horizontal_pad_location  4] {sg13g2_chip_analog_7}
+place_pad -row IO_NORTH -location [calc_horizontal_pad_location  5] {sg13g2_chip_analog_8}
+place_pad -row IO_NORTH -location [calc_horizontal_pad_location  6] {sg13g2_chip_analog_9} 
+
+place_pad -row IO_WEST -location [calc_vertical_pad_location  0] {sg13g2_IOPadVdd_1} -master sg13g2_IOPadVdd 
+place_pad -row IO_WEST -location [calc_vertical_pad_location  1] {sg13g2_chip_out_0}
+place_pad -row IO_WEST -location [calc_vertical_pad_location  2] {sg13g2_rst_n} 
+place_pad -row IO_WEST -location [calc_vertical_pad_location  3] {sg13g2_clk} 
+place_pad -row IO_WEST -location [calc_vertical_pad_location  4] {sg13g2_chip_analog_10}
+place_pad -row IO_WEST -location [calc_vertical_pad_location  5] {sg13g2_chip_analog_11}
+place_pad -row IO_WEST -location [calc_vertical_pad_location  6] {sg13g2_chip_analog_12}
+
+
+# Place Corner Cells and Filler
+place_corners sg13g2_Corner
+
+set iofill {
+    sg13g2_Filler10000
+    sg13g2_Filler4000
+    sg13g2_Filler2000
+    sg13g2_Filler1000
+    sg13g2_Filler400
+    sg13g2_Filler200
+}
+
+place_io_fill -row IO_NORTH {*}$iofill
+place_io_fill -row IO_SOUTH {*}$iofill
+place_io_fill -row IO_WEST {*}$iofill
+place_io_fill -row IO_EAST {*}$iofill
+
+connect_by_abutment
+
+place_bondpad -bond bondpad_70x70 sg13g2_* -offset {5.0 -70.0}
+
+remove_io_rows