v0.72

What's Changed

• [apb] fixed apb converter and desconverter by @AndreMerendeira in #715
• [apb2iob] removed unused signals by @AndreMerendeira in #716
• [utils] added circular shift by @AndreMerendeira in #717
• [bfifo][pack/unpack] linting and formatting by @AndreMerendeira in #720
• [bfifo] fixed write operation by @AndreMerendeira in #724
• Add Nix packages for Linux; Add minicom configuration file. by @arturum1 in #722
• [module,py] fixed adding version and generating conf_h when no swregs by @AndreMerendeira in #726
• used localparams for constants by @AndreMerendeira in #727
• feat(is_system): Add is_system attribute to iob_module by @arturum1 in #728
• Linting and CSR fixes by @AndreMerendeira in #729
• [pack/unpack] added missing signal extension by @AndreMerendeira in #731
• Verilator fix by @jjts in #732
• Iob if by @AndreMerendeira in #734
• [apb2iob] removed rvalid testing by @AndreMerendeira in #737
• Fix apb by @jjts in #738
• Ipxact gen by @AndreMerendeira in #739
• Added fpga_list feature. Now only fpga's files in this liist will be copied by @AndreMerendeira in #740
• fix(if_gen): Fix bug in 'bus_size' argument by @arturum1 in #741
• [ipxact] macros are now ignored by @AndreMerendeira in #742
• Changed fpga_list to board_list by @AndreMerendeira in #743
• Added a try catch around get_build_dir otherwise error could delete entire project by @zettasticks in #745
• [create_wrapper_files] interconnect files only added if board folder exists in core by @AndreMerendeira in #744
• [ug] fake parameters are now placed in a list instead of the confs table by @AndreMerendeira in #747
• feat(iob_timer): add Timer linux drivers and user program example by @P-Miranda in #746
• fix(setup.mk): Exit with error when get_build_dir command fails. by @arturum1 in #748
• feat(drivers): improve iob_timer drivers to use sysfs; remove linux header code from python scripts by @P-Miranda in #758
• removed the sram reg defenition and switched to iob_reg by @Vasco-Luz in #770
• reset of the error by @Vasco-Luz in #771
• fix: update with @arturum1 fork by @P-Miranda in #774
• [asym_converter] fixed rdata changing without a read by @AndreMerendeira in #779
• [ipxact_gen] fixed module name by @AndreMerendeira in #780
• [iob_soc_utils.py] added search for scripts directory by @AndreMerendeira in #781
• [iob_soc_utils.py] fixed scripts copy by @AndreMerendeira in #786
• memwrap all commits by @Vasco-Luz in #791
• update memwrap by @Vasco-Luz in #795
• Memwrap by @jjts in #796
• feat(python): add mypy type checking to iob-soc setup by @P-Miranda in #799
• xcellium fix by @Vasco-Luz in #812
• removed memories and changed purposes of some submodules by @Vasco-Luz in #817
• fix(setup): clean [corename]_V* pattern by @P-Miranda in #831
• added yosys-abc and volare,fix syntax error ,end synthesys with genus by @Vasco-Luz in #828
• [iob_module] re-written _run_setup_files to import and run modules i… by @AndreMerendeira in #832
• Changed from hardcoded to dinamic io inside memwrap.v related to iob-soc instance. by @Vasco-Luz in #833
• [Artix US+] added board support for fpga-build by @AndreMerendeira in #841
• fix(CI): update checkout action to use node 20 by @P-Miranda in #839
• added a choice of synthesiser and added yosys synthesis by @Vasco-Luz in #849
• Added IOb-KU15P board support by @AndreMerendeira in #852
• [boards] added IOb-AU20P support by @AndreMerendeira in #853
• [fpga] fixed IOb-KU15P part by @AndreMerendeira in #854
• Merge eth_simulation into main by @P-Miranda in #856

Full Changelog: V0.71...v0.72