BDD-based bit vector constrained sampler
$ tar -xf lib.tar
$ cd lib/cudd-3.0.0
$ ./configure --enable-silent-rules --enable-obj
$ make
$ cd src
$ make
$ ./bddsampler inputfile
dot to png:
dot -Tpng filename.dot -o filename.png
dot to pdf:
dot -Tpdf filename.dot -o filename.pdf
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Unify the variable bit-widths according to the syntax of system verilog before operation.
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Configure python test scripts to verify the correctness of logical operations.