ЛР3. Исправление подключения модуля в nexys_rf

MPSU · Sep 9, 2024 · 7b58389 · 7b58389
1 parent ffec97f
commit 7b58389
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/Labs/03. Register file and memory/board files/nexys_rf_riscv.sv b/Labs/03. Register file and memory/board files/nexys_rf_riscv.sv
@@ -34,7 +34,7 @@ module nexys_rf_riscv(
   logic [7:0][3:0] rd1;
   logic [7:0][3:0] rd2;
 
-  rf_riscv rf_riscv (
+  register_file rf_riscv (
     .clk_i            (clk_i),
     .read_addr1_i     (ra1  ),
     .read_addr2_i     (ra2  ),