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target/sim: Add external serial link AXI port to VIP (pulp-platform#51)
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* target/sim/src: Add 2x1 mux to allow external Serial Link drivers

* target/sim/src: Attempt to simplify external AXI mst

* target/sim/src: Remove axi_id_remap

* vip: Simplify external port connection

* clic: Fix connection parameterization

* Bender.yml: Update `axi` release

---------

Co-authored-by: Michael Rogenmoser <[email protected]>
Co-authored-by: Paul Scheffler <[email protected]>
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@alex96295 @micprog
@paulsc96 @MaistoV
3 people authored and MaistoV committed Aug 23, 2023
1 parent 4575ef8 commit 2497dde
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Showing 5 changed files with 74 additions and 8 deletions.
4 changes: 2 additions & 2 deletions Bender.lock
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Expand Up @@ -26,8 +26,8 @@ packages:
- cva6
- tech_cells_generic
axi:
revision: 1c9a10278efe643e40e22c88dbd56243fb3343c8
version: 0.39.0-beta.10
revision: bfee21757bf090ec8e358456314b0b0fd3c90809
version: 0.39.0
source:
Git: https://github.com/pulp-platform/axi.git
dependencies:
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2 changes: 1 addition & 1 deletion Bender.yml
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Expand Up @@ -13,7 +13,7 @@ package:

dependencies:
apb_uart: { git: "https://github.com/pulp-platform/apb_uart.git", version: 0.2.1 }
axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.0-beta.10 }
axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.0 }
axi_llc: { git: "https://github.com/pulp-platform/axi_llc.git", version: 0.2.1 }
axi_riscv_atomics: { git: "https://github.com/pulp-platform/axi_riscv_atomics.git", version: 0.7.0 }
axi_vga: { git: "https://github.com/pulp-platform/axi_vga.git", version: 0.1.1 }
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4 changes: 2 additions & 2 deletions hw/cheshire_soc.sv
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Expand Up @@ -715,9 +715,9 @@ module cheshire_soc import cheshire_pkg::*; #(

cheshire_intr_clic_t clic_intr;

// Connect interrupts to routed fanout, PLIC, and CLIC
// Connect interrupts to CLIC
assign clic_intr = '{
intr: intr_routed[IntrRtdCoreBase+0][NumClicIntrs-1:0],
intr: intr_routed[IntrRtdCoreBase+0][NumClicSysIntrs-1:0],
core: '{
meip: xeip[0].m,
seip: xeip[0].s,
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9 changes: 8 additions & 1 deletion target/sim/src/fixture_cheshire_soc.sv
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Expand Up @@ -148,10 +148,17 @@ module fixture_cheshire_soc;
// VIP //
///////////

axi_mst_req_t axi_slink_mst_req;
axi_mst_rsp_t axi_slink_mst_rsp;

assign axi_slink_mst_req = '0;

vip_cheshire_soc #(
.DutCfg ( DutCfg ),
.axi_ext_llc_req_t ( axi_llc_req_t ),
.axi_ext_llc_rsp_t ( axi_llc_rsp_t )
.axi_ext_llc_rsp_t ( axi_llc_rsp_t ),
.axi_ext_mst_req_t ( axi_mst_req_t ),
.axi_ext_mst_rsp_t ( axi_mst_rsp_t )
) vip (.*);

endmodule
63 changes: 61 additions & 2 deletions target/sim/src/vip_cheshire_soc.sv
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Expand Up @@ -14,6 +14,8 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
parameter cheshire_cfg_t DutCfg = '0,
parameter type axi_ext_llc_req_t = logic,
parameter type axi_ext_llc_rsp_t = logic,
parameter type axi_ext_mst_req_t = logic,
parameter type axi_ext_mst_rsp_t = logic,
// Timing
parameter time ClkPeriodSys = 5ns,
parameter time ClkPeriodJtag = 20ns,
Expand All @@ -31,6 +33,8 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
parameter int unsigned SlinkMaxWaitR = 5,
parameter int unsigned SlinkMaxWaitResp = 20,
parameter int unsigned SlinkBurstBytes = 1024,
parameter int unsigned SlinkMaxTxns = 32,
parameter int unsigned SlinkMaxTxnsPerId = 16,
parameter bit SlinkAxiDebug = 0,
// Derived Parameters; *do not override*
parameter int unsigned AxiStrbWidth = DutCfg.AxiDataWidth/8,
Expand All @@ -44,6 +48,9 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
// External AXI LLC (DRAM) port
input axi_ext_llc_req_t axi_llc_mst_req,
output axi_ext_llc_rsp_t axi_llc_mst_rsp,
// External serial link AXI port
input axi_ext_mst_req_t axi_slink_mst_req,
output axi_ext_mst_rsp_t axi_slink_mst_rsp,
// JTAG interface
output logic jtag_tck,
output logic jtag_trst_n,
Expand Down Expand Up @@ -552,10 +559,24 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
.AXI_DATA_WIDTH ( DutCfg.AxiDataWidth ),
.AXI_ID_WIDTH ( DutCfg.AxiMstIdWidth ),
.AXI_USER_WIDTH ( DutCfg.AxiUserWidth )
) slink_mst (
) slink_mst_vip_dv (
.clk_i ( clk )
);

AXI_BUS #(
.AXI_ADDR_WIDTH ( DutCfg.AddrWidth ),
.AXI_DATA_WIDTH ( DutCfg.AxiDataWidth ),
.AXI_ID_WIDTH ( DutCfg.AxiMstIdWidth ),
.AXI_USER_WIDTH ( DutCfg.AxiUserWidth )
) slink_mst_ext(), slink_mst_vip(), slink_mst();

AXI_BUS #(
.AXI_ADDR_WIDTH ( DutCfg.AddrWidth ),
.AXI_DATA_WIDTH ( DutCfg.AxiDataWidth ),
.AXI_ID_WIDTH ( DutCfg.AxiMstIdWidth+1 ),
.AXI_USER_WIDTH ( DutCfg.AxiUserWidth )
) slink_mst_mux();

AXI_BUS_DV #(
.AXI_ADDR_WIDTH ( DutCfg.AddrWidth ),
.AXI_DATA_WIDTH ( DutCfg.AxiDataWidth ),
Expand All @@ -565,6 +586,44 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
.clk_i ( clk )
);

// Multiplex internal and external AXI requests
axi_mux_intf #(
.SLV_AXI_ID_WIDTH ( DutCfg.AxiMstIdWidth ),
.MST_AXI_ID_WIDTH ( DutCfg.AxiMstIdWidth+1 ),
.AXI_ADDR_WIDTH ( DutCfg.AddrWidth ),
.AXI_DATA_WIDTH ( DutCfg.AxiDataWidth ),
.AXI_USER_WIDTH ( DutCfg.AxiUserWidth ),
.NO_SLV_PORTS ( 2 )
) i_axi_mux_slink (
.clk_i ( clk ),
.rst_ni ( rst_n ),
.test_i ( test_mode ),
.slv ( '{slink_mst_vip, slink_mst_ext} ),
.mst ( slink_mst_mux )
);

// Serialize away added AXI index bits
axi_id_serialize_intf #(
.AXI_SLV_PORT_ID_WIDTH ( DutCfg.AxiMstIdWidth+1 ),
.AXI_SLV_PORT_MAX_TXNS ( SlinkMaxTxns ),
.AXI_MST_PORT_ID_WIDTH ( DutCfg.AxiMstIdWidth ),
.AXI_MST_PORT_MAX_UNIQ_IDS ( 2**DutCfg.AxiMstIdWidth ),
.AXI_MST_PORT_MAX_TXNS_PER_ID ( SlinkMaxTxnsPerId ),
.AXI_ADDR_WIDTH ( DutCfg.AddrWidth ),
.AXI_DATA_WIDTH ( DutCfg.AxiDataWidth ),
.AXI_USER_WIDTH ( DutCfg.AxiUserWidth )
) i_axi_id_serialize_slink (
.clk_i ( clk ),
.rst_ni ( rst_n ),
.slv ( slink_mst_mux ),
.mst ( slink_mst )
);

`AXI_ASSIGN (slink_mst_vip, slink_mst_vip_dv)

`AXI_ASSIGN_FROM_REQ(slink_mst_ext, axi_slink_mst_req)
`AXI_ASSIGN_TO_RESP(axi_slink_mst_rsp, slink_mst_ext)

`AXI_ASSIGN_TO_REQ(slink_axi_mst_req, slink_mst)
`AXI_ASSIGN_FROM_RESP(slink_mst, slink_axi_mst_rsp)

Expand Down Expand Up @@ -643,7 +702,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
.TT ( ClkPeriodSys * TTest )
) slink_axi_driver_t;

slink_axi_driver_t slink_axi_driver = new (slink_mst);
slink_axi_driver_t slink_axi_driver = new (slink_mst_vip_dv);

initial begin
@(negedge rst_n);
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