Skip to content

Commit

Permalink
tmp commit
Browse files Browse the repository at this point in the history
  • Loading branch information
@MaistoV
MaistoV committed Dec 2, 2023
1 parent de2e08e commit c5b0089
Show file tree
Hide file tree
Showing 24 changed files with 454 additions and 82 deletions.
6 changes: 3 additions & 3 deletions Bender.lock
View file
Original file line number Diff line number Diff line change
Expand Up @@ -46,8 +46,8 @@ packages:
- register_interface
- tech_cells_generic
axi_riscv_atomics:
revision: c3c3f2b65071841035c4e081c61c9b7be801d749
version: 0.8.1
revision: 0ac3a78fe342c5a5b9b10bff49d58897f773059e
version: 0.8.2
source:
Git: https://github.com/pulp-platform/axi_riscv_atomics.git
dependencies:
Expand Down Expand Up @@ -130,7 +130,7 @@ packages:
- register_interface
irq_router:
revision: d1d31350b24f3965b3a51e1bc96c71eb34e94db3
version: null
version: 0.0.1-beta.1
source:
Git: https://github.com/pulp-platform/irq_router.git
dependencies:
Expand Down
11 changes: 6 additions & 5 deletions Bender.yml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,22 +13,22 @@ package:

dependencies:
apb_uart: { git: "https://github.com/pulp-platform/apb_uart.git", version: 0.2.1 }
axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.0 }
axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.0 }
axi_llc: { git: "https://github.com/pulp-platform/axi_llc.git", version: 0.2.1 }
axi_riscv_atomics: { git: "https://github.com/pulp-platform/axi_riscv_atomics.git", version: 0.8.1 }
axi_riscv_atomics: { git: "https://github.com/pulp-platform/axi_riscv_atomics.git", version: =0.8.1 }
axi_vga: { git: "https://github.com/pulp-platform/axi_vga.git", version: 0.1.1 }
clint: { git: "https://github.com/pulp-platform/clint.git", version: ^0.2.0 }
clint: { git: "https://github.com/pulp-platform/clint.git", version: 0.2.0 }
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 }
common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 }
cva6: { git: "https://github.com/MaistoV/cva6_fork.git", rev: "ara_cheshire" }
ara: { git: "https://github.com/MaistoV/ara_fork.git", rev: "ara_cheshire" }
iDMA: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9 } # TODO: master commit; use next release once out
opentitan_peripherals: { git: "https://github.com/pulp-platform/opentitan_peripherals.git", version: 0.4.0 }
register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: ^0.4.1 }
register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: =0.4.1 }
riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.0 }
serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.0 }
clic: { git: "https://github.com/pulp-platform/clic.git", version: 2.0.0 }
irq_router: { git: "https://github.com/pulp-platform/irq_router.git", rev: d1d3135 } # TODO: master commit; use next release once out
irq_router: { git: "https://github.com/pulp-platform/irq_router.git", rev: =0.0.1-beta.1 } # TODO: master commit; use next release once out

export_include_dirs:
- hw/include
Expand All @@ -42,6 +42,7 @@ sources:
- hw/regs/axi_rt_reg_top.sv
- hw/cheshire_pkg.sv
- hw/cheshire_soc.sv
- hw/mmu_stub.sv

- target: any(simulation, test)
files:
Expand Down
19 changes: 17 additions & 2 deletions RVV_TEST.md
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
# RVV_TEST light-weight framework
> **_NOTE:_** This is not close to what a structured verification pipeline should look like, but it is an acceptable solution for the short time frames we have.
> **NOTE:** This is not close to what a structured verification pipeline should look like, but it is an acceptable solution for the short time frames we have.
A set of utility make targets are defined to build and automate the tests for the extensions performed on Ara integrated in Cheshire and perform regression.

Expand Down Expand Up @@ -55,4 +55,19 @@ Unset these variables for subsequent runs:
````console
$ unset RVV_TEST RVV_TEST_ELF VSIM_ARGS ARA_NR_LANES TEST_COMMENT
````


# MMU Stub
The design features a stub MMU in `cheshire_soc`, attached to Ara MMU port, which emulates address translation and exception page fault generation.

- This module is instatiated only if the variable `MMU_STUB` is defined and equals `1`. If not so, instructions in the next bullets will cause the simulation build to fail. Otherwise its outputs are tied to zero.

> TODO: route its I/O to CVA6
- Emulated translation is enabled only if the test name, i.e., the .c source, contains the string `mmu_stub`. E.g., `rvv_test_mmu_stub.c`.

- Page faults are unconditionally generated if the test name **also** contains the string `page_fault`. E.g., `rvv_test_mmu_stub_page_fault.c`.

Rebember to unset the `MMU_STUB` variable if necessary.
````console
$ unset MMU_STUB
````
11 changes: 10 additions & 1 deletion hw/cheshire_soc.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -729,8 +729,9 @@ module cheshire_soc import cheshire_pkg::*; #(
.axi_resp_i ( axi_ara_wide_resp )
);


// DEBUG: MMU stub
// TODO: instantiate conditionally
`ifdef MMU_STUB
mmu_stub i_mmu_stub (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
Expand All @@ -746,6 +747,14 @@ module cheshire_soc import cheshire_pkg::*; #(
.paddr_o ( mmu_paddr_cva6_acc ),
.exception_o ( mmu_exception_cva6_acc )
);
`else // !MMU_STUB
// TODO: route these to CVA6
assign mmu_dtlb_hit_cva6_acc = '0;
assign mmu_dtlb_ppn_cva6_acc = '0;
assign mmu_valid_cva6_acc = '0;
assign mmu_paddr_cva6_acc = '0;
assign mmu_exception_cva6_acc = '0;
`endif // MMU_STUB

// Issue invalidations to CVA6 L1D$
axi_inval_filter #(
Expand Down
20 changes: 11 additions & 9 deletions hw/mmu_stub.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,8 +9,8 @@
module mmu_stub (
input logic clk_i,
input logic rst_ni,
input logic en_ld_st_translation_i, // Enable bahaviour
input logic trigger_exception_i, // Emulate exception generation on requests
input logic en_ld_st_translation_i, // Enable behaviour
input logic trigger_exception_i, // Emulate exception generation on requests (load/store page faults)

Check warning on line 13 in hw/mmu_stub.sv

View workflow job for this annotation

GitHub Actions / lint-sv 

[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 135 [Style: line-length] [line-length]

Raw Output:
message:"Line length exceeds max: 100; is: 135 [Style: line-length] [line-length]" location:{path:"hw/mmu_stub.sv" range:{start:{line:13 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
input ariane_pkg::exception_t misaligned_ex_i, // Ignored
input logic req_i,
input logic [riscv::VLEN-1:0] vaddr_i,
Expand All @@ -29,9 +29,11 @@ module mmu_stub (
logic [riscv::PLEN-1:0] mock_paddr_d, mock_paddr_q;
logic [riscv::VLEN-1:0] vaddr_d, vaddr_q;
logic valid_d, valid_q;
logic is_store_q, is_store_d;
`FF(mock_paddr_q, mock_paddr_d, '0, clk_i, rst_ni)
`FF(vaddr_q , vaddr_d , '0, clk_i, rst_ni)
`FF(valid_q , valid_d , '0, clk_i, rst_ni)
`FF(is_store_q , is_store_d , '0, clk_i, rst_ni)

// Combinatorial logic
always_comb begin : mmu_stub
Expand All @@ -46,19 +48,19 @@ module mmu_stub (
mock_paddr_d = mock_paddr_q;
valid_d = valid_q;
vaddr_d = vaddr_q;
is_store_d = is_store_q;

// If trasnlation is enabled
if ( en_ld_st_translation_i ) begin : enable_translation
// Cycle 0
if ( req_i ) begin : req_valid
// For next cycle
// Sample inputs, for next cycle
mock_paddr_d = vaddr_i; // Mock, just pass back the same vaddr
vaddr_d = vaddr_i;
is_store_d = is_store_i;

// Pull up valid
valid_d = 1'b1;
// Mock, just pass back the same vaddr
mock_paddr_d = vaddr_i;

// Sample vaddr_i in case of exception
vaddr_d = vaddr_i;

// DTBL hit, assume 100%
// NOTE: Ara does not use these
Expand All @@ -79,7 +81,7 @@ module mmu_stub (
// Mock exception logic
if ( trigger_exception_i & valid_q ) begin : exception
exception_o.valid = 1'b1;
exception_o.cause = ( is_store_i ) ? riscv::STORE_PAGE_FAULT : riscv::LOAD_PAGE_FAULT;
exception_o.cause = ( is_store_q ) ? riscv::STORE_PAGE_FAULT : riscv::LOAD_PAGE_FAULT;
exception_o.tval = {'0, vaddr_q};
end : exception
end : enable_translation
Expand Down
4 changes: 2 additions & 2 deletions sw/sw.mk
View file
Original file line number Diff line number Diff line change
Expand Up @@ -93,10 +93,10 @@ CHS_SW_GEN_HDRS += $(OTPROOT)/.generated
# TODO: track headers with gcc -MM!

# All objects require up-to-date patches and headers
%.o: %.c $(CHS_SW_GEN_HDRS)
%.o: %.c $(CHS_SW_GEN_HDRS) $(CHS_SW_RVV_TEST_HDRS)
$(CHS_SW_CC) $(CHS_SW_INCLUDES) $(CHS_SW_CCFLAGS) -c $< -o $@

%.o: %.S $(CHS_SW_GEN_HDRS)
%.o: %.S $(CHS_SW_GEN_HDRS) $(CHS_SW_RVV_TEST_HDRS)
$(CHS_SW_CC) $(CHS_SW_INCLUDES) $(CHS_SW_CCFLAGS) -c $< -o $@

define chs_ld_elf_rule
Expand Down
Binary file added sw/tests/mock_rvv_test_vstart_indexed
View file
Binary file not shown.
Loading

0 comments on commit c5b0089

Please sign in to comment.