Dev/v2023.2 (#18)

Libero Scripted Designs Update for v2023.2 MIV_RV32 in the designs has been updated from: v3.1.100 to v3.1.200. MIV_ESS in the designs has been updated from: v2.0.100 to v2.0.200. Updated Out-of-box example using the CoreTimer example for MIV_RV32. After programming the bitstream, software boots out of the box from the LSRAM. FlashPro_Express_Projects have been updated to reflect the latest design changes Readme files updated. --------- Co-authored-by: Ciaran Lappin <[email protected]>
Mi-V-Soft-RISC-V · Oct 31, 2023 · 4201b75 · 4201b75
1 parent c5c9ae8
commit 4201b75
Show file tree

Hide file tree

Showing 28 changed files with 30,067 additions and 1,058 deletions.
diff --git a/FlashPro_Express_Projects/Programming_Files/PF_SPLASH_MIV_RV32IMAF_CFG1_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_SPLASH_MIV_RV32IMAF_CFG1_BaseDesign.job
diff --git a/FlashPro_Express_Projects/Programming_Files/PF_SPLASH_MIV_RV32IMA_CFG1_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_SPLASH_MIV_RV32IMA_CFG1_BaseDesign.job
diff --git a/FlashPro_Express_Projects/Programming_Files/PF_SPLASH_MIV_RV32IMA_CFG2_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_SPLASH_MIV_RV32IMA_CFG2_BaseDesign.job
diff --git a/FlashPro_Express_Projects/Programming_Files/PF_SPLASH_MIV_RV32_CFG1_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_SPLASH_MIV_RV32_CFG1_BaseDesign.job
diff --git a/FlashPro_Express_Projects/Programming_Files/PF_SPLASH_MIV_RV32_CFG2_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_SPLASH_MIV_RV32_CFG2_BaseDesign.job
diff --git a/FlashPro_Express_Projects/Programming_Files/PF_SPLASH_MIV_RV32_CFG3_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_SPLASH_MIV_RV32_CFG3_BaseDesign.job
diff --git a/FlashPro_Express_Projects/README.md b/FlashPro_Express_Projects/README.md
@@ -1,11 +1,11 @@
 # PolarFire FPGA Splash-Kit FPGA Programming Files
 
-This folder contains FlashPro Express v2023.1 projects for the PolarFire FPGA Splash-Kit Mi-V sample designs.
+This folder contains FlashPro Express v2023.2 projects for the PolarFire FPGA Splash-Kit Mi-V sample designs.
 
 ## Notice
-1) Due to an issues found in the MIV_RV32 v3.1.100 with the MTVECs address, it is not recommended to use MIV_RV32 v3.1.100 for any FreeRTOS examples. You may continue to use MIV_RV32 v3.0 with FreeRTOS examples. 
+1) Due to an issue specific to the MIV_RV32 v3.1.100 with the MTVECs address, it is not recommended to use MIV_RV32 v3.1.100 for any FreeRTOS examples. You may use MIV_RV32 v3.0 or the latest MIV_RV32 v3.1.200 with the FreeRTOS examples. 
 
-2) There is also an issue which effects all MIV_RV32 cores, when using fast interrupts where the return address can become corrupted. There software workaround can be applied in the entry.S in MIV_RV32 HAL file as shown below untill the issue is fixed in the IP.
+2) There is also an issue which effects all MIV_RV32 cores up to v3.1.100, when using fast interrupts where the return address can become corrupted. There software workaround can be applied in the entry.S in MIV_RV32 HAL file as shown below until the issue is fixed in the IP.
 
 .macro STORE_CONTEXT
 addi sp, sp, -SP_SHIFT_OFFSET*REGBYTES
@@ -74,4 +74,4 @@ The peripherals in this design are located at the following addresses.
 | CoreTimer_0            | 0x7000_3000   |
 | CoreTimer_1            | 0x7000_4000   |
 | CoreGPIO_OUT           | 0x7000_5000   |
-| SRAM                   | 0x8000_0000   |
+| SRAM                   | 0x8000_0000   |
diff --git a/Libero_Projects/PF_Splash_Kit_MIV_RV32_BaseDesign.tcl b/Libero_Projects/PF_Splash_Kit_MIV_RV32_BaseDesign.tcl
@@ -19,7 +19,7 @@ set validConfigs [list "CFG1" "CFG2" "CFG3"]
 set validDesignFlows [list "SYNTHESIZE" "PLACE_AND_ROUTE" "GENERATE_BITSTREAM" "EXPORT_PROGRAMMING_FILE"]
 set validDieTypes [list "PS" "ES" ""]
 set sdName {BaseDesign}
-set exProgramHex "miv-rv32i-systick-blinky.hex"
+set exProgramHex "miv-rv32-coretimer-timer_interrupt.hex"
 
 # Call procedures to validate user arguments
 set config [verify_config $config]

diff --git a/Libero_Projects/README.md b/Libero_Projects/README.md
@@ -1,10 +1,10 @@
 # PolarFire FPGA Splash-Kit Mi-V Sample FPGA Designs
-This folder contains Tcl scripts that build Libero SoC v2023.1 design projects for the PolarFire FPGA Splash-Kit. These scripts are executed in Libero SoC to generate the sample designs. All cores boot from memory at 0x8000_0000.
+This folder contains Tcl scripts that build Libero SoC v2023.2 design projects for the PolarFire FPGA Splash-Kit. These scripts are executed in Libero SoC to generate the sample designs. All cores boot from memory at 0x8000_0000.
 
 ## Notice
-1) Due to an issues found in the MIV_RV32 v3.1.100 with the MTVECs address, it is not recommended to use MIV_RV32 v3.1.100 for any FreeRTOS examples. You may continue to use MIV_RV32 v3.0 with FreeRTOS examples. 
+1) Due to an issue specific to the MIV_RV32 v3.1.100 with the MTVECs address, it is not recommended to use MIV_RV32 v3.1.100 for any FreeRTOS examples. You may use MIV_RV32 v3.0 or the latest MIV_RV32 v3.1.200 with the FreeRTOS examples. 
 
-2) There is also an issue which effects all MIV_RV32 cores, when using fast interrupts where the return address can become corrupted. There software workaround can be applied in the entry.S in MIV_RV32 HAL file as shown below untill the issue is fixed in the IP.
+2) There is also an issue which effects all MIV_RV32 cores up to v3.1.100, when using fast interrupts where the return address can become corrupted. There software workaround can be applied in the entry.S in MIV_RV32 HAL file as shown below until the issue is fixed in the IP.
 
 .macro STORE_CONTEXT
 addi sp, sp, -SP_SHIFT_OFFSET*REGBYTES

diff --git a/Libero_Projects/import/components/CoreAHBL_C0.tcl b/Libero_Projects/import/components/CoreAHBL_C0.tcl
@@ -1,6 +1,6 @@
 # Exporting core CoreAHBL_0 to TCL
 # Exporting Create design command for core CoreAHBL_0
-create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAHBLite:5.6.105} -download_core -component_name {CoreAHBL_C0} -params {\
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAHBLite:6.1.101} -download_core -component_name {CoreAHBL_C0} -params {\
 "HADDR_SHG_CFG:1"  \
 "M0_AHBSLOT0ENABLE:false"  \
 "M0_AHBSLOT1ENABLE:false"  \

diff --git a/Libero_Projects/import/components/MIV_ESS_C0.tcl b/Libero_Projects/import/components/MIV_ESS_C0.tcl
@@ -2,7 +2,7 @@
 # Family: PolarFire
 # Part Number: MPF300TS-FCG484I
 # Create and Configure the core component MIV_ESS_0
-create_and_configure_core -core_vlnv {Actel:SystemBuilder:MIV_ESS:2.0.100} -component_name {MIV_ESS_C0} -download_core -params {\
+create_and_configure_core -core_vlnv {Actel:SystemBuilder:MIV_ESS:2.0.200} -component_name {MIV_ESS_C0} -download_core -params {\
 "APBSLOT11ENABLE:false" \
 "APBSLOT12ENABLE:false" \
 "APBSLOT13ENABLE:false" \

diff --git a/Libero_Projects/import/components/MIV_RV32_CFG1_C0.tcl b/Libero_Projects/import/components/MIV_RV32_CFG1_C0.tcl
@@ -1,6 +1,6 @@
 # Exporting core MIV_RV32_CFG1_0 to TCL
 # Exporting Create design command for core MIV_RV32_CFG1_0
-create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.100} -download_core -component_name {MIV_RV32_CFG1_C0} -params {\
+create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.200} -download_core -component_name {MIV_RV32_CFG1_C0} -params {\
 "AHB_END_ADDR_0:0xffff"  \
 "AHB_END_ADDR_1:0x8fff"  \
 "AHB_INITIATOR_TYPE:1"  \

diff --git a/Libero_Projects/import/components/MIV_RV32_CFG2_C0.tcl b/Libero_Projects/import/components/MIV_RV32_CFG2_C0.tcl
@@ -1,6 +1,6 @@
 # Exporting core MIV_RV32_CFG2_0 to TCL
 # Exporting Create design command for core MIV_RV32_CFG2_0
-create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.100} -download_core -component_name {MIV_RV32_CFG2_C0} -params {\
+create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.200} -download_core -component_name {MIV_RV32_CFG2_C0} -params {\
 "AHB_END_ADDR_0:0xffff"  \
 "AHB_END_ADDR_1:0x8fff"  \
 "AHB_INITIATOR_TYPE:0"  \

diff --git a/Libero_Projects/import/components/MIV_RV32_CFG3_C0.tcl b/Libero_Projects/import/components/MIV_RV32_CFG3_C0.tcl
@@ -1,6 +1,6 @@
 # Exporting core MIV_RV32_CFG3_0 to TCL
 # Exporting Create design command for core MIV_RV32_CFG3_0
-create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.100} -download_core -component_name {MIV_RV32_CFG3_C0} -params {\
+create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.200} -download_core -component_name {MIV_RV32_CFG3_C0} -params {\
 "AHB_END_ADDR_0:0xffff"  \
 "AHB_END_ADDR_1:0x8fff"  \
 "AHB_INITIATOR_TYPE:0"  \

diff --git a/Libero_Projects/import/proc_blocks.tcl b/Libero_Projects/import/proc_blocks.tcl
@@ -190,11 +190,10 @@ proc download_required_direct_cores  {hwPlatform softCpu config} {
 	download_core -vlnv {Actel:DirectCore:COREAXITOAHBL:3.6.101} -location {www.microchip-ip.com/repositories/DirectCore}
 	download_core -vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -location {www.microchip-ip.com/repositories/DirectCore}
 	download_core -vlnv {Actel:DirectCore:COREAHBTOAPB3:3.2.101} -location {www.microchip-ip.com/repositories/DirectCore}
-	download_core -vlnv {Actel:DirectCore:CoreAHBLite:5.6.105} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:CoreAHBLite:5.1.101} -location {www.microchip-ip.com/repositories/DirectCore}
     if {$softCpu eq "MIV_RV32"} {
-        download_core -vlnv {Microsemi:MiV:MIV_RV32:3.1.100} -location {www.microchip-ip.com/repositories/DirectCore} 
-        download_core -vlnv {Actel:SystemBuilder:MIV_ESS:2.0.100} -location {www.microchip-ip.com/repositories/SgCore}
-        download_core -vlnv {Actel:SystemBuilder:MIV_ESS:2.0.100} -location {www.microchip-ip.com/repositories/SgCore}  
+        download_core -vlnv {Microsemi:MiV:MIV_RV32:3.1.200} -location {www.microchip-ip.com/repositories/DirectCore} 
+        download_core -vlnv {Actel:SystemBuilder:MIV_ESS:2.0.200} -location {www.microchip-ip.com/repositories/SgCore} 
     }
 	if {$softCpu eq "MIV_RV32IMA_L1_AHB"} {download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AHB:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore} }
 	if {$softCpu eq "MIV_RV32IMA_L1_AXI"} {download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AXI:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore} }
@@ -241,4 +240,4 @@ proc run_verify_timing { } {
 	run_tool -name {VERIFYTIMING}	
 }
 # Procedure blocks end
-#
+#