Dev/v2024.2 (#20)

Libero SoC 2024.2 Update * Updating the version number of LiberoSoC v2024.1 to LiberoSoC v2024.2 * Legacy Core Designs Removed * Updating with latest FPExpress Jobs
Mi-V-Soft-RISC-V · Nov 15, 2024 · 5d9d11c · 5d9d11c
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diff --git a/FlashPro_Express_Projects/Programming_Files/PF_SPLASH_MIV_RV32IMAF_CFG1_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_SPLASH_MIV_RV32IMAF_CFG1_BaseDesign.job
diff --git a/FlashPro_Express_Projects/Programming_Files/PF_SPLASH_MIV_RV32IMA_CFG1_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_SPLASH_MIV_RV32IMA_CFG1_BaseDesign.job
diff --git a/FlashPro_Express_Projects/Programming_Files/PF_SPLASH_MIV_RV32IMA_CFG2_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_SPLASH_MIV_RV32IMA_CFG2_BaseDesign.job
diff --git a/FlashPro_Express_Projects/Programming_Files/PF_SPLASH_MIV_RV32_CFG1_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_SPLASH_MIV_RV32_CFG1_BaseDesign.job
diff --git a/FlashPro_Express_Projects/Programming_Files/PF_SPLASH_MIV_RV32_CFG2_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_SPLASH_MIV_RV32_CFG2_BaseDesign.job
diff --git a/FlashPro_Express_Projects/Programming_Files/PF_SPLASH_MIV_RV32_CFG3_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_SPLASH_MIV_RV32_CFG3_BaseDesign.job
diff --git a/FlashPro_Express_Projects/README.md b/FlashPro_Express_Projects/README.md
@@ -1,6 +1,6 @@
 # PolarFire FPGA Splash-Kit FPGA Programming Files
 
-This folder contains FlashPro Express v2024.1 projects for the PolarFire FPGA Splash-Kit Mi-V sample designs.
+This folder contains FlashPro Express v2024.2 projects for the PolarFire FPGA Splash-Kit Mi-V sample designs.
 
 ## FlashPro Express
 The programming files contained under this folder were exported from the designs in the Libero_Projects folder in this repository. Select the desired programming file (.job) and program your device using FlashPro Express.
@@ -48,14 +48,3 @@ The peripherals in this design are located at the following addresses.
 | MIV_ESS_APBSLOTE_BASE            | 0x7E00_0000   | 0x7EFF_FFFF    |
 | MIV_ESS_APBSLOTF_BASE            | 0x7F00_0000   | 0x7FFF_FFFF    |
 | SRAM/TCM                         | 0x8000_0000   | 0x8000_7FFF    |
-
-
-#### Legacy core based configurations:
-| Peripheral (Standalone)| Address       |
-| ----------------------:|:-------------:|
-| CoreUARTapb            | 0x7000_1000   |
-| CoreGPIO_IN            | 0x7000_2000   |
-| CoreTimer_0            | 0x7000_3000   |
-| CoreTimer_1            | 0x7000_4000   |
-| CoreGPIO_OUT           | 0x7000_5000   |
-| SRAM                   | 0x8000_0000   |
diff --git a/Libero_Projects/PF_Splash_Kit_MIV_RV32IMAF_BaseDesign.tcl b/Libero_Projects/PF_Splash_Kit_MIV_RV32IMAF_BaseDesign.tcl
diff --git a/Libero_Projects/PF_Splash_Kit_MIV_RV32IMA_BaseDesign.tcl b/Libero_Projects/PF_Splash_Kit_MIV_RV32IMA_BaseDesign.tcl
diff --git a/Libero_Projects/README.md b/Libero_Projects/README.md
@@ -1,5 +1,5 @@
 # PolarFire FPGA Splash-Kit Mi-V Sample FPGA Designs
-This folder contains Tcl scripts that build Libero SoC v2024.1 design projects for the PolarFire FPGA Splash-Kit. These scripts are executed in Libero SoC to generate the sample designs. All cores boot from memory at 0x8000_0000.
+This folder contains Tcl scripts that build Libero SoC v2024.2 design projects for the PolarFire FPGA Splash-Kit. These scripts are executed in Libero SoC to generate the sample designs. All cores boot from memory at 0x8000_0000.
 
 #### PF_Splash_Kit_MIV_RV32_BaseDesign
 
@@ -9,22 +9,6 @@ This folder contains Tcl scripts that build Libero SoC v2024.1 design projects f
 | CFG2    | This design uses the MIV_RV32 core configured as follows: <ul><li>RISC-V Extensions: IM</li><li>Multiplier: Fabric</li><li>Interfaces: AXI4 Master (mirrored), APB3 Initiator</li><li>Internal IRQs: 1</li><li>TCM: Disabled</li><li>System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled</li><li>Debug: Enabled</li><li>An example program is stored in the LSRAM to boot out the box</ul>|
 | CFG3    | This design uses the MIV_RV32 core configured as follows: <ul><li>RISC-V Extensions: I</li><li>Multiplier: none</li><li>Interfaces: APB3 Initiator</li><li>Internal IRQs: 1</li><li>TCM: enabled</li><li>System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled</li><li>Debug: Enabled</li></ul>|
 
-
-#### PF_Splash_Kit_MIV_RV32IMA_BaseDesign
-
-| Config  | Description |
-| :------:|:------------|
-| CFG1    |This design uses the MIV_RV32IMA_L1_AHB core with an **AHB** interface for memory and peripherals. <li>An example program is stored in the LSRAM to boot out the box|
-| CFG2    |This design uses the MIV_RV32IMA_L1_AXI core with an **AXI3** interface for memory and peripherals. <li>An example program is stored in the LSRAM to boot out the box|
-
-
-#### PF_Splash_Kit_MIV_RV32IMAF_BaseDesign
-
-| Config  |Description |
-| :------:|:-----------|
-| CFG1    |  This design uses the MIV_RV32IMAF_L1_AHB core with an **AHB** interface for memory and peripherals. <li>An example program is stored in the LSRAM to boot out the box|
-
-
 ## <a name="quick"></a> Instructions
 
 #### Running Libero SoC in GUI mode
@@ -107,12 +91,3 @@ The peripherals in this design are located at the following addresses.
 | SRAM/TCM                         | 0x8000_0000   | 0x8000_7FFF    |
 
 
-#### Legacy core based configurations:
-| Peripheral (Standalone)| Address       |
-| ----------------------:|:-------------:|
-| CoreUARTapb            | 0x7000_1000   |
-| CoreGPIO_IN            | 0x7000_2000   |
-| CoreTimer_0            | 0x7000_3000   |
-| CoreTimer_1            | 0x7000_4000   |
-| CoreGPIO_OUT           | 0x7000_5000   |
-| SRAM                   | 0x8000_0000   |