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Improve_synthesizer_sound
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Improve synthesizer sound
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sorgelig authored Mar 23, 2023
2 parents d17b8dd + 42025bd commit 8947c8a
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Showing 9 changed files with 423 additions and 76 deletions.
10 changes: 5 additions & 5 deletions Arcade-DonkeyKong.sv
Original file line number Diff line number Diff line change
Expand Up @@ -194,7 +194,7 @@ wire [1:0] ar = status[20:19];
assign VIDEO_ARX = (!ar) ? ((status[2]|mod_pestplace) ? 8'd8 : 8'd7) : (ar - 1'd1);
assign VIDEO_ARY = (!ar) ? ((status[2]|mod_pestplace) ? 8'd7 : 8'd8) : 12'd0;

`include "build_id.v"
`include "build_id.v"
localparam CONF_STR = {
"A.DKONG;;",
"H0OJK,Aspect ratio,Original,Full Screen,[ARC1],[ARC2];",
Expand Down Expand Up @@ -294,7 +294,7 @@ reg mod_pestplace=0;
always @(posedge clk_sys) begin
reg [7:0] mod = 0;
if (ioctl_wr & (ioctl_index==1)) mod <= ioctl_dout;

mod_dk <= (mod == 0);
mod_dkjr <= (mod == 1);
mod_dk3 <= (mod == 2);
Expand Down Expand Up @@ -371,7 +371,7 @@ arcade_video #(256,12) arcade_video
wire [15:0] audio;
assign AUDIO_L = audio;
assign AUDIO_R = AUDIO_L;
assign AUDIO_S = 0;
assign AUDIO_S = 1;

assign hblank = hbl[8];

Expand Down Expand Up @@ -436,15 +436,15 @@ dpram #(16,8) wav_rom (



dkong_top dkong(
dkong_top dkong(
.I_CLK_24576M(clk_sys),
.I_RESETn(~reset),
.I_U1(~m_up),
.I_D1(~m_down),
.I_L1(~m_left),
.I_R1(~m_right),
.I_J1(~m_fire),

.I_U2(~m_up_2),
.I_D2(~m_down_2),
.I_L2(~m_left_2),
Expand Down
2 changes: 2 additions & 0 deletions files.qip
Original file line number Diff line number Diff line change
Expand Up @@ -12,6 +12,8 @@ set_global_assignment -name VERILOG_FILE rtl/dkong_hv_count.v
set_global_assignment -name VERILOG_FILE rtl/dkong_col_pal.v
set_global_assignment -name VERILOG_FILE rtl/dkong_bram.v
set_global_assignment -name VERILOG_FILE rtl/dkong_adec.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/dkongjr_dac.sv
set_global_assignment -name VERILOG_FILE rtl/dkongjr_iir_filter.v
set_global_assignment -name VERILOG_FILE rtl/radarscp_stars.v
set_global_assignment -name QIP_FILE rtl/t48/T48.qip
set_global_assignment -name QIP_FILE rtl/T80/T80.qip
Expand Down
Binary file added releases/Arcade-DonkeyKong_20221120.rbf
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10 changes: 5 additions & 5 deletions rtl/dkong_sound.v
Original file line number Diff line number Diff line change
@@ -1,22 +1,22 @@
//===============================================================================
// FPGA DONKEY KONG SOUND_I/F
//
// Version : 4.00
// Version : 4.00
//
// Copyright(c) 2003 - 2004 Katsumi Degawa , All rights reserved
//
// Important !
//
// This program is freeware for non-commercial use.
// This program is freeware for non-commercial use.
// An author does no guarantee about this program.
// You can use this under your own risk.
//
// 2004- 9- 2 T48-IP(beta3) was include. K.Degawa
// 2004- 9-14 T48-IP was changed to beta4. K.Degawa
// 2005- 2- 9 The description of the ROM was changed.
// Data on the ROM are initialized at the time of the start.
// Data on the ROM are initialized at the time of the start.
//================================================================================

module dkong_sound(
input I_CLK,
input I_RST,
Expand Down Expand Up @@ -67,7 +67,7 @@ assign ROM_A = {I_DKJR ? I8035_PBI[3] : I8035_PSENn,S_ROM_A};
reg S_D1_CS;
always@(posedge I_CLK) S_D1_CS <= (I_DKJR | I8035_PBI[6])&(~I8035_RDn);

wire [7:0]S_D1 = S_D1_CS ? {3'h0,~I_SOUND_DAT[4:0]}: 8'h00 ;
wire [7:0]S_D1 = S_D1_CS ? {3'h0,~I_SOUND_DAT[4:0]}: 8'h00 ;

wire [7:0]S_PROG_DB;
wire [7:0]S_PROG_D = I8035_PSENn ? 8'h00 : S_PROG_DB ;
Expand Down
92 changes: 72 additions & 20 deletions rtl/dkong_soundboard.sv
Original file line number Diff line number Diff line change
@@ -1,15 +1,17 @@
module dkong_soundboard(
module dkong_soundboard #(
W_CLK_24576M_RATE = 24576000 // Hz
) (
input W_CLK_24576M,
input W_RESETn,
input I_DKJR,
input I_DKJR, /// 1 = Emulate Donkey Kong JR, 3 or PestPlace (async not a problem)
input W_W0_WE,
input W_W1_WE,
input W_CNF_EN,
input [6:0] W_6H_Q,
input W_5H_Q0,
input [1:0] W_4H_Q,
input [4:0] W_3D_Q,
output [15:0] O_SOUND_DAT,
output reg [15:0] O_SOUND_DAT,
output O_SACK,
output [11:0] ROM_A,
input [7:0] ROM_D,
Expand All @@ -33,11 +35,17 @@ wire I8035_T0;
wire I8035_T1;
wire I8035_RSTn;

reg [1:0] cnt;
// emulate 6 MHz crystal oscillor
localparam increment_width = 17; // ceil(RATE_decimal_precision * 3.32192)
reg [increment_width:0] count; // one longer for overflow bit.
localparam X1_RATE = 6000000;
localparam [increment_width:0] increment = (X1_RATE / W_CLK_24576M_RATE) * 2**increment_width;

always @(posedge W_CLK_24576M) begin
cnt <= cnt + 1'd1;
I8035_CLK_EN <= cnt == 0;
count[increment_width] <= 1'b0; // keep overflow bit for just one cycle
count <= count + increment;
end
assign I8035_CLK_EN = count[increment_width];

I8035IP SOUND_CPU
(
Expand Down Expand Up @@ -73,7 +81,7 @@ dkong_sound Digtal_sound
.I8035_DBO(I8035_DBO),
.I8035_PAI(I8035_PAI),
.I8035_PBI(I8035_PBI),
.I8035_PBO(I8035_PBO),
.I8035_PBO(I8035_PBO),
.I8035_ALE(I8035_ALE),
.I8035_RDn(I8035_RDn),
.I8035_PSENn(I8035_PSENn),
Expand All @@ -88,30 +96,67 @@ dkong_sound Digtal_sound
.ROM_D(ROM_D)
);

dkong_wav_sound Analog_sound
//---- DAC I/F ------------------------

localparam SAMPLE_RATE = 48000;
localparam [8:0] clocks_per_sample = 24000000 / 48000;

wire signed[15:0] W_D_S_DATB;

dkongjr_dac dac08
(
.I_CLK(W_CLK_24576M),
.I_DECAY_EN(~I8035_PBI[7]),
.I_RESET_n(W_RESETn),
.I_SND_DAT({2{~W_D_S_DAT[7],W_D_S_DAT[6:0]}}), // convert 8-bit unsigned to 16-bit signed.
.O_SND_DAT(W_D_S_DATB)
);

// Second order low pass filter. f= 1916 Hz, Q = 0.74.
wire signed[15:0] W_D_S_DATC;
iir_2nd_order filter
(
.O_ROM_AB(WAV_ROM_A),
.I_ROM_DB(WAV_ROM_DO),
.clk(W_CLK_24576M),
.reset(~W_RESETn),
.div({3'd0, clocks_per_sample}),
.A2(-18'sd26649),
.A3(18'sd11453),
.B1(18'sd215),
.B2(18'sd430),
.B3(18'sd215),
.in(W_D_S_DATB),
.out(W_D_S_DATC)
);

// Wav sound recored at 11025 Hz rate, 8 bit unsigned
dkong_wav_sound #(
.CLOCK_RATE(W_CLK_24576M_RATE)
) Analog_sound (
.I_CLK(W_CLK_24576M),
.I_RSTn(W_RESETn),
.I_SW(I_DKJR ? 2'b00 : W_6H_Q[2:1])
.I_SW(I_DKJR ? 2'b00 : W_6H_Q[2:1]),
.O_ROM_AB(WAV_ROM_A)
);

reg[8:0] audio_clk_counter;
wire audio_clk_en;
assign audio_clk_en = audio_clk_counter == 0;
wire signed[15:0] walk_out;

reg audio_clk_en;
always@(posedge W_CLK_24576M, negedge W_RESETn) begin
if(!W_RESETn)begin
audio_clk_en <= 0;
audio_clk_counter <= 0;
end else begin
audio_clk_counter <= audio_clk_counter + 1;
if(audio_clk_counter != (clocks_per_sample - 9'd1))begin
audio_clk_en <= 0;
audio_clk_counter <= audio_clk_counter + 9'd1;
end else begin
audio_clk_en <= 1;
audio_clk_counter <= 0;
end
end
end

dk_walk #(.CLOCK_RATE(24576000),.SAMPLE_RATE(48000)) walk (
wire signed[15:0] walk_out;
dk_walk #(.CLOCK_RATE(W_CLK_24576M_RATE),.SAMPLE_RATE(SAMPLE_RATE)) walk (
.clk(W_CLK_24576M),
.I_RSTn(W_RESETn),
.audio_clk_en(audio_clk_en),
Expand All @@ -120,9 +165,16 @@ dk_walk #(.CLOCK_RATE(24576000),.SAMPLE_RATE(48000)) walk (
);

// SOUND MIXER (WAV + DIG ) -----------------------
wire[14:0] sound_mix = ({1'b0, I_DKJR ? 15'd0 : WAV_ROM_DO, 6'b0} + {1'b0, (W_D_S_DAT >> 1) + (W_D_S_DAT >> 3), 6'b0});
wire signed[15:0] sound_mix_16_bit = sound_mix - 2**14 + walk_out;

assign O_SOUND_DAT = sound_mix_16_bit + 2**15;
wire signed[15:0] sound_mix =
(I_DKJR ? 16'd0 : {{3{~WAV_ROM_DO[7]}}, WAV_ROM_DO[6:0],6'b0}) +
{{3{W_D_S_DATC[15]}},W_D_S_DATC[14:2]} + {{5{W_D_S_DATC[15]}},W_D_S_DATC[14:4]} +
walk_out;

always@(posedge W_CLK_24576M_RATE) begin
if (audio_clk_en) begin
O_SOUND_DAT <= sound_mix;
end
end

endmodule
15 changes: 8 additions & 7 deletions rtl/dkong_top.v
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
//
// Important !
//
// This program is freeware for non-commercial use.
// This program is freeware for non-commercial use.
// An author does no guarantee about this program.
// You can use this under your own risk.
//
Expand All @@ -26,6 +26,7 @@ module dkong_top
(
// FPGA_USE
input I_CLK_24576M,
input I_CLK_24M,
input I_RESETn,
output O_PIX,

Expand Down Expand Up @@ -144,7 +145,7 @@ wire W_CPU_IORQn;
wire W_CPU_MREQn;
wire W_CPU_BUSRQ;
wire W_CPU_BUSAKn;
wire W_CPU_RDn;
wire W_CPU_RDn;
wire W_CPU_WRn;
wire [15:0]W_CPU_A;

Expand All @@ -153,7 +154,7 @@ assign WB_CLK_12288M = W_CLK_12288M; // 12.288MHz
wire W_CPU_CLK_EN_P = W_H_CNT[1:0] == 2'b01;
wire W_CPU_CLK_EN_N = W_H_CNT[1:0] == 2'b11;

T80pa z80core(
T80pa z80core(
.RESET_n(W_RESETn),
.CLK(I_CLK_24576M),
.CEN_p(W_CPU_CLK_EN_N),
Expand Down Expand Up @@ -195,7 +196,7 @@ prog ROM(

always @(*) begin
case({!I_DKJR, W_CPU_A[15:11]})
6'h02: MAIN_CPU_A = {5'h06,W_CPU_A[10:0]}; // 0x1000-0x17FF -> 0x3000-0x37FF in ROM file
6'h02: MAIN_CPU_A = {5'h06,W_CPU_A[10:0]}; // 0x1000-0x17FF -> 0x3000-0x37FF in ROM file
6'h03: MAIN_CPU_A = {5'h0B,W_CPU_A[10:0]}; // 0x1800-0x1FFF -> 0x5800-0x5FFF in ROM file
6'h05: MAIN_CPU_A = {5'h09,W_CPU_A[10:0]}; // 0x2800-0x2FFF -> 0x4800-0x4FFF in ROM file
6'h06: MAIN_CPU_A = {5'h02,W_CPU_A[10:0]}; // 0x3000-0x37FF -> 0x1000-0x17FF in ROM file
Expand Down Expand Up @@ -370,7 +371,7 @@ dkong_adec adec
.I_DK3B(I_DK3B),
.I_PESTPLCE(I_PESTPLCE),
.I_AB(W_CPU_A),
.I_DB(WI_D),
.I_DB(WI_D),
.I_MREQ_n(W_CPU_MREQn),
.I_RFSH_n(W_CPU_RFSHn),
.I_RD_n(W_CPU_RDn),
Expand Down Expand Up @@ -497,7 +498,7 @@ dkong_vram vram
.DL_ADDR(DL_ADDR),
.DL_WR(DL_WR),
.DL_DATA(DL_DATA),

.hs_address(hs_address),
.hs_data_in(hs_data_in),
.hs_data_out(hs_data_out_VRAM),
Expand Down Expand Up @@ -579,5 +580,5 @@ dkong_soundboard dkong_soundboard(
.WAV_ROM_A(WAV_ROM_A),
.WAV_ROM_DO(WAV_ROM_DO)
);

endmodule
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