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Add READMEs for tools that don't have one
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slang-hier | ||
========== | ||
A tool that can display information about a Verilog hierarchy. | ||
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This tool accepts the standard set of slang driver command line options, | ||
which lets you configure your design. Then the tool will display | ||
information like module instance names and resolved parameter values. | ||
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Additional options to control output: | ||
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`--params` | ||
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Include instance parameter values in the output. | ||
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`--max-depth <depth>` | ||
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The maximum instance depth of the hierarchy to be printed. | ||
Everything deeper than that will be ignored. | ||
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`--inst-prefix <prefix>` | ||
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A hierarchical path indicating which hierarchy to display. | ||
All parts of the design not under this prefix will be ignored. | ||
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`--inst-regex <regex>` | ||
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Only instances that match the given regex (anywhere in the design tree) | ||
will be shown. All others will be skipped. | ||
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`--custom-format <fmt>` | ||
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A libfmt style format string that controls how the output is printed. | ||
Use `{inst}`, `{module}`, `{file}` as argument names in the string. |
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rewriter | ||
======== | ||
A simple tool that shows using the syntax API to read in a source file, | ||
parse it, and write it back out again. This can be used for testing purposes, | ||
to make sure syntax trees round trip correctly, or as a basic example of | ||
working with the syntax API. | ||
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Usage: | ||
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``` | ||
rewriter <file-name> | ||
``` |
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# Slang Tidy | ||
# slang-tidy | ||
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A SystemVerilog linter | ||
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