Currently an undergrad Electrical Engineering student at SEECS, NUST.
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Classical-5-stage-pipelined-RISCV-Processor-In-Verilog
Classical-5-stage-pipelined-RISCV-Processor-In-Verilog PublicThis project is an implementation of a single core RISCV processor in verilog
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Temperature-Sensor-Using-AVR-ATmega
Temperature-Sensor-Using-AVR-ATmega PublicThis project is about implementing a temperature sensing unit using AVR ATmega16A microcontroller, and a simple machine learning algorithm to calibrate it
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