hw/riscv: sifive_e: Correct debug block size

Currently the debug region size is set to 0x100, but according to FE310-G000 and FE310-G002 manuals: FE310-G000: 0x100 - 0xFFF FE310-G002: 0x0 - 0xFFF Change the size to 0x1000 that applies to both. Signed-off-by: Bin Meng <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Message-Id: <[email protected]> Signed-off-by: Alistair Francis <[email protected]>
Mr-HappyLI · Jul 22, 2020 · e79d27c · e79d27c
1 parent 3e09396
commit e79d27c
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
@@ -54,7 +54,7 @@ static const struct MemmapEntry {
     hwaddr base;
     hwaddr size;
 } sifive_e_memmap[] = {
-    [SIFIVE_E_DEBUG] =    {        0x0,      0x100 },
+    [SIFIVE_E_DEBUG] =    {        0x0,     0x1000 },
     [SIFIVE_E_MROM] =     {     0x1000,     0x2000 },
     [SIFIVE_E_OTP] =      {    0x20000,     0x2000 },
     [SIFIVE_E_CLINT] =    {  0x2000000,    0x10000 },