Skip to content
View Mudassir10X's full-sized avatar

Block or report Mudassir10X

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Mudassir10X/README.md
  • 👋 Hi, I’m Syed Mudassir Ali
  • 👀 I’m interested in SAIL-ISA, Python, verilog/System-verilog, C, C++, Matlab, Arduino, RISCV
  • 🌱 I’m currently working on Fiverr as a freelancer
  • 💞️ I’m looking to collaborate on riscv/sail-riscv
  • 📫 How to reach me [email protected]
  • 😄 Pronouns: He/Him
  • ⚡ Fun fact: Ignorance is Blessing

Pinned Loading

  1. riscv-arch-test riscv-arch-test Public

    Forked from riscv-non-isa/riscv-arch-test

    Assembly

  2. RISCV-DV2B RISCV-DV2B Public

    Risc-v Privilege specs and csr tests

    Assembly 1

  3. sail-riscv sail-riscv Public

    Forked from riscv/sail-riscv

    Sail RISC-V model

    Coq

  4. riscv-non-isa/riscv-arch-test riscv-non-isa/riscv-arch-test Public

    Assembly 516 204

  5. riscv/sail-riscv riscv/sail-riscv Public

    Sail RISC-V model

    Coq 461 167