Weird CPU (WIP)

This is a simple proof of concept CPU made solely by myself. There might be still some bugs floating around.

Overview:

• 8bit Data Bus
• 16bit Data Address Bus
• 8bit I/O Address Bus
• 1 General Purpose, 1 Special Purpose Register
• Conditional / Unconditional Jump
• Indirect Addressing
• Zero Page Addressing
• 4 function ALU
• Memory-Mapped I/O (Separate Address)

Todo:

1. Update Emulator code to reflect the changes in Logisim-Evolution circuit
2. Enhance & clean-up the assembler

How does it looks like?