supports Vivado2023.2 and latest open-nic shell/driver

NetFPGA · Jan 14, 2024 · a105e56 · a105e56
1 parent f03b61c
commit a105e56
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diff --git a/RELEASE_NOTES b/RELEASE_NOTES
@@ -26,22 +26,12 @@
 #
 # @NETFPGA_LICENSE_HEADER_END@
 #
-GIT VERSION 1.0.0
+GIT VERSION 1.1.0
 
 This release contains:
 1. Designs
-  - reference design for L2 switch, router, nic on Alveo series FPGA cards
-    (e.g., U200, U250, U280) and VCU1525
-  - Linux driver (open-nic-driver), hardware testing and simulation enviroments are included.
-  - library cores to build reference_switch, reference_switch_lite, reference_router, 
-    reference_nic and simulation and hardware testings
+  - support Vivado 2023.2
+  - support OpenNIC Shell open-nic-shell (commit: 8077751)
+  - support OpenNIC Driver open-nic-driver (commit: cbac3b9)
 
-2. Notes
-  - For U280 board, please use 320MHz for reference_switch_lite project to fix timing closure,
-    and use 300MHz for reference_router project to fix timing closure
-    To change the running freq., please refer to each tcl file.
-    e.g., NetFPGA-PLUS/hw/projects/reference_switch_lite/hw/tcl/reference_switch_lite.tcl
-  - scone is not fully tested.
 
-3. Wiki
-  - Please refer to our wiki: https://github.com/NetFPGA/NetFPGA-PLUS/wiki
diff --git a/hw/lib/common/constraints/au200_general.xdc b/hw/lib/common/constraints/au200_general.xdc
@@ -136,6 +136,15 @@ set_property -dict { LOC T2 } [get_ports QSFP1_RX_P[1]]
 set_property -dict { LOC T1 } [get_ports QSFP1_RX_N[1]]
 set_property -dict { LOC U4 } [get_ports QSFP1_RX_P[0]]
 set_property -dict { LOC U3 } [get_ports QSFP1_RX_N[0]]
+
+
+# Satellite Core
+set_property -dict {PACKAGE_PIN BB19 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports satellite_uart_0_txd]
+set_property -dict {PACKAGE_PIN BA19 IOSTANDARD LVCMOS12}         [get_ports satellite_uart_0_rxd]
+set_property -dict {PACKAGE_PIN AR20 IOSTANDARD LVCMOS12}         [get_ports satellite_gpio[0]]
+set_property -dict {PACKAGE_PIN AM20 IOSTANDARD LVCMOS12}         [get_ports satellite_gpio[1]]
+set_property -dict {PACKAGE_PIN AM21 IOSTANDARD LVCMOS12}         [get_ports satellite_gpio[2]]
+set_property -dict {PACKAGE_PIN AN21 IOSTANDARD LVCMOS12}         [get_ports satellite_gpio[3]]
 ##########################################################################
 # Timing
 ##########################################################################

diff --git a/hw/lib/common/constraints/au200_vcu1525_timing.tcl b/hw/lib/common/constraints/au200_vcu1525_timing.tcl
@@ -15,6 +15,7 @@
 # limitations under the License.
 #
 # *************************************************************************
+create_clock -period 4.000 -name axis_aclk [get_nets u_top_wrapper/axis_aclk]
 set_false_path -through [get_ports pci_rst_n]
 
 set axis_aclk [get_clocks -of_object [get_nets u_top_wrapper/axis_aclk]]

diff --git a/hw/lib/common/constraints/au250_general.xdc b/hw/lib/common/constraints/au250_general.xdc
@@ -135,21 +135,31 @@ set_property -dict { LOC T2 } [get_ports QSFP1_RX_P[1]]
 set_property -dict { LOC T1 } [get_ports QSFP1_RX_N[1]]
 set_property -dict { LOC U4 } [get_ports QSFP1_RX_P[0]]
 set_property -dict { LOC U3 } [get_ports QSFP1_RX_N[0]]
+
+# Satellite Core
+set_property -dict {PACKAGE_PIN BB19 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports satellite_uart_0_txd]
+set_property -dict {PACKAGE_PIN BA19 IOSTANDARD LVCMOS12}         [get_ports satellite_uart_0_rxd]
+set_property -dict {PACKAGE_PIN AR20 IOSTANDARD LVCMOS12}         [get_ports satellite_gpio[0]]
+set_property -dict {PACKAGE_PIN AM20 IOSTANDARD LVCMOS12}         [get_ports satellite_gpio[1]]
+set_property -dict {PACKAGE_PIN AM21 IOSTANDARD LVCMOS12}         [get_ports satellite_gpio[2]]
+set_property -dict {PACKAGE_PIN AN21 IOSTANDARD LVCMOS12}         [get_ports satellite_gpio[3]]
 ##########################################################################
 # Timing
 ##########################################################################
-# CMAC user clock
-create_clock -period 3.103 -name cmac_clk_0 [get_pins -hier -filter name=~*cmac_port[0]*cmac_gtwiz_userclk_tx_inst/txoutclk_out[0]]
-create_clock -period 3.103 -name cmac_clk_1 [get_pins -hier -filter name=~*cmac_port[1]*cmac_gtwiz_userclk_tx_inst/txoutclk_out[0]]
+# axis_aclk needs to be specified
+create_clock -period 4.000 -name axis_aclk [get_pins -hier -filter name=~*u_top_wrapper/xilinx_nic_shell/axis_aclk]
 
-# Datapath Clock - 340MHz
+# Datapath Clock - 340MHz   (called core_clk internally apparently)
 create_clock -period 2.941 -name dp_clk [get_pins -hier -filter name=~*u_clk_wiz_1/clk_out1]
 
+# PCIe clock 100MHz
+create_clock -period 10.000 -name pcie_refclk [get_ports pci_clk_p]
+
 set_false_path -from [get_clocks axis_aclk] -to [get_clocks dp_clk]
 set_false_path -from [get_clocks dp_clk] -to [get_clocks axis_aclk]
-set_false_path -from [get_clocks cmac_clk_1] -to [get_clocks dp_clk]
-set_false_path -from [get_clocks dp_clk] -to [get_clocks cmac_clk_1]
-set_false_path -from [get_clocks cmac_clk_0] -to [get_clocks dp_clk]
-set_false_path -from [get_clocks dp_clk] -to [get_clocks cmac_clk_0]
+set_false_path -from [get_clocks dp_clk] -to [get_clocks {txoutclk_out[0]}]
+set_false_path -from [get_clocks {txoutclk_out[0]}] -to [get_clocks dp_clk]
+set_false_path -from [get_clocks dp_clk] -to [get_clocks {txoutclk_out[0]_1}]
+set_false_path -from [get_clocks {txoutclk_out[0]_1}] -to [get_clocks dp_clk]
 set_false_path -from [get_clocks clk_out1_qdma_subsystem_clk_div] -to [get_clocks axis_aclk]
 set_false_path -from [get_clocks dp_clk] -to [get_clocks clk_out1_qdma_subsystem_clk_div]
diff --git a/hw/lib/common/constraints/au250_timing.tcl b/hw/lib/common/constraints/au250_timing.tcl
@@ -15,6 +15,7 @@
 # limitations under the License.
 #
 # *************************************************************************
+# QDMA clock
 set_false_path -through [get_ports pci_rst_n]
 
 set axis_aclk [get_clocks -of_object [get_nets u_top_wrapper/axis_aclk]]

diff --git a/hw/lib/common/constraints/au280_general.xdc b/hw/lib/common/constraints/au280_general.xdc
@@ -67,8 +67,14 @@ set_property PACKAGE_PIN H30 [get_ports QSFP1_RESET]
 set_property IOSTANDARD LVCMOS18 [get_ports QSFP1_RESET]
 
 # HBM
-set_property PACKAGE_PIN D32 [get_ports STAT_CATTRIP]
-set_property IOSTANDARD LVCMOS18 [get_ports STAT_CATTRIP]
+set_property -dict {PACKAGE_PIN D32 IOSTANDARD LVCMOS18 PULLDOWN TRUE} [get_ports hbm_cattrip]
+
+set_property -dict {PACKAGE_PIN D29 IOSTANDARD LVCMOS18} [get_ports satellite_uart_0_txd]
+set_property -dict {PACKAGE_PIN E28 IOSTANDARD LVCMOS18} [get_ports satellite_uart_0_rxd]
+set_property -dict {PACKAGE_PIN K28 IOSTANDARD LVCMOS18} [get_ports satellite_gpio[0]]
+set_property -dict {PACKAGE_PIN J29 IOSTANDARD LVCMOS18} [get_ports satellite_gpio[1]]
+set_property -dict {PACKAGE_PIN K29 IOSTANDARD LVCMOS18} [get_ports satellite_gpio[2]]
+set_property -dict {PACKAGE_PIN J31 IOSTANDARD LVCMOS18} [get_ports satellite_gpio[3]]
 ##########################################################################
 # Timing
 ##########################################################################

diff --git a/hw/lib/common/constraints/au280_timing.tcl b/hw/lib/common/constraints/au280_timing.tcl
@@ -15,6 +15,7 @@
 # limitations under the License.
 #
 # *************************************************************************
+create_clock -period 4.000 -name axis_aclk [get_nets u_top_wrapper/axis_aclk]
 set_false_path -through [get_ports pci_rst_n]
 
 set axis_aclk [get_clocks -of_object [get_nets u_top_wrapper/axis_aclk]]

diff --git a/hw/lib/common/constraints/vcu1525_general.xdc b/hw/lib/common/constraints/vcu1525_general.xdc
@@ -133,6 +133,14 @@ set_property -dict { LOC T2 } [get_ports QSFP1_RX_P[1]]
 set_property -dict { LOC T1 } [get_ports QSFP1_RX_N[1]]
 set_property -dict { LOC U4 } [get_ports QSFP1_RX_P[0]]
 set_property -dict { LOC U3 } [get_ports QSFP1_RX_N[0]]
+
+# Satellite Core
+set_property -dict {PACKAGE_PIN BB19 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports satellite_uart_0_txd]
+set_property -dict {PACKAGE_PIN BA19 IOSTANDARD LVCMOS12}         [get_ports satellite_uart_0_rxd]
+set_property -dict {PACKAGE_PIN AR20 IOSTANDARD LVCMOS12}         [get_ports satellite_gpio[0]]
+set_property -dict {PACKAGE_PIN AM20 IOSTANDARD LVCMOS12}         [get_ports satellite_gpio[1]]
+set_property -dict {PACKAGE_PIN AM21 IOSTANDARD LVCMOS12}         [get_ports satellite_gpio[2]]
+set_property -dict {PACKAGE_PIN AN21 IOSTANDARD LVCMOS12}         [get_ports satellite_gpio[3]]
 ##########################################################################
 # Timing
 ##########################################################################

diff --git a/hw/lib/common/hdl/nf_attachment.sv b/hw/lib/common/hdl/nf_attachment.sv
@@ -271,7 +271,7 @@ module nf_attachment #(
   wire             S2_AXI_BVALID,   S1_AXI_BVALID,   S0_AXI_BVALID;
   wire             S2_AXI_AWREADY,  S1_AXI_AWREADY,  S0_AXI_AWREADY;
 
-  axi_crossbar_0 u_crossbar_m0 (
+  axi_crossbar_1 u_crossbar_m1 (
     .aclk          (axil_aclk),
     .aresetn       (!axil_rst),
     .s_axi_awaddr  (m0_axil_awaddr ),

diff --git a/hw/lib/common/hdl/top.v b/hw/lib/common/hdl/top.v
@@ -36,8 +36,34 @@ module top #(
 	parameter NF_C_S_AXI_DATA_WIDTH        = 32,
 	parameter NF_C_S_AXI_ADDR_WIDTH        = 32
 )(	
-`ifdef BOARD_AU280
-	output wire STAT_CATTRIP,
+`ifdef __au280__
+	output wire                    hbm_cattrip,
+	input  wire              [3:0] satellite_gpio,
+`elsif __au50__
+	output wire                    hbm_cattrip,
+	input  wire              [1:0] satellite_gpio,
+`elsif __au55n__
+	output wire                    hbm_cattrip,
+	input  wire              [3:0] satellite_gpio,
+`elsif __au55c__
+	output wire                    hbm_cattrip,
+	input  wire              [3:0] satellite_gpio,
+`elsif __au200__
+	//output                   [1:0] qsfp_resetl,
+	//input                    [1:0] qsfp_modprsl,
+	//input                    [1:0] qsfp_intl,
+	//output                   [1:0] qsfp_lpmode,
+	//output                   [1:0] qsfp_modsell,
+	input  wire              [3:0] satellite_gpio,
+`elsif __au250__
+	//output                   [1:0] qsfp_resetl,
+	//input                    [1:0] qsfp_modprsl,
+	//input                    [1:0] qsfp_intl,
+	//output                   [1:0] qsfp_lpmode,
+	//output                   [1:0] qsfp_modsell,
+	input  wire              [3:0] satellite_gpio,
+`elsif __au45n__
+	input  wire              [1:0] satellite_gpio,
 `endif
 	input wire QSFP0_CLOCK_P,
 	input wire QSFP0_CLOCK_N,
@@ -82,6 +108,10 @@ module top #(
 	input  wire [3:0] QSFP1_RX_P,
 	input  wire [3:0] QSFP1_RX_N,
 
+	// Satellite core
+	input  wire       satellite_uart_0_rxd,
+	output wire       satellite_uart_0_txd,
+
 	input  wire         sysclk_p,
 	input  wire         sysclk_n,
 
@@ -95,9 +125,9 @@ module top #(
 	input  wire [15:0]  pcie_rxn
 );
 
-`ifdef BOARD_AU280
-  assign STAT_CATTRIP = 1'b0;
-`endif 
+//`ifdef BOARD_AU280
+//  assign STAT_CATTRIP = 1'b0;
+//`endif 
 
 `ifndef BOARD_AU280
   // QSFP Clock for 156.25MHz (2'b01)
@@ -505,6 +535,35 @@ module top #(
     .C_TDATA_WIDTH    (C_IF_DATA_WIDTH),
     .C_TUSER_WIDTH    (C_IF_TUSER_WIDTH)
   ) u_top_wrapper (
+`ifdef __au280__
+    .hbm_cattrip    (hbm_cattrip   ),
+    .satellite_gpio (satellite_gpio),
+`elsif __au50__
+    .hbm_cattrip    (hbm_cattrip   ),
+    .satellite_gpio (satellite_gpio),
+`elsif __au55n__
+    .hbm_cattrip    (hbm_cattrip   ),
+    .satellite_gpio (satellite_gpio),
+`elsif __au55c__
+    .hbm_cattrip    (hbm_cattrip   ),
+    .satellite_gpio (satellite_gpio),
+`elsif __au200__
+    .qsfp_resetl    (/*qsfp_resetl   */),
+    .qsfp_modprsl   (/*qsfp_modprsl  */),
+    .qsfp_intl      (/*qsfp_intl     */),
+    .qsfp_lpmode    (/*qsfp_lpmode   */),
+    .qsfp_modsell   (/*qsfp_modsell  */),
+    .satellite_gpio (satellite_gpio),
+`elsif __au250__
+    .qsfp_resetl    (/*qsfp_resetl   */),
+    .qsfp_modprsl   (/*qsfp_modprsl  */),
+    .qsfp_intl      (/*qsfp_intl     */),
+    .qsfp_lpmode    (/*qsfp_lpmode   */),
+    .qsfp_modsell   (/*qsfp_modsell  */),
+    .satellite_gpio (satellite_gpio),
+`elsif __au45n__
+    .satellite_gpio (satellite_gpio),
+`endif
     // QSFP port0
     .qsfp0_rxp         (QSFP0_RX_P),
     .qsfp0_rxn         (QSFP0_RX_N),
@@ -530,6 +589,9 @@ module top #(
     .pcie_clk_p        (pci_clk_p),
     .pcie_clk_n        (pci_clk_n),
     .pcie_rst_n        (pci_rst_n),
+    // Satellite core
+    .satellite_uart_0_rxd(satellite_uart_0_rxd),
+    .satellite_uart_0_txd(satellite_uart_0_txd),
 
     .m_axil_awvalid    (m_axil_awvalid),
     .m_axil_awaddr     (m_axil_awaddr ),

diff --git a/hw/lib/common/hdl/top_wrapper.sv b/hw/lib/common/hdl/top_wrapper.sv
@@ -29,6 +29,35 @@ module top_wrapper #(
 	parameter C_TDATA_WIDTH    = 512,
 	parameter C_TUSER_WIDTH    = 128
 )(
+`ifdef __au280__
+	output                         hbm_cattrip,
+	input                    [3:0] satellite_gpio,
+`elsif __au50__
+	output                         hbm_cattrip,
+	input                    [1:0] satellite_gpio,
+`elsif __au55n__
+	output                         hbm_cattrip,
+	input                    [3:0] satellite_gpio,
+`elsif __au55c__
+	output                         hbm_cattrip,
+	input                    [3:0] satellite_gpio,
+`elsif __au200__
+	output                   [1:0] qsfp_resetl,
+	input                    [1:0] qsfp_modprsl,
+	input                    [1:0] qsfp_intl,
+	output                   [1:0] qsfp_lpmode,
+	output                   [1:0] qsfp_modsell,
+	input                    [3:0] satellite_gpio,
+`elsif __au250__
+	output                   [1:0] qsfp_resetl,
+	input                    [1:0] qsfp_modprsl,
+	input                    [1:0] qsfp_intl,
+	output                   [1:0] qsfp_lpmode,
+	output                   [1:0] qsfp_modsell,
+	input                    [3:0] satellite_gpio,
+`elsif __au45n__
+	input                    [1:0] satellite_gpio,
+`endif
 	// QSFP port0
 	input  [3:0]                  qsfp0_rxp,
 	input  [3:0]                  qsfp0_rxn,
@@ -55,6 +84,10 @@ module top_wrapper #(
 	input                         pcie_clk_n,
 	input                         pcie_rst_n,
 
+	// Satellite core
+	input                         satellite_uart_0_rxd,
+	output                        satellite_uart_0_txd,
+
 	output                        m_axil_awvalid,
 	output                 [31:0] m_axil_awaddr,
 	input                         m_axil_awready,
@@ -399,6 +432,39 @@ module top_wrapper #(
     .qsfp_txn      ({qsfp1_txn, qsfp0_txn}),
     .qsfp_refclk_p ({qsfp1_clk_p, qsfp0_clk_p}),
     .qsfp_refclk_n ({qsfp1_clk_n, qsfp0_clk_n}),
+
+    .satellite_uart_0_rxd(satellite_uart_0_rxd),
+    .satellite_uart_0_txd(satellite_uart_0_txd),
+`ifdef __au280__
+    .hbm_cattrip    (hbm_cattrip   ),
+    .satellite_gpio (satellite_gpio),
+`elsif __au50__
+    .hbm_cattrip    (hbm_cattrip   ),
+    .satellite_gpio (satellite_gpio),
+`elsif __au55n__
+    .hbm_cattrip    (hbm_cattrip   ),
+    .satellite_gpio (satellite_gpio),
+`elsif __au55c__
+    .hbm_cattrip    (hbm_cattrip   ),
+    .satellite_gpio (satellite_gpio),
+`elsif __au200__
+    .qsfp_resetl    (qsfp_resetl   ),
+    .qsfp_modprsl   (qsfp_modprsl  ),
+    .qsfp_intl      (qsfp_intl     ),
+    .qsfp_lpmode    (qsfp_lpmode   ),
+    .qsfp_modsell   (qsfp_modsell  ),
+    .satellite_gpio (satellite_gpio),
+`elsif __au250__
+    .qsfp_resetl    (qsfp_resetl   ),
+    .qsfp_modprsl   (qsfp_modprsl  ),
+    .qsfp_intl      (qsfp_intl     ),
+    .qsfp_lpmode    (qsfp_lpmode   ),
+    .qsfp_modsell   (qsfp_modsell  ),
+    .satellite_gpio (satellite_gpio),
+`elsif __au45n__
+    .satellite_gpio (satellite_gpio),
+`endif
+
 `else // !`ifdef __synthesis__
     .s_axil_awvalid (),
     .s_axil_awaddr  (),

diff --git a/hw/lib/xilinx/cam_v1_1_0/cam.tcl b/hw/lib/xilinx/cam_v1_1_0/cam.tcl
@@ -31,9 +31,10 @@ set   lib_name       xilinx
 set   ip_version     1.1
 set   design         cam
 
-set device $::env(DEVICE)
+set   device         $::env(DEVICE)
 set   proj_dir       ip_proj
 
+set_param board.repoPaths $::env(BOARD_FILE_PATH)
 # Project setting
 create_project -name ${design} -force -dir "./${proj_dir}" -part ${device} -ip
 

diff --git a/hw/lib/xilinx/tcam_v1_1_0/tcam.tcl b/hw/lib/xilinx/tcam_v1_1_0/tcam.tcl
@@ -33,6 +33,7 @@ set   design         tcam
 set   device         $::env(DEVICE)
 set   proj_dir       ip_proj
 
+set_param board.repoPaths $::env(BOARD_FILE_PATH)
 # Project setting
 create_project -name ${design} -force -dir "./${proj_dir}" -part ${device} -ip